coreboot-gerrit February 2024

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[M] Change in coreboot[main]: mb/amd/birman: add Phoenix with openSIL mainboard option
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Fred Reitberger, Jason Glenesk. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80299?usp=email ) Change subject: mb/amd/birman: add Phoenix with openSIL mainboard option ...................................................................... mb/amd/birman: add Phoenix with openSIL mainboard option Introduce BOARD_AMD_BIRMAN_PHOENIX_OPENSIL which selects the openSIL based Phoenix SoC code. Since the Phoenix chip.c is different due to some FSP-specific data structures in there that are guarded in the openSIL case, a separate devicetree for the openSIL case is added. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7 --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Kconfig.name R src/mainboard/amd/birman/devicetree_phoenix_fsp.cb A src/mainboard/amd/birman/devicetree_phoenix_opensil.cb 4 files changed, 155 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/80299/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index cd7e938..9fafae1 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -19,6 +19,10 @@ select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_PHOENIX_FSP +config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL + select BOARD_AMD_BIRMAN_COMMON + select SOC_AMD_PHOENIX_OPENSIL + config BOARD_AMD_BIRMAN_GLINDA select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_GLINDA @@ -27,7 +31,7 @@ config FMDFILE default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA - default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX_FSP + default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS default "src/mainboard/amd/birman/board_glinda.fmd" if BOARD_AMD_BIRMAN_GLINDA default "src/mainboard/amd/birman/board_phoenix.fmd" @@ -37,10 +41,12 @@ config MAINBOARD_PART_NUMBER default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA default "Birman_Phoenix_FSP" if BOARD_AMD_BIRMAN_PHOENIX_FSP + default "Birman_Phoenix_openSIL" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL config DEVICETREE default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA - default "devicetree_phoenix.cb" + default "devicetree_phoenix_fsp.cb" if BOARD_AMD_BIRMAN_PHOENIX_FSP + default "devicetree_phoenix_opensil.cb" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL config BIRMAN_HAVE_MCHP_FW bool "Have Microchip EC firmware?" diff --git a/src/mainboard/amd/birman/Kconfig.name b/src/mainboard/amd/birman/Kconfig.name index 9eee171..6daea88 100644 --- a/src/mainboard/amd/birman/Kconfig.name +++ b/src/mainboard/amd/birman/Kconfig.name @@ -3,5 +3,8 @@ config BOARD_AMD_BIRMAN_PHOENIX_FSP bool "-> Birman for Phoenix SoC using FSP" +config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL + bool "-> Birman for Phoenix SoC using openSIL" + config BOARD_AMD_BIRMAN_GLINDA bool "-> Birman for Glinda SoC" diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb similarity index 100% rename from src/mainboard/amd/birman/devicetree_phoenix.cb rename to src/mainboard/amd/birman/devicetree_phoenix_fsp.cb diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb new file mode 100644 index 0000000..58cead5 --- /dev/null +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# TODO: Update for birman + +chip soc/amd/phoenix + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x3f8, + .size = 8, + }, + .generic_io_range[1] = { + .base = 0x600, + .size = 256, + }, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "i2c[0].early_init" = "1" + register "i2c[1].early_init" = "1" + register "i2c[2].early_init" = "1" + register "i2c[3].early_init" = "1" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" + + register "s0ix_enable" = "true" + + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works< + + device domain 0 on + device ref iommu on end + device ref gpp_bridge_1_1 on end # MXM + device ref gpp_bridge_1_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD1 + device ref gpp_bridge_1_3 on end # GBE + device ref gpp_bridge_2_1 on end # SD + device ref gpp_bridge_2_2 on end # WWAN + device ref gpp_bridge_2_3 on end # WIFI + device ref gpp_bridge_2_4 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD0 + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port6 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port7 on end + end + chip drivers/usb/acpi + device ref usb2_port7 on end + end + end + end + end + device ref acp on end # Audio Processor (ACP) + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref usb4_xhci_0 on + chip drivers/usb/acpi + device ref usb4_xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port0 on end + end + end + end + end + device ref usb4_xhci_1 on + chip drivers/usb/acpi + device ref usb4_xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port1 on end + end + chip drivers/usb/acpi + device ref usb2_port1 on end + end + end + end + end + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + device ref uart_0 on end # UART0 + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/80299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7 Gerrit-Change-Number: 80299 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/phoenix/chip.h: guard FSP-specific data structures
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

1 0

[S] Change in coreboot[main]: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

1 0

[S] Change in coreboot[main]: soc/amd/phoenix: add openSIL calls
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80296?usp=email ) Change subject: soc/amd/phoenix: add openSIL calls ...................................................................... soc/amd/phoenix: add openSIL calls Add the calls to the openSIL stubs to do the silicon initialization, to get the APCI IO ports, and to get the memory map. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c --- M src/soc/amd/phoenix/acpi.c M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/memmap.c 3 files changed, 20 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/80296/1 diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index a6482ee..606a45f 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <soc/iomap.h> #include <types.h> +#include <vendorcode/amd/opensil/genoa_poc/opensil.h> #include "chip.h" /* @@ -29,12 +30,17 @@ { const struct soc_amd_phoenix_config *cfg = config_of_soc(); - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); + if (CONFIG(PLATFORM_USES_FSP2_0)) { + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + } else { + /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */ + opensil_fill_fadt_io_ports(fadt); + } fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index 2291945..a9b0e57 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -12,6 +12,7 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> +#include <vendorcode/amd/opensil/stub/opensil.h> #include "chip.h" static const char *soc_acpi_name(const struct device *dev) @@ -39,8 +40,12 @@ { default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; - if (CONFIG(PLATFORM_USES_FSP2_0)) + if (CONFIG(PLATFORM_USES_FSP2_0)) { amd_fsp_silicon_init(); + } else { + setup_opensil(); + opensil_xSIM_timepoint_1(); + } data_fabric_set_mmio_np(); diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c index 432d850..e516572 100644 --- a/src/soc/amd/phoenix/memmap.c +++ b/src/soc/amd/phoenix/memmap.c @@ -7,6 +7,7 @@ #include <cbmem.h> #include <device/device.h> #include <stdint.h> +#include <vendorcode/amd/opensil/stub/opensil.h> /* * +--------------------------------+ @@ -96,4 +97,6 @@ if (CONFIG(PLATFORM_USES_FSP2_0)) read_fsp_resources(dev, idx); + else + add_opensil_memmap(dev, idx); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c Gerrit-Change-Number: 80296 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

1 0

[S] Change in coreboot[main]: soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80294?usp=email ) Change subject: soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case ...................................................................... soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case In the FSP case we get this info via a HOB. It's currently unclear if we'll get a data structure for this from openSIL or if we'll end up being able to just read the configuration fro the hardware, so add a get_pci_routing_table stub for now to be able to build. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14 --- M src/soc/amd/phoenix/Makefile.mk A src/soc/amd/phoenix/pci_irq_routing.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/80294/1 diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index 9c775cc..be0a022 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -32,6 +32,7 @@ ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += memmap.c +ramstage-$(CONFIG_SOC_AMD_PHOENIX_OPENSIL) += pci_irq_routing.c ramstage-y += root_complex.c ramstage-y += soc_util.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/pci_irq_routing.c b/src/soc/amd/phoenix/pci_irq_routing.c new file mode 100644 index 0000000..5c891c2 --- /dev/null +++ b/src/soc/amd/phoenix/pci_irq_routing.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_util.h> +#include <console/console.h> +#include <types.h> + +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + /* TODO: still needs to be implemented for the non-FSP case */ + printk(BIOS_NOTICE, "%s stub: returning empty IRQ routing table\n", __func__); + + *entries = 0; + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14 Gerrit-Change-Number: 80294 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80293?usp=email ) Change subject: soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option ...................................................................... soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option Add the SOC_AMD_PHOENIX_OPENSIL Kconfig option to be able to build the Phoenix code using openSIL instead of FSP for initializing the hardware. Since there's currently no publicly available openSIL code for Phoenix, SOC_AMD_OPENSIL_STUB is selected to have the stubs added to the build instead of the actual openSIL code. The code added by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPPC relies on getting the information it needs via a HOB, so for only select that option in the FSP case for now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If597ff3dc824ce832399d3efde32352b36354b21 --- M src/soc/amd/phoenix/Kconfig 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/80293/1 diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index fd40231..f37dd20 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -29,7 +29,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_ACPI_CPPC + select SOC_AMD_COMMON_BLOCK_ACPI_CPPC if !SOC_AMD_PHOENIX_OPENSIL # TODO: add support for openSIL case select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct @@ -100,6 +100,12 @@ help AMD Phoenix support using FSP +config SOC_AMD_PHOENIX_OPENSIL + bool + select SOC_AMD_PHOENIX_BASE + select SOC_AMD_OPENSIL + select SOC_AMD_OPENSIL_STUB + if SOC_AMD_PHOENIX_BASE config CHIPSET_DEVICETREE -- To view, visit https://review.coreboot.org/c/coreboot/+/80293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If597ff3dc824ce832399d3efde32352b36354b21 Gerrit-Change-Number: 80293 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: vc/amd/opensil: add openSIL stub implementation
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80292?usp=email ) Change subject: vc/amd/opensil: add openSIL stub implementation ...................................................................... vc/amd/opensil: add openSIL stub implementation Add a stub implementation of the openSIL interface between coreboot and vendorcode. This can be used to add most of the coreboot-side support for a SoC using openSIL without the actual opnSIL code already being publicly available. Once the corresponding openSIL code is available, the SoC can then switch over to using the actual openSIL implementation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0 --- M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/Makefile.mk A src/vendorcode/amd/opensil/stub/Makefile.mk A src/vendorcode/amd/opensil/stub/opensil.h A src/vendorcode/amd/opensil/stub/ramstage.c A src/vendorcode/amd/opensil/stub/romstage.c 6 files changed, 97 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/80292/1 diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig index bc80b8c..f0a303c 100644 --- a/src/vendorcode/amd/opensil/Kconfig +++ b/src/vendorcode/amd/opensil/Kconfig @@ -2,6 +2,13 @@ if SOC_AMD_OPENSIL +config SOC_AMD_OPENSIL_STUB + bool + help + Select this option to include the openSIL stub in the build that can + be used for build-testing before the actual openSIL source code for a + SoC is released. + config SOC_AMD_OPENSIL_GENOA_POC bool help diff --git a/src/vendorcode/amd/opensil/Makefile.mk b/src/vendorcode/amd/opensil/Makefile.mk index a97bf63..3e8661d 100644 --- a/src/vendorcode/amd/opensil/Makefile.mk +++ b/src/vendorcode/amd/opensil/Makefile.mk @@ -2,6 +2,12 @@ ifeq ($(CONFIG_SOC_AMD_OPENSIL),y) +ifeq ($(CONFIG_SOC_AMD_OPENSIL_STUB),y) + +subdirs-y += stub + +else # CONFIG_SOC_AMD_OPENSIL_STUB + ifneq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) $(error OpenSIL can only be built for either x86 or x86_64) endif @@ -90,4 +96,6 @@ romstage-libs += $(OBJPATH)/opensil.a ramstage-libs += $(OBJPATH)/opensil.a -endif +endif # CONFIG_SOC_AMD_OPENSIL_STUB + +endif # CONFIG_SOC_AMD_OPENSIL diff --git a/src/vendorcode/amd/opensil/stub/Makefile.mk b/src/vendorcode/amd/opensil/stub/Makefile.mk new file mode 100644 index 0000000..29ef421 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += romstage.c + +ramstage-y += ramstage.c \ No newline at end of file diff --git a/src/vendorcode/amd/opensil/stub/opensil.h b/src/vendorcode/amd/opensil/stub/opensil.h new file mode 100644 index 0000000..caa7b13 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/opensil.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _OPENSIL_H_ +#define _OPENSIL_H_ + +#include <acpi/acpi.h> + +// Add the memory map to dev, starting at index idx, returns last use idx +void add_opensil_memmap(struct device *dev, unsigned long *idx); +// Fill in FADT from openSIL +void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); + +void setup_opensil(void); +void opensil_xSIM_timepoint_1(void); +void opensil_xSIM_timepoint_2(void); +void opensil_xSIM_timepoint_3(void); + +#endif diff --git a/src/vendorcode/amd/opensil/stub/ramstage.c b/src/vendorcode/amd/opensil/stub/ramstage.c new file mode 100644 index 0000000..33ca447 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/ramstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <device/device.h> +#include "opensil.h" + +void add_opensil_memmap(struct device *dev, unsigned long *idx) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void setup_opensil(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_xSIM_timepoint_1(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_xSIM_timepoint_2(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_xSIM_timepoint_3(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} diff --git a/src/vendorcode/amd/opensil/stub/romstage.c b/src/vendorcode/amd/opensil/stub/romstage.c new file mode 100644 index 0000000..36dff95 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/romstage.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include <inttypes.h> + +uintptr_t cbmem_top_chipset(void) +{ + /* Since the stub doesn't have the openSIL function xPrfGetLowUsableDramAddress to + call, we just use 0xc0000000 here which should be a usable value in most cases */ + uintptr_t top_mem = 0xc0000000; + + printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, top_mem); + + /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so + account for potentially ill aligned TOP_MEM. */ + if (CONFIG_SMM_TSEG_SIZE) { + top_mem -= CONFIG_SMM_TSEG_SIZE; + top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE); + } + + return top_mem; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0 Gerrit-Change-Number: 80292 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/common/amdblocks/pci_clk_req: remove unneeded include
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

1 0

[S] Change in coreboot[main]: mb/amd/birman: add _FSP postfix to BOARD_AMD_BIRMAN_PHOENIX
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Fred Reitberger, Jason Glenesk. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80290?usp=email ) Change subject: mb/amd/birman: add _FSP postfix to BOARD_AMD_BIRMAN_PHOENIX ...................................................................... mb/amd/birman: add _FSP postfix to BOARD_AMD_BIRMAN_PHOENIX Rename the BOARD_AMD_BIRMAN_PHOENIX option to BOARD_AMD_BIRMAN_PHOENIX_FSP to distinguish between the FSP-based SoC initialization and the non-FSP based one. Also change the MAINBOARD_PART_NUMBER string to 'Birman_Phoenix_FSP'. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id3293a07cd1b1833df15ee0a40cad3127e19b7df --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Kconfig.name M src/mainboard/amd/birman/Makefile.mk 3 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/80290/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 3b9d607..cd7e938 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -15,7 +15,7 @@ select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE -config BOARD_AMD_BIRMAN_PHOENIX +config BOARD_AMD_BIRMAN_PHOENIX_FSP select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_PHOENIX_FSP @@ -27,7 +27,7 @@ config FMDFILE default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA - default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX + default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX_FSP default "src/mainboard/amd/birman/board_glinda.fmd" if BOARD_AMD_BIRMAN_GLINDA default "src/mainboard/amd/birman/board_phoenix.fmd" @@ -36,7 +36,7 @@ config MAINBOARD_PART_NUMBER default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA - default "Birman_Phoenix" + default "Birman_Phoenix_FSP" if BOARD_AMD_BIRMAN_PHOENIX_FSP config DEVICETREE default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA diff --git a/src/mainboard/amd/birman/Kconfig.name b/src/mainboard/amd/birman/Kconfig.name index c02173c..9eee171 100644 --- a/src/mainboard/amd/birman/Kconfig.name +++ b/src/mainboard/amd/birman/Kconfig.name @@ -1,7 +1,7 @@ comment "Birman" -config BOARD_AMD_BIRMAN_PHOENIX - bool "-> Birman for Phoenix SoC" +config BOARD_AMD_BIRMAN_PHOENIX_FSP + bool "-> Birman for Phoenix SoC using FSP" config BOARD_AMD_BIRMAN_GLINDA bool "-> Birman for Glinda SoC" diff --git a/src/mainboard/amd/birman/Makefile.mk b/src/mainboard/amd/birman/Makefile.mk index 4dba53e..6c417ce 100644 --- a/src/mainboard/amd/birman/Makefile.mk +++ b/src/mainboard/amd/birman/Makefile.mk @@ -4,12 +4,12 @@ bootblock-y += early_gpio.c bootblock-y += ec.c -romstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX) += port_descriptors_phoenix.c +romstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c ramstage-y += chromeos.c ramstage-y += gpio.c -ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX) += port_descriptors_phoenix.c +ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FP8_LPDDR5.bin),) -- To view, visit https://review.coreboot.org/c/coreboot/+/80290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3293a07cd1b1833df15ee0a40cad3127e19b7df Gerrit-Change-Number: 80290 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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