coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

1 participants
3067 discussions

[M] Change in coreboot[main]: mb/google/brya/var/xol: Update GPIO configurations
by SH Kim (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80325?usp=email ) Change subject: mb/google/brya/var/xol: Update GPIO configurations ...................................................................... mb/google/brya/var/xol: Update GPIO configurations Upload initial GPIO configuration for xol based on proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage xol proto board can boot to ChromeOS Change-Id: I224e58628e44571c07ce034136d690587e62be08 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- A src/mainboard/google/brya/variants/xol/Makefile.mk A src/mainboard/google/brya/variants/xol/gpio.c 2 files changed, 220 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/80325/1 diff --git a/src/mainboard/google/brya/variants/xol/Makefile.mk b/src/mainboard/google/brya/variants/xol/Makefile.mk new file mode 100644 index 0000000..91f031e --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c new file mode 100644 index 0000000..7ded00b --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_overrides[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> PU 100K 3.3V */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A16 : USB_OC3# ==> NC */ + PAD_NC(GPP_A16, NONE), + /* A17 : DISP_MISCC ==> EN_WCAM_PWR */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : PROC_GP3 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : ISH_I2C0_SDA ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_SCL ==> NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_B8, NONE), + /* B9 : NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : PMCALERT# ==> NC */ + PAD_NC(GPP_B11, NONE), + /* B15 : TIME_SYNC0 ==> PU 100K 3.3V */ + PAD_CFG_GPI(GPP_B15, NONE, DEEP), + + /* C0 : SMBCLK ==> NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D5 : SRCCLKREQ0# ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_D5, NONE, DEEP), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> PU 100K 3.3V */ + PAD_CFG_GPI(GPP_D8, NONE, DEEP), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + /* D17 : UART1_RXD ==> PU 100K 3.3V */ + PAD_CFG_GPI(GPP_D17, NONE, DEEP), + /* D18 : UART1_TXD ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_E3, NONE, DEEP), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E7 : PROC_GP1 ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E10 : THC0_SPI1_CS# ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_E17, NONE, DEEP), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F15 : GSXSRESET# ==> PU 100K 3.3V */ + PAD_CFG_GPI(GPP_F15, NONE, DEEP), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_F21, NONE, DEEP), + + /* H3 : SX_EXIT_HOLDOFF# ==> NC */ + PAD_NC(GPP_H3, NONE), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : I2C7_SDA ==> PU 100K 3.3V */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H19 : SRCCLKREQ4# ==> PU 100K 1.8V */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> PU 100K 3.3V */ + PAD_CFG_GPI(GPP_H23, NONE, DEEP), + + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD8: SUSCLK ==> NC */ + PAD_NC(GPD8, NONE), + /* GPD9: SLP_WLAN# ==> NC */ + PAD_NC(GPD9, NONE), + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_overrides); + return gpio_overrides; + +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80325?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I224e58628e44571c07ce034136d690587e62be08 Gerrit-Change-Number: 80325 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/google/brya/var/xol: Update devicetree
by SH Kim (Code Review) 01 Feb '24

01 Feb '24

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80324?usp=email ) Change subject: mb/google/brya/var/xol: Update devicetree ...................................................................... mb/google/brya/var/xol: Update devicetree Upload the initial devicetree for xol following proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot Change-Id: I411932eb4872d77993394a290e8afdd1a0038faf Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xol/overridetree.cb 1 file changed, 433 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/80324/1 diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 4f2c04a..fc10847 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -1,6 +1,437 @@ + chip soc/intel/alderlake + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .enable_fast_vmode = 1, + }" - device domain 0 on - end + register "sagv" = "SaGv_Enabled" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_DEFAULT" + + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "disable_dynamic_tccold_handshake" = "true" + + register "platform_pmax" = "145" + + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC0, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, + }" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, + }" # USB2_C2 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # uSD + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_11P25MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # USB2_A1 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # Camera + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_EMPTY" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_A1 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" + + register "tcss_aux_ori" = "0x11" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A19, .pad_auxn_dc = GPP_A20}" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + # Enable HDMI in PortB, HDMI/DP in Port1, Port2 + #register "ddi_ports_config" = "{ + # [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + # //[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + # //[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + #}" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0]= { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 175, + .fall_time_ns = 8, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD"" + # DDIB for HDMI + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 40), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 40), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(82, 97), + TEMP_PCT(78, 93), + TEMP_PCT(72, 86), + TEMP_PCT(60, 80), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 1 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 1, + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end # SSD + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref tbt_pcie_rp3 off end + device ref tcss_dma0 off end + device ref tcss_dma1 off end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "btn_cfg" = "50" + register "mic_det_thr" = "200" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end #I2C1 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ZNT0000"" + register "generic.desc" = ""Zinitix Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0xE" + device i2c 40 on end + end + end #I2C5 + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "da7219" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 MMC"" + register "type" = "UPC_TYPE_EXPRESSCARD" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port3 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/80324?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I411932eb4872d77993394a290e8afdd1a0038faf Gerrit-Change-Number: 80324 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
by Jérémy Compostella (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tim Chu, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80277?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits ...................................................................... Patch Set 4: (16 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80277/comment/62a62a86_bb8be310 : PS2, Line 39: In addition, this commit sets`PLATFORM_USES_FSP2_X86_32' to `n' by : default if FSP 2.4 is enabled as 64-bits FSP should be norm moving : forward. > Maybe make that a separate commit, so it also gets more exposure. Done File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/80277/comment/2422e2f8_a78ceff5 : PS2, Line 62: Starting with FSP specification 2.4 they can be 64-bits. > i thought u said elsewhere that FSP 2.4 also supports 32-bit? […] `they can be 64-bits` does not mean they cannot be 32-bits Would not the following work in a soc Kconfig ? ``` config PLATFORM_USES_FSP2_X86_32 default n ``` File src/drivers/intel/fsp2_0/debug.c: https://review.coreboot.org/c/coreboot/+/80277/comment/3367aecb_78ee0292 : PS2, Line 94: efi_return_status_t > need to include `#include <efi/efi_datatype. […] This is already include throught the `fsp/util.h`. Also if I included in the right alphabetical order then I will hit a EFIAPI is already defined issue as EDK headers are defining it if not already and soc_binding.h will try to define it appropriately after that. https://review.coreboot.org/c/coreboot/+/80277/comment/b1a9fede_b9724649 : PS2, Line 97: status > why not use `size_t status` directly ? I tried to use size_t but then it breaks due to some EFI_STATUS usage in some EDK2 prototype. Anyway, the use of `size_t` was nice but more like a hack. I moved to a helper function approach instead. File src/drivers/intel/fsp2_0/include/fsp/api.h: https://review.coreboot.org/c/coreboot/+/80277/comment/ffad1b94_701e8cc7 : PS2, Line 11: #define __efiapi EFIAPI > why not inside `efi_datatype. […] Done File src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h: https://review.coreboot.org/c/coreboot/+/80277/comment/630427a2_881c6c1f : PS2, Line 13: #include <efi/efi_datatype.h> > order ? Unfortunately, the order matter as soc_binding is in charge of defining EFIAPI appropriately. I added a comment. Let me know if you have a better suggestion. File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/80277/comment/745c9673_becabd8c : PS2, Line 39: #if CONFIG(PLATFORM_USES_FSP2_4) > look at line #36, i don;t think u need a guard here as well. […] Done File src/drivers/intel/fsp2_0/include/fsp/soc_binding.h: https://review.coreboot.org/c/coreboot/+/80277/comment/5e0a8959_6a1beecf : PS2, Line 8: #if CONFIG(VENDOR_INTEL) > why Intel? this is UEFI calling convention and nothing SoC vendor specific […] I "temporarily" added this to see if it would help with coreboot jenkins error on AMD platform.. I removed it. File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/80277/comment/5eec4725_6ea9ffa3 : PS2, Line 282: efi_return_status_t > size_t? Done File src/include/efi/efi_datatype.h: https://review.coreboot.org/c/coreboot/+/80277/comment/9a369a98_be788dfc : PS2, Line 81: statuses > ??? Done https://review.coreboot.org/c/coreboot/+/80277/comment/6e2563fe_89f26c8b : PS2, Line 88: _Static_assert(sizeof(size_t) == sizeof(efi_return_status_t), : "Unexpected EFI_STATUS size"); > if u use `size_t` over `efi_return_status_t` then I don't believe u need this logic Done File src/soc/intel/xeon_sp/bootblock.c: https://review.coreboot.org/c/coreboot/+/80277/comment/c9eee100_cf6f7c82 : PS2, Line 5: #include <fsp/util.h> > please submit this cl separately Done https://review.coreboot.org/c/coreboot/+/80277/comment/4bf8e945_9fe02f04 : PS2, Line 9: #include <soc/iomap.h> > same Done https://review.coreboot.org/c/coreboot/+/80277/comment/5ec24a9e_65567eef : PS2, Line 10: #include <console/console.h> : #include <cpu/x86/mtrr.h> > this is also out of order Done https://review.coreboot.org/c/coreboot/+/80277/comment/a0c62701_4b454012 : PS2, Line 12: #include <intelblocks/lpc_lib.h> > same Done https://review.coreboot.org/c/coreboot/+/80277/comment/e8ed2170_5a725d08 : PS2, Line 15: #include <soc/bootblock.h> > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99 Gerrit-Change-Number: 80277 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Feb 2024 00:47:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: commonlib: Add generic word-at-a-time optimization to ipchksum()
by Julius Werner (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80304?usp=email to look at the new patch set (#3). Change subject: commonlib: Add generic word-at-a-time optimization to ipchksum() ...................................................................... commonlib: Add generic word-at-a-time optimization to ipchksum() This patch adds a generic optimization to calculate a machine-word-sized "wide sum" for the ipchksum() algorithm. This is often not as efficient as handcrafted assembly (about half as fast on arm64 and x86_32, about the same speed on x86_64), but likely still much better than nothing on architectures that we don't have handcrafted assembly for. Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/ipchksum.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/80304/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80304?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694 Gerrit-Change-Number: 80304 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: commonlib: Add generic word-at-a-time optimization to ipchksum()
by Julius Werner (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80304?usp=email to look at the new patch set (#2). Change subject: commonlib: Add generic word-at-a-time optimization to ipchksum() ...................................................................... commonlib: Add generic word-at-a-time optimization to ipchksum() This patch adds a generic optimization to calculate a machine-word-sized "wide sum" for the ipchksum() algorithm. This is often not as efficient as handcrafted assembly (about half as fast on arm64 and x86_32, about the same speed on x86_64), but likely still much better than nothing on architectures that we don't have handcrafted assembly for. Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/ipchksum.c 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/80304/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80304?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694 Gerrit-Change-Number: 80304 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: commonlib: Add generic word-at-a-time optimization to ipchksum()
by Julius Werner (Code Review) 01 Feb '24

01 Feb '24

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80304?usp=email ) Change subject: commonlib: Add generic word-at-a-time optimization to ipchksum() ...................................................................... commonlib: Add generic word-at-a-time optimization to ipchksum() This patch adds a generic optimization to calculate a machine-word-sized "wide sum" for the ipchksum() algorithm. This is often not as efficient as handcrafted assembly (about half as fast on arm64 and x86_32, about the same speed on x86_64), but likely still much better than nothing on architectures that we don't have handcrafted assembly for. Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/ipchksum.c 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/80304/1 diff --git a/src/commonlib/bsd/ipchksum.c b/src/commonlib/bsd/ipchksum.c index b7434e5..8e0aa9b 100644 --- a/src/commonlib/bsd/ipchksum.c +++ b/src/commonlib/bsd/ipchksum.c @@ -34,7 +34,7 @@ :: "cc" ); } -#elif defined(__i386__) || defined(__x86_64__) +#elif defined(__i386__) || defined(__x86_64__) /* __aarch64__ */ size_t size8 = size / 8; const uint64_t *p8 = data; i = size8 * 8; @@ -57,7 +57,18 @@ [size8] "+c" (size8) /* put size in ECX so we can JECXZ */ :: "cc" ); -#endif /* __i386__ || __x86_64__ */ +#else /* __i386__ || __x86_64__ */ + size_t aligned_size = ALIGN_DOWN(size, sizeof(unsigned long)); + const unsigned long *p_long = data; + for (; i < aligned_size; i += sizeof(unsigned long)) { + unsigned long new = wide_sum + *p_long++; + /* Overflow check to emulate a manual "add with carry" in C. The compiler seems + to be clever enough to find ways to elide the branch on most archs. */ + if (new < wide_sum) + new++; + wide_sum = new; + } +#endif while (wide_sum) { sum += wide_sum & 0xFFFF; -- To view, visit https://review.coreboot.org/c/coreboot/+/80304?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694 Gerrit-Change-Number: 80304 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/amd/phoenix/chip.h: guard FSP-specific data structures
by Matt DeVillier (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80298?usp=email ) Change subject: soc/amd/phoenix/chip.h: guard FSP-specific data structures ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c324421fbc3dc7b9a7bf6f5868785e9718147a5 Gerrit-Change-Number: 80298 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Feb 2024 23:17:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
by Matt DeVillier (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80297?usp=email ) Change subject: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80297/comment/91ef2d57_808367f6 : PS1, Line 9: don't overwrite : those by the coreboot code. phrasing is slightly awkward, maybe "coreboot should not overwrite them" -- To view, visit https://review.coreboot.org/c/coreboot/+/80297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7 Gerrit-Change-Number: 80297 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Feb 2024 23:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/phoenix: add openSIL calls
by Matt DeVillier (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80296?usp=email ) Change subject: soc/amd/phoenix: add openSIL calls ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c Gerrit-Change-Number: 80296 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Feb 2024 23:15:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case
by Matt DeVillier (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80294?usp=email ) Change subject: soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14 Gerrit-Change-Number: 80294 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Feb 2024 23:14:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2024