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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition. The __ms_abi__ attribute works for both i386 and x86_64.
This attribute has to be set to all functions calling or called by
the FSP.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/debug.h
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/efi/efi_datatype.h
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/intel/common/fsp_reset.c
15 files changed, 94 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/7
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77255?usp=email )
Change subject: [Squash]: Add ACPI BDAT support
......................................................................
Patch Set 14:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/acpi_bdat.h:
https://review.coreboot.org/c/coreboot/+/77255/comment/2254a643_61a4eb87 :
PS14, Line 66: EFI_GUID schema_hob_guids[MAX_SCHEMA_LIST_LENGTH];
> From the schema HOB GUIDs, coreboot can get the base/size of these HOBs and do memcpy to add the con […]
Done
https://review.coreboot.org/c/coreboot/+/77255/comment/353f0a4e_42ababed :
PS14, Line 67: } bdat_schema_list_hob;
> e.g. […]
Done
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77255?usp=email )
Change subject: [Squash]: Add ACPI BDAT support
......................................................................
Patch Set 14: Code-Review+1
(4 comments)
Patchset:
PS14:
We can merge this first and add future changes for server coreboot BDAT schema patches based on needs.
File src/soc/intel/common/block/acpi/acpi_bdat.c:
https://review.coreboot.org/c/coreboot/+/77255/comment/1f320c14_4a8684e0 :
PS14, Line 175: memcpy(next_block, schema_data, data_size);
> Regarding the spec of BDAT, the schema_data itself does not contain pointers. […]
Acknowledged
File src/soc/intel/common/block/include/intelblocks/acpi_bdat.h:
https://review.coreboot.org/c/coreboot/+/77255/comment/33a8ff5c_58136803 :
PS14, Line 66: EFI_GUID schema_hob_guids[MAX_SCHEMA_LIST_LENGTH];
> I'm not sure how to accommodate the code of handling ways other than hobs as I don't have a platform […]
From the schema HOB GUIDs, coreboot can get the base/size of these HOBs and do memcpy to add the contents to BDAT. Hence what is needed is actually the base/sizes. Sometimes, customers will have needs to patch the BDAT beyond FSP provided schemas, they can provide schemas with base/sizes to be gathered by bdat_schema_list(_hob) as well.
https://review.coreboot.org/c/coreboot/+/77255/comment/4ae8bbd8_59190ad7 :
PS14, Line 67: } bdat_schema_list_hob;
> I am not sure if the structure from non-hobs should leverage the same structure.
e.g. in server platform, INTEL_FSP_BDAT_SCHEMA_LIST_HOB_GUID will not be provided, but EWL, RMT schema data will be provided as separate HOBs (and maybe others as well). coreboot codes can generate bdat_schema_list by filling needed schemas instead of getting the list from a HOB.
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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, build bot (Jenkins),
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition. The __ms_abi__ attribute works for both i386 and x86_64.
This attribute has to be set to all functions calling or called by
the FSP.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/debug.h
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/efi/efi_datatype.h
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/intel/common/fsp_reset.c
15 files changed, 96 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/6
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Change subject: mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switching
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80215/comment/f267b401_973c4e8b :
PS5, Line 9: Follow reference design rex0, keep the GPIO settings of CNVi/PCIe.
> Why? What are the problems with the current one, and why was this tried in the first place?
Currently no problem about wifi cnvi/pcie. This is just for follow the setting of reference design. Except GPP_F04,GPP_F05 and GPP_S01,GPP_S02, it's for HW change.
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email )
Change subject: mb/google/nissa/var/anraggar: Config TCSS AUX according fw_config
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
File src/mainboard/google/brya/variants/anraggar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/80259/comment/bd4ce118_1683bc90 :
PS7, Line 14: option UNKNOWN 0
maybe typeC with retimer etc...SOC real weird.
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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80277?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition. The __ms_abi__ attribute works for both i386 and x86_64.
This attribute has to be set to all functions calling or called by
the FSP.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/debug.h
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/efi/efi_datatype.h
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/intel/common/fsp_reset.c
15 files changed, 90 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/5
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