coreboot-gerrit February 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add generic function to locate devices
by Shuo Liu (Code Review) 01 Feb '24

01 Feb '24

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp/util: Locate PCU by PCI device ID
by Shuo Liu (Code Review) 01 Feb '24

01 Feb '24

1 0

[L] Change in coreboot[main]: util/ifdtool: Add a new switch -E to protect GPR0
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80235?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/ifdtool: Add a new switch -E to protect GPR0 ...................................................................... util/ifdtool: Add a new switch -E to protect GPR0 This patch adds support for the new command-line option `-E` to the ifdtool, which enables users (primarily factory users) to protect GPR0. Additionally, this patch refactors some code while adding support for enabling GPR0 protection. For more information on the scope of GPR0 (General Protection Range 0), please refer to the Intel Meteor Lake-U Type 4 Client Platform SPI Programming Guide, Document Number 768150. BUG=b:270275115 TEST=Able to test GPR0 protection on google/rex and google/yahiko. > ifdtool -p mtl -E image.bin -O image.bin_lock ... Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff ... GPR0 protection is now enabled Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80235 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 233 insertions(+), 24 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Reka Norman: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 07cc268..e020a8a 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -44,6 +44,32 @@ #define PLATFORM_HAS_10GBE_0_REGION (platform == PLATFORM_DNV) #define PLATFORM_HAS_10GBE_1_REGION (platform == PLATFORM_DNV) +union gprd { + struct bit_field { + /* + * Start Address: bit 0-14 of the GPRD represents the + * protected region start address, where bit 0-11 of + * the start address are assumed to be zero. + */ + uint32_t start:15; + + /* Specifies read protection is enabled */ + uint32_t read_protect_en:1; + + /* + * End Address: bit 16-30 of the GPRD represents the + * protected region end address, where bit 0-11 of + * the end address are assumed to be 0xfff. + */ + uint32_t end:15; + + /* Specifies write protection is enabled */ + uint32_t write_protect_en:1; + } __packed data; + + uint32_t value; +}; + static int max_regions_from_fdbar(const struct fdbar *fdb); static int ifd_version; @@ -1551,14 +1577,39 @@ write_image(filename, image, size); } -static void disable_gpr0(const char *filename, char *image, int size) +static void print_gpr0_range(union gprd reg) { - struct fpsba *fpsba = find_fpsba(image, size); - if (!fpsba) - exit(EXIT_FAILURE); + printf("--------- GPR0 Protected Range --------------\n"); + printf("Start address = 0x%08x\n", reg.data.start << 12); + printf("End address = 0x%08x\n", (reg.data.end << 12) | 0xfff); +} +static uint8_t get_cse_data_partition_offset(void) +{ + uint8_t data_offset = 0xff; + + switch (platform) { + case PLATFORM_CNL: + case PLATFORM_JSL: + data_offset = 0x10; + break; + case PLATFORM_TGL: + case PLATFORM_ADL: + case PLATFORM_MTL: + data_offset = 0x18; + break; + default: + break; + } + + return data_offset; +} + +static uint32_t get_gpr0_offset(void) +{ /* Offset expressed as number of 32-bit fields from FPSBA */ - uint32_t gpr0_offset; + uint32_t gpr0_offset = 0xffffffff; + switch (platform) { case PLATFORM_CNL: gpr0_offset = 0x10; @@ -1574,32 +1625,163 @@ gpr0_offset = 0x40; break; default: + break; + } + + return gpr0_offset; +} + +static void disable_gpr0(const char *filename, char *image, int size) +{ + struct fpsba *fpsba = find_fpsba(image, size); + if (!fpsba) + exit(EXIT_FAILURE); + + uint32_t gpr0_offset = get_gpr0_offset(); + if (gpr0_offset == 0xffffffff) { fprintf(stderr, "Disabling GPR0 not supported on this platform\n"); exit(EXIT_FAILURE); } + + union gprd reg; /* If bit 31 is set then GPR0 protection is enable */ - bool gpr0_status = fpsba->pchstrp[gpr0_offset] & 0x80000000; - if (!gpr0_status) { + reg.value = fpsba->pchstrp[gpr0_offset]; + if (!reg.data.write_protect_en) { printf("GPR0 protection is already disabled\n"); return; } - printf("Value at GPRD offset (%d) is 0x%08x\n", gpr0_offset, fpsba->pchstrp[gpr0_offset]); - printf("--------- GPR0 Protected Range --------------\n"); - /* - * Start Address: bit 0-15 of the GPRD represents the protected region start address, - * where bit 0-11 of the start address are assumed to be zero. - */ - printf("Start address = 0x%08x\n", (fpsba->pchstrp[gpr0_offset] & 0xffff) << 12); - /* - * End Address: bit 16-30 of the GPRD represents the protected region end address, - * where bit 0-11 of the end address are assumed to be 0xfff. - */ - printf("End address = 0x%08x\n", - ((fpsba->pchstrp[gpr0_offset] >> 16) & 0x7fff) << 12 | 0xfff); + printf("Value at GPRD offset (%d) is 0x%08x\n", gpr0_offset, reg.value); + print_gpr0_range(reg); /* 0 means GPR0 protection is disabled */ fpsba->pchstrp[gpr0_offset] = 0; write_image(filename, image, size); + printf("GPR0 protection is now disabled\n"); +} + +/* + * Helper function to parse the FPT to retrieve the FITC start offset and size. + * FITC is a sub-partition table inside CSE data partition known as FPT. + * + * CSE Region + * |-----> CSE Data Partition Offset + * | |-------> FPT Entry + * | | |-> Sub Partition 1 + * | | |-> Sub Partition 2 + * | | |-> FITC + * | | | | -> FITC Offset + * | | | | -> FITC Length + */ +static int parse_fitc_table(struct cse_fpt *fpt, uint32_t *offset, + size_t *size) +{ + size_t num_part_header = fpt->count; + /* Move to the next structure which is FPT sub-partition entries */ + struct cse_fpt_sub_part *fpt_sub_part = (struct cse_fpt_sub_part *)(fpt + 1); + for (size_t index = 0; index < num_part_header; index++) { + if (!strncmp(fpt_sub_part->signature, "FITC", 4)) { + *offset = fpt_sub_part->offset; + *size = fpt_sub_part->length; + return 0; + } + fpt_sub_part++; + } + + return -1; +} + +/* + * Formula to calculate the GPR0 protection range as below: + * Start: CSE Region Base Offset + * End: Till the end of FITC sub-partition + */ +static int calculate_gpr0_range(char *image, int size, + uint32_t *gpr0_start, uint32_t *gpr0_end) +{ + struct frba *frba = find_frba(image, size); + if (!frba) + return -1; + + struct region region = get_region(frba, REGION_ME); + if (region.size <= 0) { + fprintf(stderr, "Region %s is disabled in target\n", + region_name(REGION_ME)); + return -1; + } + + /* CSE Region Start */ + uint32_t cse_region_start = region.base; + /* Get CSE Data Partition Offset */ + uint8_t cse_data_offset = get_cse_data_partition_offset(); + if (cse_data_offset == 0xff) { + fprintf(stderr, "Unsupported platform\n"); + exit(EXIT_FAILURE); + } + uint32_t data_part_offset = *((uint32_t *)(image + cse_region_start + cse_data_offset)); + /* Start reading the CSE Data Partition Table, also known as FPT */ + uint32_t data_part_start = data_part_offset + cse_region_start; + + uint32_t fitc_region_start = 0; + size_t fitc_region_size = 0; + /* + * FPT holds entry for own FPT data structure also bunch of sub-partitions. + * `FITC` is one of such sub-partition entry. + */ + if (parse_fitc_table(((struct cse_fpt *)(image + data_part_start)), + &fitc_region_start, &fitc_region_size) < 0) { + fprintf(stderr, "Unable to find FITC entry\n"); + return -1; + } + + /* + * GPR0 protection is configured to the following range: + * start: CSE region base offset + * end: Till the end of FITC sub-partition (i.e. CSE region + data partition offset + + * FITC sub partition offset + FITC sub partition size) + */ + *gpr0_start = cse_region_start; + *gpr0_end = (cse_region_start + data_part_offset + + fitc_region_start + fitc_region_size) - 1; + + return 0; +} + +static void enable_gpr0(const char *filename, char *image, int size) +{ + struct fpsba *fpsba = find_fpsba(image, size); + if (!fpsba) + exit(EXIT_FAILURE); + + uint32_t gpr0_offset = get_gpr0_offset(); + if (gpr0_offset == 0xffffffff) { + fprintf(stderr, "Enabling GPR0 not supported on this platform\n"); + exit(EXIT_FAILURE); + } + + union gprd reg; + /* If bit 31 is set then GPR0 protection is enable */ + reg.value = fpsba->pchstrp[gpr0_offset]; + if (reg.data.write_protect_en) { + printf("GPR0 protection is already enabled\n"); + print_gpr0_range(reg); + return; + } + + uint32_t gpr0_range_start, gpr0_range_end; + + if (calculate_gpr0_range(image, size, &gpr0_range_start, &gpr0_range_end)) + exit(EXIT_FAILURE); + + reg.data.start = (gpr0_range_start >> 12) & 0x7fff; + reg.data.end = (gpr0_range_end >> 12) & 0x7fff; + reg.data.read_protect_en = 0; + reg.data.write_protect_en = 1; + + fpsba->pchstrp[gpr0_offset] = reg.value; + printf("Value at GPRD offset (%d) is 0x%08x\n", gpr0_offset, reg.value); + print_gpr0_range(reg); + write_image(filename, image, size); + printf("GPR0 protection is now enabled\n"); } static void set_pchstrap(struct fpsba *fpsba, const struct fdbar *fdb, const int strap, @@ -1942,6 +2124,7 @@ " -r | --read Enable CPU/BIOS read access for ME region\n" " -u | --unlock Unlock firmware descriptor and ME region\n" " -g | --gpr0-disable Disable GPR0 (Global Protected Range) register\n" + " -E | --gpr0-enable Enable GPR0 (Global Protected Range) register\n" " -M | --altmedisable <0|1> Set the MeDisable and AltMeDisable (or HAP for skylake or newer platform)\n" " bits to disable ME\n" " -p | --platform Add platform-specific quirks\n" @@ -1975,7 +2158,7 @@ int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; - int mode_gpr0_disable = 0; + int mode_gpr0_disable = 0, mode_gpr0_enable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; char *new_filename = NULL; @@ -2002,6 +2185,7 @@ {"read", 0, NULL, 'r'}, {"unlock", 0, NULL, 'u'}, {"gpr0-disable", 0, NULL, 'g'}, + {"gpr0-enable", 0, NULL, 'E'}, {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, {"platform", 0, NULL, 'p'}, @@ -2011,7 +2195,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:elrugvth?", + while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:elrugEvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -2217,6 +2401,9 @@ case 'g': mode_gpr0_disable = 1; break; + case 'E': + mode_gpr0_enable = 1; + break; case 'p': if (!strcmp(optarg, "aplk")) { platform = PLATFORM_APL; @@ -2270,7 +2457,7 @@ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + - mode_gpr0_disable) > 1) { + (mode_gpr0_disable | mode_gpr0_enable)) > 1) { fprintf(stderr, "You may not specify more than one mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); @@ -2279,7 +2466,7 @@ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + mode_unlocked + mode_density + mode_altmedisable + - mode_validate + mode_gpr0_disable) == 0) { + mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); fprintf(stderr, "run '%s -h' for usage\n", argv[0]); exit(EXIT_FAILURE); @@ -2379,6 +2566,9 @@ if (mode_gpr0_disable) disable_gpr0(new_filename, image, size); + if (mode_gpr0_enable) + enable_gpr0(new_filename, image, size); + if (mode_setstrap) { struct fpsba *fpsba = find_fpsba(image, size); const struct fdbar *fdb = find_fd(image, size); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 219634b..79fe0ab 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -208,3 +208,22 @@ const char *filename; const char *fmapname; }; + +struct cse_fpt { + const char signature[4]; + uint32_t count; + uint8_t header_version; + uint8_t entry_version; + uint8_t length; + uint8_t crc; + uint8_t reserved[20]; +}; + +struct cse_fpt_sub_part { + const char signature[4]; + uint32_t reserved_1; + uint32_t offset; + uint32_t length; + uint8_t reserved_2[12]; + uint32_t flags; +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/80235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Gerrit-Change-Number: 80235 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/rex/variants/ovis: Generate RAM IDs
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/76349?usp=email ) Change subject: mb/google/rex/variants/ovis: Generate RAM IDs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/76349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e97c66082cdb1302c021048b5b438d9a6524bb9 Gerrit-Change-Number: 76349 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Update Kconfig
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80327?usp=email ) Change subject: mb/google/brya/var/xol: Update Kconfig ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/80327/comment/3cd3e856_ad489cda : PS3, Line 479: select DRIVERS_I2C_DA7219 nit: this should be above line 478 -- To view, visit https://review.coreboot.org/c/coreboot/+/80327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e896eb01d37f06a6f1f956d6cd2c2263fefd781 Gerrit-Change-Number: 80327 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Feb 2024 05:17:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/xol: Update memory configuration
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80326?usp=email ) Change subject: mb/google/brya/var/xol: Update memory configuration ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a Gerrit-Change-Number: 80326 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Feb 2024 05:17:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brya/var/xol: Update devicetree
by Subrata Banik (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80324?usp=email ) Change subject: mb/google/brya/var/xol: Update devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80324?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I411932eb4872d77993394a290e8afdd1a0038faf Gerrit-Change-Number: 80324 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Feb 2024 05:16:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop code to locate the UBOX bus
by Shuo Liu (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80102?usp=email ) Change subject: soc/intel/xeon_sp: Drop code to locate the UBOX bus ...................................................................... Patch Set 9: (3 comments) File src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h: https://review.coreboot.org/c/coreboot/+/80102/comment/24d6c10e_378c610e : PS9, Line 27: uint8_t get_stack_busno(const uint8_t stack); the wording 'stack' might be confused, can we use below instead? get_socket_ubox_busno(socket, func)? File src/soc/intel/xeon_sp/spr/soc_util.c: https://review.coreboot.org/c/coreboot/+/80102/comment/b927af8f_9e086bcb : PS9, Line 142: uint32_t get_ubox_busno(uint32_t socket, uint8_t offset) it is still needed to do per-socket uncore bus operations as a general case so it would make sense to keep File src/soc/intel/xeon_sp/util.c: https://review.coreboot.org/c/coreboot/+/80102/comment/11b79bc5_384683de : PS9, Line 27: The words STACK is confusing, can we use UNCORE_BUS_1 directly? or UNCORE_PCU instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/80102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Gerrit-Change-Number: 80102 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Feb 2024 05:14:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/xol: Update memory configuration
by SH Kim (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80326?usp=email ) Change subject: mb/google/brya/var/xol: Update memory configuration ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt: https://review.coreboot.org/c/coreboot/+/80326/comment/a00fd9c6_2b2c8fb5 : PS2, Line 1: # This is a CSV file containing a list of memory parts used by this variant. : # One part per line with an optional fixed ID in column 2. : # Only include a fixed ID if it is required for legacy reasons! : # Generated IDs are dependent on the order of parts in this file, : # so new parts must always be added at the end of the file! : # : # Generate an updated Makefile.inc and dram_id.generated.txt by running the : # part_id_gen tool from util/spd_tools. : # See util/spd_tools/README.md for more details and instructions. > should we keep these auto generated lines ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a Gerrit-Change-Number: 80326 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Feb 2024 04:36:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Update Kconfig
by SH Kim (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80327?usp=email ) Change subject: mb/google/brya/var/xol: Update Kconfig ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/80327/comment/67687976_4033d5de : PS2, Line 480: select DRIVERS_I2C_DA7219 : select DRIVERS_INTEL_ISH > please follow the alphabetic order Done https://review.coreboot.org/c/coreboot/+/80327/comment/b67af714_18cadcdc : PS2, Line 481: select DRIVERS_INTEL_ISH > this is with UFS sku I assume ? Yes. Xol has plan for UFS sku only so far. -- To view, visit https://review.coreboot.org/c/coreboot/+/80327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e896eb01d37f06a6f1f956d6cd2c2263fefd781 Gerrit-Change-Number: 80327 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Feb 2024 04:35:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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