coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/amd/birman/Kconfig: fix comment on endif
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Fred Reitberger, Jason Glenesk. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80289?usp=email ) Change subject: mb/amd/birman/Kconfig: fix comment on endif ...................................................................... mb/amd/birman/Kconfig: fix comment on endif The last 'endif' belongs to the 'if BOARD_AMD_BIRMAN_COMMON' in line 26, so fix the comment. Commit 35a30de7afcc ("mb/amd/birman: Use common option for variant configuration") changed that condition, but missed updating this comment, so do this now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199 --- M src/mainboard/amd/birman/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/80289/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 8d7de450..3b9d607 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -153,4 +153,4 @@ endif # !EM100 -endif # BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_PHOENIX +endif # BOARD_AMD_BIRMAN_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/80289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199 Gerrit-Change-Number: 80289 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/phoenix/Makefile: only include FSP folder conditionally
by Felix Held (Code Review) 01 Feb '24

01 Feb '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80288?usp=email ) Change subject: soc/amd/phoenix/Makefile: only include FSP folder conditionally ...................................................................... soc/amd/phoenix/Makefile: only include FSP folder conditionally Only add the vendorcode/amd/fsp/phoenix and vendorcode/amd/fsp/common folders to the include search path when the SOC_AMD_PHOENIX_FSP Kconfig option is selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272 --- M src/soc/amd/phoenix/Makefile.mk 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80288/1 diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index feb9b1a..9c775cc 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -42,8 +42,11 @@ CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi + +ifeq ($(CONFIG_SOC_AMD_PHOENIX_FSP),y) CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common +endif # Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough ifeq ($(CONFIG_CBFS_VERIFICATION),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/80288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272 Gerrit-Change-Number: 80288 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: riscv/mb/qemu: fix qemu invocation comment
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Philipp Hug, ron minnich. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80262?usp=email ) Change subject: riscv/mb/qemu: fix qemu invocation comment ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80262/comment/e0186558_07dc6dda : PS2, Line 8: Is this because QEMU was improved? (What version?) Or what changed in coreboot, that `util/riscv/make-spike-elf.s` is not needed anymore? -- To view, visit https://review.coreboot.org/c/coreboot/+/80262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I773fb39801f180fead584942dfb385fcde9d2680 Gerrit-Change-Number: 80262 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 19:16:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 7: (5 comments) Patchset: PS3: > > > quick feedback […] I updated the commit message to clarify the document references better. I am working on the `TEST` flag. Patchset: PS7: I think I got all almost all your points right. Thanks for reviewing so promptly 😊 I am still working on the `TEST` flag even though obviously I am testing. File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/80275/comment/3652cc48_f387451b : PS3, Line 295: : #if CONFIG(PLATFORM_USES_FSP2_4) > i don't believe u need this. we don't see this inside silicon_init. […] Done https://review.coreboot.org/c/coreboot/+/80275/comment/1d7cf690_c157d465 : PS3, Line 297: multi_phase_init > > Considering we are in memory_init. […] Done https://review.coreboot.org/c/coreboot/+/80275/comment/50dc9ee6_2322241b : PS3, Line 437: if (hdr->fsp_multi_phase_mem_init_entry_offset) > > Wouldn't it be dangerous to look outside after the limit of the data structure ? These fields are […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 18:20:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
by Jérémy Compostella (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Paul Menzel, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim. Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80277?usp=email to look at the new patch set (#3). Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits ...................................................................... drivers/intel/fsp2_0: Support FSP 2.4 64-bits FSP 2.4 brings FSP 64-bits support which requires some adjustments in coreboot: - Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned. This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP stack buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. - The EDK2 EFIAPI macro definition relies on compiler flags such as __GNUC__ which is not working well when included by coreboot. While it has no side-effect on i386 because the C calling convention used by coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI uses the Microsoft x64 calling convention while coreboot uses the System V AMD64 ABI. Fortunately, EDK2 header allows to override the EFIAPI definition. The __ms_abi__ attribute works for both i386 and x86_64. This attribute has to be set to all functions calling or called by the FSP. - The EFI_STATUS/efi_return_status_t size changes with the architecture (32-bits vs 64-bits). To print statuses independently of the architecture we leverage the size_t 'z' print format which is generally aligned with the architecture size too. In addition, this commit sets`PLATFORM_USES_FSP2_X86_32' to `n' by default if FSP 2.4 is enabled as 64-bits FSP should be norm moving forward. Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/fsp_debug_event.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/debug.h M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/ppi/mp_service1.c M src/drivers/intel/fsp2_0/ppi/mp_service2.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c M src/include/efi/efi_datatype.h M src/soc/amd/common/fsp/fsp_reset.c M src/soc/intel/common/fsp_reset.c M src/soc/intel/xeon_sp/bootblock.c 18 files changed, 94 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99 Gerrit-Change-Number: 80277 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun, Wonkyu Kim. Hello Andrey Petrov, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Tarun, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80275?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. However, since post-codes are in short supply, memory and silicon multi-phase init share the same post-codes. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-… Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/commonlib/include/commonlib/console/post_codes.h M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/upd_display.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c M util/cbfstool/eventlog.c 13 files changed, 124 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/up/squared: Make mini PCIe port mode configurable
by Paul Menzel (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Felix Singer, Reto Buerki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80261?usp=email ) Change subject: mb/up/squared: Make mini PCIe port mode configurable ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80261/comment/07544961_3b46f73a : PS1, Line 11: > Done Perfect. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/80261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Gerrit-Change-Number: 80261 Gerrit-PatchSet: 2 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Thu, 01 Feb 2024 18:02:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Reto Buerki <reet(a)codelabs.ch> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: riscv/mb/qemu: fix qemu invocation comment
by Philipp Hug (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: ron minnich. Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80262?usp=email ) Change subject: riscv/mb/qemu: fix qemu invocation comment ...................................................................... riscv/mb/qemu: fix qemu invocation comment Change-Id: I773fb39801f180fead584942dfb385fcde9d2680 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/emulation/qemu-riscv/Kconfig 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/80262/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 460fb1b..af30d37 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -1,8 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only # To execute, do: -# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf -# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf +# qemu-system-riscv64 -M virt -m 1024M -nographic -bios build/coreboot.rom if BOARD_EMULATION_QEMU_RISCV_RV64 -- To view, visit https://review.coreboot.org/c/coreboot/+/80262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I773fb39801f180fead584942dfb385fcde9d2680 Gerrit-Change-Number: 80262 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 6: (2 comments) Patchset: PS3: > > some more generic feedback, […] Is there anything else I should do ? File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/80275/comment/81555d6c_b0dd11a1 : PS3, Line 282: error_handler > > Considering we are in memory_init. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Feb 2024 17:52:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Nico Huber (Code Review) 01 Feb '24

01 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Michał Żygowski, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 13: (2 comments) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/2929f70c_4a114110 : PS11, Line 598: awlays > Ad.1. This happens right now in patchset 11 AFAIU. It did more than that. And now the code around 1. has too many redundant paths. Not sure if this help: pciexp_scan_bus() is already recursive. Every- thing that is called before the recursion happens on the way down, everything after happens on the way up. So we don't need additional loops that walk up, we do it already. We should first decide on a specific strategy, then try to implement that. I already mentioned > 1. On the way down, set every device to its own maximum. On the way up, propagate the minimum from the endpoints up to the root port This would work without additional state tracking. With the `max_payload_set` state, we can also do everything on the way up. Then we would have to look at the already set value and the cap maximum (like the current implementation does). File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/565ab89e_8ba54ecb : PS13, Line 755: (child->upstream->secondary > max_bus)) `child->upstream` is the same as `bus` by definition. So this check isn't necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Feb 2024 17:51:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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