coreboot-gerrit November 2024

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 50: (2 comments) File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/e01d8097_0b0baed9?us… : PS15, Line 12: static void get_pcie_bar(struct device *dev, uint16_t index, uint64_t *base, uint64_t *size) Maybe to rename as get_pcie_config_bar to be more clear? https://review.coreboot.org/c/coreboot/+/83321/comment/186d4f90_d5936523?us… : PS15, Line 17: *size = CONFIG_ECAM_MMCONF_LENGTH; > The PCIe MMCFG limit register holds a wrong value, so using the Kconfig value as a workaround. Maybe to add a comment here as a note? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 50 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 08 Nov 2024 08:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 50: (3 comments) File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/83b1eda8_dc7580cd?us… : PS15, Line 418: } > Seems there is no `enable` method in the default PCI or PCIe device operations, and the `PCI_COMMAND […] Acknowledged File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/b964d70b_fc48d0fc?us… : PS50, Line 417: if (is_dev_on_domain0(dev) && is_pch_slot(PCI_DEV2DEVFN(PCI_BDF(dev))) && Seems that these static PCH devices will be assigned with an ops later by the PCI probing process, right? https://review.coreboot.org/c/coreboot/+/83321/comment/3906fa82_3d120241?us… : PS50, Line 418: (dev->ops == NULL || dev->ops->enable == NULL)) { What is the benefit of (dev->ops == NULL || dev->ops->enable == NULL)?, just to double confirm it is not enabled by PCI probing yet? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 50 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 08 Nov 2024 08:53:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Raise the open -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 08:37:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Not quite follow up. If the gpmr.h is referred to, should we always assume GPMR is used? -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 08:37:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/google/rex/var/kanix: Add initial GPIO config
by Tyler Wang (Code Review) 08 Nov '24

08 Nov '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85042?usp=email ) Change subject: mb/google/rex/var/kanix: Add initial GPIO config ...................................................................... mb/google/rex/var/kanix: Add initial GPIO config Initial GPIO config for kanix, it's copied from karis. Will update more GPIO config in future. BUG=b:368501705 TEST=emerge-rex coreboot pass Change-Id: Id23b836b48925a30b212b444c9f51cfd6166b9f8 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/kanix/gpio.c 1 file changed, 430 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85042/1 diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c index b6e346f..0bc8f3d 100644 --- a/src/mainboard/google/rex/variants/kanix/gpio.c +++ b/src/mainboard/google/rex/variants/kanix/gpio.c @@ -6,25 +6,445 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R */ + PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R */ + PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R */ + PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R */ + PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L */ + PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R */ + PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L */ + PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A12 : [] ==> EN_UCAM_PWR, test point. */ + PAD_NC(GPP_A12, NONE), + /* GPP_A13 : Not connected */ + PAD_NC(GPP_A13, NONE), + /* GPP_A14 : NC pad. */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 : NC pad. */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L */ + PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), + + /* GPP_A18 : [] ==> CAM_PSW_L */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), + /* GPP_A21 : [] ==> PMCALERT */ + PAD_NC(GPP_A21, NONE), + + /* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */ + PAD_CFG_GPI_IRQ_WAKE(GPP_B00, NONE, PWROK, LEVEL, INVERT), + /* GPP_B01 : [] ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_B01, 1, DEEP), + /* GPP_B02 : net NC is not present in the given design */ + PAD_NC(GPP_B02, NONE), + /* GPP_B03 : net NC is not present in the given design */ + PAD_NC(GPP_B03, NONE), + /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05 : [] ==> SPKR_INT_L_R */ + PAD_CFG_GPI(GPP_B05, NONE, DEEP), + /* GPP_B06 : [] ==> HP_INT_L_R */ + PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), + /* GPP_B07 : [] ==> CAM_DET_L */ + PAD_CFG_GPI_INT_LOCK(GPP_B07, NONE, EDGE_BOTH, LOCK_CONFIG), + /* GPP_B08 : net NC is not present in the given design */ + PAD_NC(GPP_B08, NONE), + /* GPP_B09 : [] ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + /* GPP_B10 : [] ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_B10, 1, DEEP), + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_B11, 0, LOCK_CONFIG), + /* GPP_B12 : [] ==> SLP_SO_R_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 : [] ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 : GPP_B14_STRAP ==> Component NC */ + PAD_NC(GPP_B14, NONE), + /* GPP_B15 : [] ==> USB_OC3# */ + PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* GPP_B17 : NC pad. */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), + /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */ + PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG), + /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */ + PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG), + /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 : NC pad. */ + PAD_NC(GPP_B23, NONE), + + /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_C00, 1, DEEP), + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */ + PAD_CFG_GPO(GPP_C01, 1, DEEP), + /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03 : [] ==> Test pad. */ + PAD_NC(GPP_C03, NONE), + /* GPP_C04 : net NC. */ + PAD_NC(GPP_C04, NONE), + /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */ + PAD_NC(GPP_C05, NONE), + /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ + PAD_CFG_GPO(GPP_C06, 0, DEEP), + /* GPP_C07 : [] ==> SOC_TCHSCR_INT */ + PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE), + /* GPP_C08 : [] ==> SOCHOT_ODL */ + PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), + /* GPP_C09 : net NC is not present in the given design */ + PAD_NC(GPP_C09, NONE), + /* GPP_C10 : net NC is not present in the given design */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 : Not Connected */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12 : NC pad. */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13 : Not connected */ + PAD_NC(GPP_C13, NONE), + /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16 : [] ==> USB_C0_LSX_TX */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17 : [] ==> USB_C0_LSX_RX */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18 : Not Connected. */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19 : Not Connected. */ + PAD_NC(GPP_C19, NONE), + /* GPP_C20 : [] ==> USB_C1_LSX_TX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21 : [] ==> USB_C1_LSX_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22 : [] ==> SOC_FP_BOOT0 */ + PAD_CFG_GPO_LOCK(GPP_C22, 0, LOCK_CONFIG), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_C23, 0, LOCK_CONFIG), + + /* GPP_D00 : Not connected. */ + PAD_NC(GPP_D00, NONE), + /* GPP_D01 : Not Connected */ + PAD_NC(GPP_D01, NONE), + /* GPP_D04 : Not Connected. */ + PAD_NC(GPP_D04, NONE), + /* GPP_D05 : net NC. Test pad. */ + PAD_NC(GPP_D05, NONE), + /* GPP_D06 : net NC. Test pad.*/ + PAD_NC(GPP_D06, NONE), + /* GPP_D07 : [] ==> FPMCU_UWB_MUX_SEL, test pad. */ + PAD_NC(GPP_D07, NONE), + /* GPP_D08 : [] ==> CAM_NC_RES */ + PAD_CFG_GPO(GPP_D08, 1, DEEP), + /* GPP_D09 : [] ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2), + /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* GPP_D14 : [] ==> I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), + /* GPP_D15 : [] ==> I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2), + /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* GPP_D18 : net NC is not present in the given design */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 : [] ==> EC_SOC_REC_SWITCH_ODL */ + PAD_CFG_GPI_LOCK(GPP_D19, NONE, LOCK_CONFIG), + /* GPP_D20 : [] ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D21 : [] ==> WLAN_CLKREQ_ODLl */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + /* GPP_D22 : net NC is not present in the given design */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23 : net NC is not present in the given design */ + PAD_NC(GPP_D23, NONE), + + /* GPP_E00 : NC net. */ + PAD_NC(GPP_E00, NONE), + /* GPP_E01 : MEM_STRAP_2 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), + /* GPP_E02 : MEM_STRAP_1 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E04 : [] ==> SOC_PEN_DETECT */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E04, NONE, PLTRST), + /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E05, 1, DEEP), + /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07 : NC pad. */ + PAD_NC(GPP_E07, NONE), + /* GPP_E08 : NC net. */ + PAD_NC(GPP_E08, NONE), + /* GPP_E09 : SOC_PEN_DETECT */ + PAD_CFG_GPI_SCI_LOCK(GPP_E09, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), + /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E10, NONE, PWROK, LEVEL, INVERT), + /* GPP_E11 : [] ==> MEM_STRAP_0 */ + PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), + /* GPP_E12 : [] ==> MEM_STRAP_3 */ + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 : net NC is not present in the given design */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16 : net NC. Test pad. */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17 : net NC is not present in the given design */ + PAD_NC(GPP_E17, NONE), + /* GPP_E22 : [] ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + + /* GPP_F00 : [] ==> CNV_BRI_DT_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 : [] ==> CNV_BRI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 : [] ==> CNV_RGI_DT_Rl */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 : [] ==> CNV_RGI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 : [] ==> CNV_RF_RST_L */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 : [] ==> CNV_CLKREQ */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 : [] ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), + /* GPP_F07 : [] ==> UCAM_MCLK_R */ + PAD_NC(GPP_F07, NONE), + /* GPP_F08 : [] ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F08, 1, DEEP), + /* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F09, NONE, PLTRST, LEVEL, INVERT), + /* GPP_F10 : NC pad. */ + PAD_NC(GPP_F10, NONE), + /* GPP_F11 : GSP1_SOC_CLK_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5), + /* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5), + /* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS_R */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5), + /* GPP_F14 : net NC. */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15 : net NC. */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16 : net NC. */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5), + /* GPP_F18 : net NC. */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19 : [] ==> GPP_F19_STRAP */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20 : [] ==> GPP_F20_STRAP */ + PAD_NC(GPP_F20, NONE), + /* GPP_F21 : [] ==> SPI_SOC_CS_UWB_L_STRAP */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 : net NC is not present in the given design */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 : net NC is not present in the given design */ + PAD_NC(GPP_F23, NONE), + + /* GPP_H00 : SPI_SOC_CLK_UWB_STRAP_R ==> Component NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01 : SPI_SOC_DO_UWB_DI_STRAP_R ==> Component NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02 : SPI_SOC_DI_UWB_DO_STRAP ==> Component NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H04 : [] ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), + /* GPP_H05 : [] ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), + /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */ + PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG), + /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */ + PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + /* GPP_H11 : net NC is not present in the given design */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13 : [] ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 : [] ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* GPP_H15 : [] ==> CAM_SEN_EN */ + PAD_CFG_GPO_LOCK(GPP_H15, 0, LOCK_CONFIG), + /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 : [] ==> SOC_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 : [] ==> SOC_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S00 : [] ==> SDW_HP_CLK_WLAN_PCM_CLK */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01 : [] ==> SDW_HP_DATA_WLAN_PCM_SYNC */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02 : [] ==> DMIC_SOC_CLK0_WLAN_PCM_OUT */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3), + /* GPP_S03 : [] ==> DMIC_SOC_DATA0_WLAN_PCM_IN */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3), + /* GPP_S04 : Not connected. */ + PAD_NC(GPP_S04, NONE), + /* GPP_S05 : Not connected. */ + PAD_NC(GPP_S05, NONE), + /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), + /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), + + /* GPP_V00 : [] ==> BATLOW_L */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01 : [] ==> ACPRESENT */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04 : [] ==> SLP_S3_L */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 : [] ==> SLP_S4_L */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 : [] ==> SOC_SLP_A_L */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V08 : [] ==> SOC_SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 : [] ==> SLP_S5_L */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 : [] ==> SOC_GPP_V11 testpoint*/ + PAD_NC(GPP_V11, NONE), + /* GPP_V12 : [] ==> SOC_SLP_LAN_L */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V14 : [] ==> SOC_WAKE_L */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V22 : NC net. */ + PAD_NC(GPP_V22, NONE), + /* GPP_V23 : [] ==> UCAM_RST_L */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), + + /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + + /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_D03 : Not Connected */ + PAD_NC(GPP_D03, NONE), + + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + + /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_C00, 1, DEEP), + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */ + PAD_CFG_GPO(GPP_C01, 0, DEEP), + + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_C00, 1, DEEP), + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */ + PAD_CFG_GPO(GPP_C01, 0, DEEP), + /* GPP_D02 : Not Connected */ + PAD_NC(GPP_D02, NONE), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), +}; + const struct pad_config *variant_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(gpio_table); + return gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; DECLARE_CROS_GPIOS(cros_gpios); - -const struct pad_config *variant_romstage_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/85042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id23b836b48925a30b212b444c9f51cfd6166b9f8 Gerrit-Change-Number: 85042 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84932?usp=email ) Change subject: mb/google/rauru: Configure TPM ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: `aarch64-elf-ld.bfd: Bootblock exceeded its allotted size! (70K)` -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 07:39:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/rauru: Enable ChromeOS EC
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84931?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Enable ChromeOS EC ...................................................................... mb/google/rauru: Enable ChromeOS EC 1. Configure ChromeOS EC 2. Pass GPIO_EC_AP_INT_ODL to the payload TEST=build pass BUG=b:317009620 Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84931 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/bootblock.c M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h M src/mainboard/google/rauru/reset.c 5 files changed, 19 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 457b5fb..c7483e2 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -10,7 +10,7 @@ config VBOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT + select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_MOCK_SECDATA config BOARD_SPECIFIC_OPTIONS @@ -21,6 +21,10 @@ select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI config MAINBOARD_DIR string @@ -35,4 +39,8 @@ config BOOT_DEVICE_SPI_FLASH_BUS int default 8 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x1 endif diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index e0717aa..bbebf52 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -17,6 +17,7 @@ if (CONFIG(PCI)) mtk_pcie_pre_init(); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index 863e9a2..a24995f 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -7,6 +7,8 @@ void setup_chromeos_gpios(void) { + gpio_input(GPIO_EC_AP_INT_ODL); + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0); gpio_output(GPIO_BEEP_ON_OD, 0); gpio_output(GPIO_EN_PWR_FP, 0); @@ -20,6 +22,7 @@ struct lb_gpio chromeos_gpios[] = { { GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done" }, { GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable" }, + { GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt" }, { GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable" }, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index 870a02f..b8c9a82 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -7,7 +7,9 @@ #define GPIO_BEEP_ON_OD GPIO(PERIPHERAL_EN1) #define GPIO_EN_SPKR GPIO(PERIPHERAL_EN0) +#define GPIO_EC_AP_INT_ODL GPIO(EINT19) #define GPIO_XHCI_INIT_DONE GPIO(EINT28) +#define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29) #define GPIO_FP_RST_1V8_S3_L GPIO(EINT26) #define GPIO_AP_FP_FW_UP_STRAP GPIO(EINT27) #define GPIO_EN_PWR_FP GPIO(PERIPHERAL_EN3) diff --git a/src/mainboard/google/rauru/reset.c b/src/mainboard/google/rauru/reset.c index 3eb1390..05a576b 100644 --- a/src/mainboard/google/rauru/reset.c +++ b/src/mainboard/google/rauru/reset.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <reset.h> +#include "gpio.h" + void do_board_reset(void) { - /* TODO: add reset function when gpio is ready */ + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059 Gerrit-Change-Number: 84931 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add SPI driver support
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84930?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add SPI driver support ...................................................................... soc/mediatek/mt8196: Add SPI driver support Add SPI controller driver code with support for 8 buses (SPI0 to SPI7). Test=Build pass, verify the wavefroms for SPI0~7 are correct. BUG=b:317009620 Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Signed-off-by: Liya Li <ot_liya.li(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84930 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/spi.h M src/soc/mediatek/mt8196/spi.c 3 files changed, 120 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 145c424..f67ef0c 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -6,7 +6,7 @@ all-y += ../common/gpio.c ../common/gpio_op.c gpio.c gpio_eint.c all-y += ../common/i2c.c i2c.c all-y += ../common/pll.c pll.c -all-$(CONFIG_SPI_FLASH) += spi.c +all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c all-y += timer.c timer_prepare.c all-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8196/include/soc/spi.h b/src/soc/mediatek/mt8196/include/soc/spi.h index 43edc89..2db20ab 100644 --- a/src/soc/mediatek/mt8196/include/soc/spi.h +++ b/src/soc/mediatek/mt8196/include/soc/spi.h @@ -8,7 +8,21 @@ #ifndef SOC_MEDIATEK_MT8196_SPI_H #define SOC_MEDIATEK_MT8196_SPI_H -#include <spi-generic.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 8 + +#define GET_SCK_REG(x) ((x)->spi_cfg2_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cmd_reg) + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 32, 16) +DEFINE_BITFIELD(SPI_TICK_DLY, 24, 22) /* Initialize SPI NOR Flash Controller */ void mtk_snfc_init(void); diff --git a/src/soc/mediatek/mt8196/spi.c b/src/soc/mediatek/mt8196/spi.c index 770b5b0..cf2df63 100644 --- a/src/soc/mediatek/mt8196/spi.c +++ b/src/soc/mediatek/mt8196/spi.c @@ -5,6 +5,8 @@ * Chapter number: 13.9 */ +#include <assert.h> +#include <console/console.h> #include <device/mmio.h> #include <gpio.h> #include <soc/addressmap.h> @@ -12,6 +14,92 @@ #include <soc/spi.h> #include <spi_flash.h> +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(EINT31), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(INT_SIM2), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(SPI_CSB_SEC), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + }, + { + .regs = (void *)SPI6_BASE, + .cs_gpio = GPIO(I2SIN1_LRCK), + }, + { + .regs = (void *)SPI7_BASE, + .cs_gpio = GPIO(EINT6), + }, +}; + +static const struct pad_func pad_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC_DOWN(SPI0_MI, SPI0_MI), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC_DOWN(SPI0_MO, SPI0_MO), + PAD_FUNC_DOWN(SPI0_CLK, SPI0_CLK), + }, + { + PAD_FUNC_DOWN(SPI1_MI, SPI1_MI), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC_DOWN(SPI1_MO, SPI1_MO), + PAD_FUNC_DOWN(SPI1_CLK, SPI1_CLK), + }, + { + PAD_FUNC_DOWN(EINT28, SPI2_A_MI), + PAD_FUNC_GPIO(EINT31), + PAD_FUNC_DOWN(EINT29, SPI2_A_MO), + PAD_FUNC_DOWN(EINT30, SPI2_A_CLK), + }, + { + PAD_FUNC_DOWN(EINT1, SPI3_A_MI), + PAD_FUNC_GPIO(INT_SIM2), + PAD_FUNC_DOWN(EINT0, SPI3_A_MO), + PAD_FUNC_DOWN(INT_SIM1, SPI3_A_CLK), + }, + { + PAD_FUNC_DOWN(SPI_MI_SEC, SPI4_A_MI), + PAD_FUNC_GPIO(SPI_CSB_SEC), + PAD_FUNC_DOWN(SPI_MO_SEC, SPI4_A_MO), + PAD_FUNC_DOWN(SPI_CLK_SEC, SPI4_A_CLK), + }, + { + PAD_FUNC_DOWN(SPI5_MI, SPI5_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC_DOWN(SPI5_MO, SPI5_MO), + PAD_FUNC_DOWN(SPI5_CLK, SPI5_CLK), + }, + { + PAD_FUNC_DOWN(I2SOUT1_DO, SPI6_A_MI), + PAD_FUNC_GPIO(I2SIN1_LRCK), + PAD_FUNC_DOWN(I2SIN1_DI, SPI6_A_MO), + PAD_FUNC_DOWN(I2SIN1_BCK, SPI6_A_CLK), + }, + { + PAD_FUNC_DOWN(EINT8, SPI7_A_MI), + PAD_FUNC_GPIO(EINT6), + PAD_FUNC_DOWN(EINT7, SPI7_A_MO), + PAD_FUNC_DOWN(EINT5, SPI7_A_CLK), + }, +}; + static const struct pad_func nor_pinmux[4] = { PAD_FUNC(SDA10, SF_CK, GPIO_PULL_DOWN), PAD_FUNC(SCL10, SF_CS, GPIO_PULL_UP), @@ -25,6 +113,17 @@ mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_14_MA); } +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr; + + ptr = pad_funcs[bus]; + + for (unsigned int i = 0; i < ARRAY_SIZE(pad_funcs[0]); i++) + gpio_set_mode(ptr[i].gpio, ptr[i].func); +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, @@ -32,6 +131,11 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { .ctrlr = &spi_flash_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, -- To view, visit https://review.coreboot.org/c/coreboot/+/84930?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Gerrit-Change-Number: 84930 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and clock init support
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email ) ( 27 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add PLL and clock init support ...................................................................... soc/mediatek/mt8196: Add PLL and clock init support Add PLL and clock init code, frequency meter and APIs for raising little CPU frequency and set tvdpll frequency. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84495 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/pll.c 6 files changed, 2,137 insertions(+), 7 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 6b29e73..145c424 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -5,6 +5,7 @@ all-y += ../common/flash_controller.c all-y += ../common/gpio.c ../common/gpio_op.c gpio.c gpio_eint.c all-y += ../common/i2c.c i2c.c +all-y += ../common/pll.c pll.c all-$(CONFIG_SPI_FLASH) += spi.c all-y += timer.c timer_prepare.c all-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 1b1f09f..19b90ee 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -3,11 +3,14 @@ #include <bootblock_common.h> #include <soc/early_init.h> #include <soc/mmu_operations.h> +#include <soc/pll.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); mtk_wdt_init(); + mt_pll_init(); + mt_pll_post_init(); early_init_clear(); } diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index c50ab6e..73702bf 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -11,6 +11,11 @@ enum { MCUCFG_BASE = MCUSYS_BASE, + CCIPLL_PLL_CTRL_BASE = MCUSYS_BASE + 0x00030000, + ARMPLL_LL_PLL_CTRL_BASE = MCUSYS_BASE + 0x00030400, + ARMPLL_BL_PLL_CTRL_BASE = MCUSYS_BASE + 0x00030800, + ARMPLL_B_PLL_CTRL_BASE = MCUSYS_BASE + 0x00030C00, + PTPPLL_PLL_CTRL_BASE = MCUSYS_BASE + 0x00034000, }; enum { @@ -30,6 +35,7 @@ BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, BCRM_INFRA1_AO_BASE = IO_PHYS + 0x0002A000, GPIO_BASE = IO_PHYS + 0x0002D000, + APINFRA_IO_CTRL_AO_BCRM_BASE = IO_PHYS + 0x00156000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, EMI0_BASE = IO_PHYS + 0x00469000, EMI0_MPU_BASE = IO_PHYS + 0x00468000, @@ -68,7 +74,13 @@ I2C7_BASE = IO_PHYS + 0x03AB0000, I2C8_BASE = IO_PHYS + 0x03B30000, I2C9_BASE = IO_PHYS + 0x03BB0000, + IMP_IIC_WRAP_N_BASE = IO_PHYS + 0x03C30000, + APINFRA_IO_NOC_AO_BCRM_BASE = IO_PHYS + 0x04012000, + APINFRA_MEM_NOC_AO_BCRM_BASE = IO_PHYS + 0x04032000, + APINFRA_MEM_CTRL_AO_BCRM_BASE = IO_PHYS + 0x04124000, + APIFRBUS_AO_MEM_REG_BASE = IO_PHYS + 0x04126000, THERM_CTRL_BASE = IO_PHYS + 0x04414000, + VOTE_BASE = IO_PHYS + 0x04500000, UART0_BASE = IO_PHYS + 0x06000000, SPI0_BASE = IO_PHYS + 0x06110000, SPI1_BASE = IO_PHYS + 0x06130000, @@ -98,22 +110,52 @@ I2C12_DMA_BASE = IO_PHYS + 0x064D0000, I2C13_DMA_BASE = IO_PHYS + 0x064F0000, I2C14_DMA_BASE = IO_PHYS + 0x06500000, + PERI_PAR_BCRM_BASE = IO_PHYS + 0x06610000, + PERICFG_AO_SEC_BASE = IO_PHYS + 0x06630000, PERICFG_AO_BASE = IO_PHYS + 0x06640000, SSUSB_IPPC_BASE = IO_PHYS + 0x06703E00, SSUSB_SIF_BASE = IO_PHYS + 0x06730300, + USB_BUS_BCRM_BASE = IO_PHYS + 0x06781000, UFSHCI_BASE = IO_PHYS + 0x06810000, + SSR_TOP_BASE = IO_PHYS + 0x08000000, + VLPCFG_BASE = IO_PHYS + 0x0C001000, SCP_BASE = IO_PHYS + 0x0C004000, SCP_PBUS_BASE = IO_PHYS + 0x0C00D000, RGU_BASE = IO_PHYS + 0x0C010000, GPT_BASE = IO_PHYS + 0x0C015000, + VLP_CKSYS_BASE = IO_PHYS + 0x0C016000, PMIF_SPMI_P_BASE = IO_PHYS + 0x0C018000, PMIF_SPMI_BASE = IO_PHYS + 0x0C01A000, SPMI_MST_BASE = IO_PHYS + 0x0C01C000, SPMI_MST_P_BASE = IO_PHYS + 0x0C01C800, SYSTIMER_BASE = IO_PHYS + 0x0C400000, + MMVOTE_MMSYS_CONFIG_BASE = IO_PHYS + 0x12000000, + MMVOTE_MMSYS1_CONFIG_BASE = IO_PHYS + 0x12400000, + MMVOTE_OVLSYS_CONFIG_BASE = IO_PHYS + 0x12800000, + MMVOTE_OVLSYS1_CONFIG_BASE = IO_PHYS + 0x12C00000, + MMVOTE_IMGSYS_MAIN_BASE = IO_PHYS + 0x14000000, + MMVOTE_IMG_VCORE_D1A_BASE = IO_PHYS + 0x14780000, + MMVOTE_VDEC_SOC_GCON_BASE = IO_PHYS + 0x1600f000, + MMVOTE_VDEC_GCON_BASE = IO_PHYS + 0x1602f000, + MMVOTE_VENC_GCON_BASE = IO_PHYS + 0x18000000, + MMVOTE_VENC_GCON_CORE1_BASE = IO_PHYS + 0x18800000, + MMVOTE_VENC_GCON_CORE2_BASE = IO_PHYS + 0x18C00000, + MMVOTE_CAM_MAIN_R1A_BASE = IO_PHYS + 0x1A000000, + MMVOTE_CCU_MAIN_BASE = IO_PHYS + 0x1C800000, + MMVOTE_DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x1E800000, + MMVOTE_BASE = IO_PHYS + 0x21B00000, + MMPC_BASE = IO_PHYS + 0x21B50000, + MMSYS_CONFIG_BASE = IO_PHYS + 0x22000000, + MMSYS1_CONFIG_BASE = IO_PHYS + 0x22400000, DSI0_BASE = IO_PHYS + 0x22490000, DISP_DVO0 = IO_PHYS + 0x224C0000, + OVLSYS_CONFIG_BASE = IO_PHYS + 0x22800000, + OVLSYS1_CONFIG_BASE = IO_PHYS + 0x22C00000, + DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x2E800000, EDP_BASE = IO_PHYS + 0x2EC40000, + MFGPLL_PLL_CTRL_BASE = IO_PHYS + 0x3B810000, + MFGPLL_SC0_PLL_CTRL_BASE = IO_PHYS + 0x3B810400, + MFGPLL_SC1_PLL_CTRL_BASE = IO_PHYS + 0x3B810800, }; #endif diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index 3fdfebd..9bddf10 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -43,7 +43,7 @@ DRAM_INIT_CODE(0x02000000, 600K) #else /* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */ - BOOTBLOCK(0x02001000, 60K) + BOOTBLOCK(0x02001000, 70K) #endif OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) PRERAM_CBFS_CACHE(0x020DA000, 48K) diff --git a/src/soc/mediatek/mt8196/include/soc/pll.h b/src/soc/mediatek/mt8196/include/soc/pll.h index 1f6d1c9..8f2854f 100644 --- a/src/soc/mediatek/mt8196/include/soc/pll.h +++ b/src/soc/mediatek/mt8196/include/soc/pll.h @@ -8,16 +8,430 @@ #ifndef SOC_MEDIATEK_MT8196_PLL_H #define SOC_MEDIATEK_MT8196_PLL_H +#include <soc/addressmap.h> #include <soc/pll_common.h> -/* top_div rate */ -enum { - CLK26M_HZ = 26 * MHz, +static struct mtk_apinfra_io_noc_regs *const + mtk_apinfra_io_noc = (void *)APINFRA_IO_NOC_AO_BCRM_BASE; +static struct mtk_apinfra_io_ctrl_regs *const + mtk_apinfra_io_ctrl = (void *)APINFRA_IO_CTRL_AO_BCRM_BASE; +static struct mtk_apinfra_mem_noc_regs *const + mtk_apinfra_mem_noc = (void *)APINFRA_MEM_NOC_AO_BCRM_BASE; +static struct mtk_apinfra_mem_ctrl_regs *const + mtk_apinfra_mem_ctrl = (void *)APINFRA_MEM_CTRL_AO_BCRM_BASE; +static struct mtk_mcusys_regs *const + mtk_mcusys = (void *)MCUCFG_BASE; +static struct mtk_peri_regs *const + mtk_peri = (void *)PERI_PAR_BCRM_BASE; +static struct mtk_usb_regs *const + mtk_usb = (void *)USB_BUS_BCRM_BASE; +static struct mtk_topckgen2_regs *const + mtk_topckgen2 = (void *)CKSYS_GP2_BASE; +static struct mtk_apmixed2_regs *const + mtk_apmixed2 = (void *)APMIXEDSYS_GP2_BASE; +static struct mtk_apifrbus_regs *const + mtk_apifrbus = (void *)APIFRBUS_AO_MEM_REG_BASE; +static struct mtk_pericfg_regs *const + mtk_pericfg = (void *)PERICFG_AO_BASE; +static struct mtk_ssr_regs *const + mtk_ssr = (void *)SSR_TOP_BASE; +static struct mtk_spm_mtcmos_regs *const + mtk_spm_mtcmos = (void *)SCP_BASE; +static struct mtk_vlp_regs *const + mtk_vlpsys = (void *)VLP_CKSYS_BASE; +static struct mtk_dispsys_regs *const + mtk_mmsys = (void *)MMSYS_CONFIG_BASE; +static struct mtk_dispsys_regs *const + mtk_mmsys1 = (void *)MMSYS1_CONFIG_BASE; +static struct mtk_dispsys_regs *const + mtk_ovlsys = (void *)OVLSYS_CONFIG_BASE; +static struct mtk_dispsys_regs *const + mtk_ovlsys1 = (void *)OVLSYS1_CONFIG_BASE; +static struct mtk_dispsys_regs *const + mtk_disp = (void *)DISP_VDISP_AO_CONFIG_BASE; +static struct mtk_mfgpll_regs *const + mtk_mfgpll = (void *)MFGPLL_PLL_CTRL_BASE; +static struct mtk_mfgpll_regs *const + mtk_mfgpll_sc0 = (void *)MFGPLL_SC0_PLL_CTRL_BASE; +static struct mtk_mfgpll_regs *const + mtk_mfgpll_sc1 = (void *)MFGPLL_SC1_PLL_CTRL_BASE; +static struct mtk_mcupll_regs *const + mtk_ccipll = (void *)CCIPLL_PLL_CTRL_BASE; +static struct mtk_mcupll_regs *const + mtk_armpll_ll = (void *)ARMPLL_LL_PLL_CTRL_BASE; +static struct mtk_mcupll_regs *const + mtk_armpll_bl = (void *)ARMPLL_BL_PLL_CTRL_BASE; +static struct mtk_mcupll_regs *const + mtk_armpll_b = (void *)ARMPLL_B_PLL_CTRL_BASE; +static struct mtk_mcupll_regs *const + mtk_ptppll = (void *)PTPPLL_PLL_CTRL_BASE; + +struct mtk_apinfra_io_noc_regs { + u32 reserved1[1]; + u32 clk_io_noc_ctrl; +}; +check_member(mtk_apinfra_io_noc_regs, clk_io_noc_ctrl, 0x0004); + +struct mtk_apinfra_io_ctrl_regs { + u32 reserved1[2]; + u32 clk_io_intx_bus_ctrl; +}; +check_member(mtk_apinfra_io_ctrl_regs, clk_io_intx_bus_ctrl, 0x0008); + +struct mtk_apinfra_mem_noc_regs { + u32 vdnr_mem_intf_par_bus_ctrl; +}; +check_member(mtk_apinfra_mem_noc_regs, vdnr_mem_intf_par_bus_ctrl, 0x0000); + +struct mtk_apinfra_mem_ctrl_regs { + u32 reserved1[3]; + u32 vdnr_dcm_mem_intx_bus_ctrl; + u32 reserved2[1]; + u32 clk_mem_intx_bus_ctrl[6]; +}; +check_member(mtk_apinfra_mem_ctrl_regs, vdnr_dcm_mem_intx_bus_ctrl, 0x000C); +check_member(mtk_apinfra_mem_ctrl_regs, clk_mem_intx_bus_ctrl[0], 0x0014); +check_member(mtk_apinfra_mem_ctrl_regs, clk_mem_intx_bus_ctrl[5], 0x0028); + +struct mtk_mcusys_regs { + u32 reserved1[64]; + u32 bus_plldiv_cfg; + u32 reserved2[2]; + u32 cpu_plldiv0_cfg; + u32 reserved3[2]; + u32 cpu_plldiv1_cfg; + u32 reserved4[2]; + u32 cpu_plldiv2_cfg; + u32 reserved5[112]; + u32 cpu_src_clk_config; + u32 infra_clk_src_config; + u32 dsu_pcsm_clk_src_config; + u32 reserved6[323]; + u32 ses_clk_free_ck_en; +}; +check_member(mtk_mcusys_regs, bus_plldiv_cfg, 0x0100); +check_member(mtk_mcusys_regs, cpu_src_clk_config, 0x02E8); +check_member(mtk_mcusys_regs, ses_clk_free_ck_en, 0x0800); + +struct mtk_peri_regs { + u32 reserved1[11]; + u32 vdnr_dcm_top_peri_par_bus_u_peri_par_bus_ctrl; +}; +check_member(mtk_peri_regs, vdnr_dcm_top_peri_par_bus_u_peri_par_bus_ctrl, 0x002C); + +struct mtk_usb_regs { + u32 reserved1[24]; + u32 vdnr_dcm_top_usb_bus_u_usb_bus_ctrl; +}; +check_member(mtk_usb_regs, vdnr_dcm_top_usb_bus_u_usb_bus_ctrl, 0x0060); + +struct mtk_clk_cfg { + u32 cfg; + u32 set; + u32 clr; + u32 reserved; }; -/* top_mux rate */ +struct mtk_topckgen_regs { + u32 reserved1[1]; + u32 clk_cfg_update[3]; + struct mtk_clk_cfg clk_cfg[23]; + u32 reserved2[16]; + u32 clk26cali[2]; + u32 reserved3[3]; + u32 clk_misc_cfg; + u32 reserved4[10]; + u32 clk_dbg_cfg; + u32 reserved5[13]; + u32 clk_prot_idle_reg; + u32 clk_fenc_bypass_reg[3]; + u32 clk_prot_idle_all_reg[3]; + u32 clk_prot_idle_all_inv_reg[3]; + u32 clk_prot_vote_ck_en_reg[3]; + u32 clk_prot_spm_ck_en_reg; +}; +check_member(mtk_topckgen_regs, clk_cfg_update[0], 0x0004); +check_member(mtk_topckgen_regs, clk_cfg[0], 0x0010); +check_member(mtk_topckgen_regs, clk26cali[0], 0x01C0); +check_member(mtk_topckgen_regs, clk_prot_idle_all_reg[0], 0x0248); +check_member(mtk_topckgen_regs, clk_prot_spm_ck_en_reg, 0x026C); + +struct mtk_apmixed_regs { + u32 reserved1[13]; + u32 fenc_bypass_con; + u32 fenc_protected_con; + u32 reserved2[4]; + u32 child_enable_mask_con; + u32 reserved3[1]; + u32 ref_clk_req_protected_con; + u32 reserved4[11]; + u32 pllen_all_set; + u32 pllen_all_clr; + u32 reserved5[1]; + u32 pll_div_rstb_all_set; + u32 reserved6[111]; + u32 mainpll_con[2]; + u32 reserved7[3]; + u32 univpll_con[2]; + u32 reserved8[3]; + u32 msdcpll_con[2]; + u32 reserved9[3]; + u32 adsppll_con[2]; + u32 reserved10[3]; + u32 emipll_con[2]; + u32 reserved11[3]; + u32 emipll2_con[2]; + u32 reserved12[3]; + u32 net1pll_con[2]; + u32 reserved13[3]; + u32 sgmiipll_con[2]; +}; +check_member(mtk_apmixed_regs, fenc_bypass_con, 0x0034); +check_member(mtk_apmixed_regs, mainpll_con[0], 0x0250); +check_member(mtk_apmixed_regs, sgmiipll_con[0], 0x02DC); + +struct mtk_topckgen2_regs { + u32 reserved0[1]; + u32 cksys2_clk_cfg_update; + u32 reserved1[2]; + struct mtk_clk_cfg cksys2_clk_cfg[7]; + u32 reserved2[28]; + u32 cksys2_clk26cali[2]; + u32 reserved3[3]; + u32 cksys2_clk_misc_cfg; + u32 reserved4[7]; + u32 cksys2_clk_dbg_cfg; + u32 reserved5[5]; + u32 cksys2_clk_prot_idle_reg; + u32 cksys2_clk_fenc_bypass_reg; + u32 reserved6[2]; + u32 cksys2_clk_prot_idle_all_reg; + u32 reserved7[2]; + u32 cksys2_clk_prot_idle_all_inv_reg; + u32 reserved8[2]; + u32 cksys2_clk_prot_vote_ck_en_reg; + u32 reserved9[2]; + u32 cksys2_clk_prot_spm_ck_en_reg; +}; +check_member(mtk_topckgen2_regs, cksys2_clk_cfg_update, 0x0004); +check_member(mtk_topckgen2_regs, cksys2_clk26cali[0], 0x00F0); +check_member(mtk_topckgen2_regs, cksys2_clk_prot_spm_ck_en_reg, 0x0170); + +struct mtk_apmixed2_regs { + u32 reserved1[13]; + u32 gp2_fenc_bypass_con; + u32 gp2_fenc_protected_con; + u32 reserved2[4]; + u32 gp2_child_enable_mask_con; + u32 reserved3[1]; + u32 gp2_ref_clk_req_protected_con; + u32 reserved4[11]; + u32 gp2_pllen_all_set; + u32 gp2_pllen_all_clr; + u32 reserved5[1]; + u32 gp2_pll_div_rstb_all_set; + u32 reserved6[111]; + u32 mainpll2_con[2]; + u32 reserved7[3]; + u32 univpll2_con[2]; + u32 reserved8[3]; + u32 mmpll2_con[2]; + u32 reserved9[3]; + u32 imgpll_con[2]; + u32 reserved10[3]; + u32 tvdpll1_con[2]; + u32 reserved11[3]; + u32 tvdpll2_con[2]; + u32 reserved12[3]; + u32 tvdpll3_con[2]; +}; +check_member(mtk_apmixed2_regs, gp2_fenc_bypass_con, 0x0034); +check_member(mtk_apmixed2_regs, mainpll2_con[0], 0x0250); +check_member(mtk_apmixed2_regs, tvdpll3_con[1], 0x02CC); + +struct mtk_apifrbus_regs { + u32 reserved1[832]; + struct mtk_clk_cfg apifrbus_ao_mem_reg_module_cg; +}; +check_member(mtk_apifrbus_regs, apifrbus_ao_mem_reg_module_cg.cfg, 0x0D00); +check_member(mtk_apifrbus_regs, apifrbus_ao_mem_reg_module_cg.clr, 0x0D08); + +struct mtk_pericfg_regs { + u32 reserved1[4]; + u32 pericfg_ao_peri_cg[3]; + u32 reserved2[2]; + u32 pericfg_ao_peri_cg_0_set; + u32 pericfg_ao_peri_cg_0_clr; + u32 pericfg_ao_peri_cg_1_set; + u32 pericfg_ao_peri_cg_1_clr; + u32 pericfg_ao_peri_cg_2_set; + u32 pericfg_ao_peri_cg_2_clr; +}; +check_member(mtk_pericfg_regs, pericfg_ao_peri_cg[0], 0x0010); +check_member(mtk_pericfg_regs, pericfg_ao_peri_cg_2_clr, 0x0038); + +struct mtk_ssr_regs { + u32 ssr_top_ssr_top_clk_cfg[3]; +}; +check_member(mtk_ssr_regs, ssr_top_ssr_top_clk_cfg[0], 0x0000); + +struct mtk_spm_mtcmos_regs { + u32 reserved1[260]; + u32 spm2gpupm_con; + u32 reserved2[635]; + u32 md1_pwr_con; + u32 conn_pwr_con; + u32 reserved3[4]; + u32 ssusb_dp_phy_p0_pwr_con; + u32 ssusb_p0_pwr_con; + u32 ssusb_p1_pwr_con; + u32 ssusb_p23_pwr_con; + u32 ssusb_phy_p2_pwr_con; + u32 ufs0_pwr_con; + u32 ufs0_phy_pwr_con; + u32 pextp_mac0_pwr_con; + u32 pextp_mac1_pwr_con; + u32 pextp_mac2_pwr_con; + u32 pextp_phy0_pwr_con; + u32 pextp_phy1_pwr_con; + u32 pextp_phy2_pwr_con; + u32 audio_pwr_con; + u32 reserved4[1]; + u32 adsp_top_pwr_con; + u32 adsp_infra_pwr_con; + u32 adsp_ao_pwr_con; + u32 mm_proc_pwr_con; + u32 reserved5[8]; + u32 ssrsys_pwr_con; + u32 spu_ise_pwr_con; + u32 spu_hwrot_pwr_con; + u32 reserved6[1]; + u32 hsgmii0_pwr_con; + u32 hsgmii1_pwr_con; + u32 reserved7[24]; + u32 md_buck_iso_con; + u32 reserved8[5]; + u32 pwr_status; + u32 pwr_status_2nd; +}; +check_member(mtk_spm_mtcmos_regs, spm2gpupm_con, 0x0410); +check_member(mtk_spm_mtcmos_regs, md1_pwr_con, 0x0E00); +check_member(mtk_spm_mtcmos_regs, ufs0_pwr_con, 0x0E2C); +check_member(mtk_spm_mtcmos_regs, hsgmii0_pwr_con, 0x0E94); +check_member(mtk_spm_mtcmos_regs, pwr_status_2nd, 0x0F18); + +struct mtk_vlp_regs { + u32 reserved0[1]; + u32 vlp_clk_cfg_update[2]; + u32 reserved1[1]; + struct mtk_clk_cfg vlp_clk_cfg[12]; + u32 reserved2[76]; + u32 vlp_ulposc1_con[3]; + u32 reserved3[9]; + u32 vlp_fqmtr_con[2]; + u32 reserved4[11]; + u32 vlp_ap_pll_con3; + u32 reserved5[3]; + u32 vlp_apll1_con[3]; + u32 reserved6[3]; + u32 vlp_apll2_con[3]; + u32 reserved7[6]; + u32 vlp_pllen_apll_set; + u32 vlp_pllen_apll_clr; + u32 reserved8[19]; + u32 vlp_clk_prot_idle_reg; + u32 vlp_clk_prot_idle_all_reg[2]; + u32 vlp_clk_prot_idle_all_inv_reg[2]; + u32 reserved9[3]; + u32 vlp_clk_fenc_bypass_reg[2]; + u32 reserved10[18]; + u32 vlp_child_enable_mask_con; + u32 vlp_fenc_bypass_con; + u32 vlp_fenc_protected_con; + u32 reserved11[5]; + u32 vlp_ref_clk_req_protected_con; +}; +check_member(mtk_vlp_regs, vlp_clk_cfg_update, 0x0004); +check_member(mtk_vlp_regs, vlp_ulposc1_con, 0x0200); +check_member(mtk_vlp_regs, vlp_fqmtr_con, 0x0230); +check_member(mtk_vlp_regs, vlp_ap_pll_con3, 0x0264); +check_member(mtk_vlp_regs, vlp_clk_prot_idle_reg, 0x0304); +check_member(mtk_vlp_regs, vlp_child_enable_mask_con, 0x0374); +check_member(mtk_vlp_regs, vlp_ref_clk_req_protected_con, 0x0394); + +struct mtk_dispsys_regs { + u32 reserved1[64]; + struct mtk_clk_cfg clk_cfg[2]; +}; +check_member(mtk_dispsys_regs, clk_cfg[0].cfg, 0x0100); +check_member(mtk_dispsys_regs, clk_cfg[1].clr, 0x0118); + +struct mtk_mfgpll_regs { + u32 reserved1[2]; + u32 pll_con[6]; + u32 reserved2[8]; + u32 fqmtr_con[2]; +}; +check_member(mtk_mfgpll_regs, pll_con[0], 0x0008); +check_member(mtk_mfgpll_regs, fqmtr_con[1], 0x0044); + +struct mtk_mcupll_regs { + u32 reserved1[2]; + u32 pll_con[2]; + u32 reserved2[12]; + u32 fqmtr_con[2]; +}; +check_member(mtk_mcupll_regs, pll_con[0], 0x0008); +check_member(mtk_mcupll_regs, fqmtr_con[1], 0x0044); + +/* PLL rate */ enum { - UART_HZ = CLK26M_HZ, + MAINPLL_HZ = 2184UL * MHz, + UNIVPLL_HZ = 2496UL * MHz, + MSDCPLL_HZ = 384 * MHz, + ADSPPLL_HZ = 800 * MHz, + MAINPLL2_HZ = 2184UL * MHz, + UNIVPLL2_HZ = 2496UL * MHz, + MMPLL2_HZ = 2750UL * MHz, + IMGPLL_HZ = 2640UL * MHz, + TVDPLL1_HZ = 594 * MHz, + TVDPLL2_HZ = 594 * MHz, + TVDPLL3_HZ = 594 * MHz, + VLP_APLL1_HZ = 180633600, + VLP_APLL2_HZ = 196608 * KHz, + ARMPLL_LL_HZ = 700 * MHz, + ARMPLL_BL_HZ = 800 * MHz, + ARMPLL_B_HZ = 1250UL * MHz, + CCIPLL_HZ = 471 * MHz, + PTPPLL_HZ = 654 * MHz, + MFGPLL_HZ = 338 * MHz, + MFGPLL_SC0_HZ = 338 * MHz, + MFGPLL_SC1_HZ = 338 * MHz, }; -#endif /* SOC_MEDIATEK_MT8196_PLL_H */ +enum { + CLK26M_HZ = 26 * MHz, + UNIVPLL_D6_D2_HZ = UNIVPLL_HZ / 6 / 2, +}; + +enum { + SPI_HZ = UNIVPLL_D6_D2_HZ, + UART_HZ = CLK26M_HZ, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +enum { + PLL_EN_DELAY = 20, +}; + +enum { + MT8196_PLL_EN = BIT(0), +}; + +u32 mt_get_vlpck_freq(u32 id); +void mt_pll_post_init(void); + +#endif /* SOC_MEDIATEK_MT8196_PLL_H */ diff --git a/src/soc/mediatek/mt8196/pll.c b/src/soc/mediatek/mt8196/pll.c new file mode 100644 index 0000000..59a9b09 --- /dev/null +++ b/src/soc/mediatek/mt8196/pll.c @@ -0,0 +1,1670 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 14.1 + */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pll.h> +#include <timer.h> + +#define VLP_FM_WAIT_TIME_MS 40 + +#define FMIN (1700UL * MHz) +#define FMAX (3800UL * MHz) +#define FIN_RATE (26 * MHz) +#define CON1_PCW_CHG BIT(31) +#define POSTDIV_VAL_MAX 5 +#define POSTDIV_MASK 0x7 +#define POSTDIV_SHIFT 24 +#define PCW_FBITS 14 + +#define FM_PLL_CK 0 +#define FM_PLL_CKDIV_CK 1 + +enum mux_id { + CLK_CK_AXI_SEL, + CLK_CK_MEM_SUB_SEL, + CLK_CK_IO_NOC_SEL, + CLK_CK_P_AXI_SEL, + CLK_CK_PEXTP0_AXI_SEL, + CLK_CK_PEXTP1_USB_AXI_SEL, + CLK_CK_P_FMEM_SUB_SEL, + CLK_CK_PEXPT0_MEM_SUB_SEL, + CLK_CK_PEXTP1_USB_MEM_SUB_SEL, + CLK_CK_P_NOC_SEL, + CLK_CK_EMI_N_SEL, + CLK_CK_EMI_S_SEL, + CLK_CK_EMI_SLICE_N_SEL, + CLK_CK_EMI_SLICE_S_SEL, + CLK_CK_AP2CONN_HOST_SEL, + CLK_CK_ATB_SEL, + CLK_CK_CIRQ_SEL, + CLK_CK_PBUS_156M_SEL, + CLK_CK_NOC_LOW_SEL, + CLK_CK_NOC_MID_SEL, + CLK_CK_EFUSE_SEL, + CLK_CK_MCL3GIC_SEL, + CLK_CK_MCINFRA_SEL, + CLK_CK_DSP_SEL, + CLK_CK_MFG_REF_SEL, + CLK_CK_MFGSC_REF_SEL, + CLK_CK_MFG_EB_SEL, + CLK_CK_UART_SEL, + CLK_CK_SPI0_BCLK_SEL, + CLK_CK_SPI1_BCLK_SEL, + CLK_CK_SPI2_BCLK_SEL, + CLK_CK_SPI3_BCLK_SEL, + CLK_CK_SPI4_BCLK_SEL, + CLK_CK_SPI5_BCLK_SEL, + CLK_CK_SPI6_BCLK_SEL, + CLK_CK_SPI7_BCLK_SEL, + CLK_CK_MSDC_MACRO_1P_SEL, + CLK_CK_MSDC_MACRO_2P_SEL, + CLK_CK_MSDC30_1_SEL, + CLK_CK_MSDC30_2_SEL, + CLK_CK_DISP_PWM_SEL, + CLK_CK_USB_TOP_1P_SEL, + CLK_CK_USB_XHCI_1P_SEL, + CLK_CK_USB_FMCNT_P1_SEL, + CLK_CK_I2C_P_SEL, + CLK_CK_I2C_EAST_SEL, + CLK_CK_I2C_WEST_SEL, + CLK_CK_I2C_NORTH_SEL, + CLK_CK_AES_UFSFDE_SEL, + CLK_CK_SEL, + CLK_CK_MBIST_SEL, + CLK_CK_PEXTP_MBIST_SEL, + CLK_CK_AUD_1_SEL, + CLK_CK_AUD_2_SEL, + CLK_CK_ADSP_SEL, + CLK_CK_ADSP_UARTHUB_BCLK_SEL, + CLK_CK_DPMAIF_MAIN_SEL, + CLK_CK_PWM_SEL, + CLK_CK_MCUPM_SEL, + CLK_CK_SFLASH_SEL, + CLK_CK_IPSEAST_SEL, + CLK_CK_IPSWEST_SEL, + CLK_CK_TL_SEL, + CLK_CK_TL_P1_SEL, + CLK_CK_TL_P2_SEL, + CLK_CK_EMI_INTERFACE_546_SEL, + CLK_CK_SDF_SEL, + CLK_CK_UARTHUB_BCLK_SEL, + CLK_CK_DPSW_CMP_26M_SEL, + CLK_CK_SMAPCK_SEL, + CLK_CK_SSR_PKA_SEL, + CLK_CK_SSR_DMA_SEL, + CLK_CK_SSR_KDF_SEL, + CLK_CK_SSR_RNG_SEL, + CLK_CK_SPU0_SEL, + CLK_CK_SPU1_SEL, + CLK_CK_DXCC_SEL, + CLK_CK_SPU0_BOOT_SEL, + CLK_CK_SPU1_BOOT_SEL, + CLK_CK_SGMII0_REF_325M_SEL, + CLK_CK_SGMII0_REG_SEL, + CLK_CK_SGMII1_REF_325M_SEL, + CLK_CK_SGMII1_REG_SEL, + CLK_CK_GMAC_312P5M_SEL, + CLK_CK_GMAC_125M_SEL, + CLK_CK_GMAC_RMII_SEL, + CLK_CK_GMAC_62P4M_PTP_SEL, + CLK_CK_DUMMY1_SEL, + CLK_CK_DUMMY2_SEL, +}; + +enum cksys2_mux_id { + CLK_CK2_SENINF0_SEL, + CLK_CK2_SENINF1_SEL, + CLK_CK2_SENINF2_SEL, + CLK_CK2_SENINF3_SEL, + CLK_CK2_SENINF4_SEL, + CLK_CK2_SENINF5_SEL, + CLK_CK2_IMG1_SEL, + CLK_CK2_IPE_SEL, + CLK_CK2_CAM_SEL, + CLK_CK2_CAMTM_SEL, + CLK_CK2_DPE_SEL, + CLK_CK2_VDEC_SEL, + CLK_CK2_CCUSYS_SEL, + CLK_CK2_CCUTM_SEL, + CLK_CK2_VENC_SEL, + CLK_CK2_DVO_SEL, + CLK_CK2_DVO_FAVT_SEL, + CLK_CK2_DP1_SEL, + CLK_CK2_DP0_SEL, + CLK_CK2_DISP_SEL, + CLK_CK2_MDP_SEL, + CLK_CK2_MMINFRA_SEL, + CLK_CK2_MMINFRA_SNOC_SEL, + CLK_CK2_MMUP_SEL, + CLK_CK2_DUMMY1_SEL, + CLK_CK2_DUMMY2_SEL, + CLK_CK2_MMINFRA_AO_SEL, +}; + +enum vlp_mux_id { + CLK_VLP_CK_SCP_SEL, + CLK_VLP_CK_SCP_SPI_SEL, + CLK_VLP_CK_SCP_IIC_SEL, + CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, + CLK_VLP_CK_PWRAP_ULPOSC_SEL, + CLK_VLP_CK_SPMI_M_TIA_32K_SEL, + CLK_VLP_CK_APXGPT_26M_BCLK_SEL, + CLK_VLP_CK_DPSW_SEL, + CLK_VLP_CK_DPSW_CENTRAL_SEL, + CLK_VLP_CK_SPMI_M_MST_SEL, + CLK_VLP_CK_DVFSRC_SEL, + CLK_VLP_CK_PWM_VLP_SEL, + CLK_VLP_CK_AXI_VLP_SEL, + CLK_VLP_CK_SYSTIMER_26M_SEL, + CLK_VLP_CK_SSPM_SEL, + CLK_VLP_CK_SRCK_SEL, + CLK_VLP_CK_CAMTG0_SEL, + CLK_VLP_CK_CAMTG1_SEL, + CLK_VLP_CK_CAMTG2_SEL, + CLK_VLP_CK_CAMTG3_SEL, + CLK_VLP_CK_CAMTG4_SEL, + CLK_VLP_CK_CAMTG5_SEL, + CLK_VLP_CK_CAMTG6_SEL, + CLK_VLP_CK_CAMTG7_SEL, + CLK_VLP_CK_IPS_SEL, + CLK_VLP_CK_SSPM_26M_SEL, + CLK_VLP_CK_ULPOSC_SSPM_SEL, + CLK_VLP_CK_VLP_PBUS_26M_SEL, + CLK_VLP_CK_DEBUG_ERR_FLAG_SEL, + CLK_VLP_CK_DPMSRDMA_SEL, + CLK_VLP_CK_VLP_PBUS_156M_SEL, + CLK_VLP_CK_SPM_SEL, + CLK_VLP_CK_MMINFRA_VLP_SEL, + CLK_VLP_CK_USB_TOP_SEL, + CLK_VLP_CK_USB_XHCI_SEL, + CLK_VLP_CK_NOC_VLP_SEL, + CLK_VLP_CK_AUDIO_H_SEL, + CLK_VLP_CK_AUD_ENGEN1_SEL, + CLK_VLP_CK_AUD_ENGEN2_SEL, + CLK_VLP_CK_AUD_INTBUS_SEL, + CLK_VLP_CK_SPVLP_26M_SEL, + CLK_VLP_CK_SPU0_VLP_SEL, + CLK_VLP_CK_SPU1_VLP_SEL, + CLK_VLP_CK_VLP_DUMMY1_SEL, + CLK_VLP_CK_VLP_DUMMY2_SEL, +}; + +#define MUX_UPD(_id, _sys, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &_sys->_clk_cfg.cfg, \ + .set_reg = &_sys->_clk_cfg.set, \ + .clr_reg = &_sys->_clk_cfg.clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &_sys->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +#define CKSYS_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + MUX_UPD(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift) + +#define CKSYS2_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + MUX_UPD(_id, mtk_topckgen2, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift) + +#define VLP_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + MUX_UPD(_id, mtk_vlpsys, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift) + +struct mux_sel { + u8 id; + u8 sel; +}; + +static const struct mux muxes[] = { + CKSYS_MUX_UPD(CLK_CK_AXI_SEL, clk_cfg[0], 0, 3, clk_cfg_update[0], 0), + CKSYS_MUX_UPD(CLK_CK_MEM_SUB_SEL, clk_cfg[0], 8, 4, clk_cfg_update[0], 1), + CKSYS_MUX_UPD(CLK_CK_IO_NOC_SEL, clk_cfg[0], 16, 3, clk_cfg_update[0], 2), + CKSYS_MUX_UPD(CLK_CK_P_AXI_SEL, clk_cfg[0], 24, 3, clk_cfg_update[0], 3), + CKSYS_MUX_UPD(CLK_CK_PEXTP0_AXI_SEL, clk_cfg[1], 0, 3, clk_cfg_update[0], 4), + CKSYS_MUX_UPD(CLK_CK_PEXTP1_USB_AXI_SEL, clk_cfg[1], 8, 3, clk_cfg_update[0], 5), + CKSYS_MUX_UPD(CLK_CK_P_FMEM_SUB_SEL, clk_cfg[1], 16, 4, clk_cfg_update[0], 6), + CKSYS_MUX_UPD(CLK_CK_PEXPT0_MEM_SUB_SEL, clk_cfg[1], 24, 4, clk_cfg_update[0], 7), + CKSYS_MUX_UPD(CLK_CK_PEXTP1_USB_MEM_SUB_SEL, clk_cfg[2], 0, 4, clk_cfg_update[0], 8), + CKSYS_MUX_UPD(CLK_CK_P_NOC_SEL, clk_cfg[2], 8, 4, clk_cfg_update[0], 9), + CKSYS_MUX_UPD(CLK_CK_EMI_N_SEL, clk_cfg[2], 16, 3, clk_cfg_update[0], 10), + CKSYS_MUX_UPD(CLK_CK_EMI_S_SEL, clk_cfg[2], 24, 3, clk_cfg_update[0], 11), + CKSYS_MUX_UPD(CLK_CK_EMI_SLICE_N_SEL, clk_cfg[3], 0, 2, clk_cfg_update[0], 12), + CKSYS_MUX_UPD(CLK_CK_EMI_SLICE_S_SEL, clk_cfg[3], 8, 2, clk_cfg_update[0], 13), + CKSYS_MUX_UPD(CLK_CK_AP2CONN_HOST_SEL, clk_cfg[3], 16, 1, clk_cfg_update[0], 14), + CKSYS_MUX_UPD(CLK_CK_ATB_SEL, clk_cfg[3], 24, 2, clk_cfg_update[0], 15), + CKSYS_MUX_UPD(CLK_CK_CIRQ_SEL, clk_cfg[4], 0, 2, clk_cfg_update[0], 16), + CKSYS_MUX_UPD(CLK_CK_PBUS_156M_SEL, clk_cfg[4], 8, 2, clk_cfg_update[0], 17), + CKSYS_MUX_UPD(CLK_CK_NOC_LOW_SEL, clk_cfg[4], 16, 3, clk_cfg_update[0], 18), + CKSYS_MUX_UPD(CLK_CK_NOC_MID_SEL, clk_cfg[4], 24, 4, clk_cfg_update[0], 19), + CKSYS_MUX_UPD(CLK_CK_EFUSE_SEL, clk_cfg[5], 0, 1, clk_cfg_update[0], 20), + CKSYS_MUX_UPD(CLK_CK_MCL3GIC_SEL, clk_cfg[5], 8, 2, clk_cfg_update[0], 21), + CKSYS_MUX_UPD(CLK_CK_MCINFRA_SEL, clk_cfg[5], 16, 3, clk_cfg_update[0], 22), + CKSYS_MUX_UPD(CLK_CK_DSP_SEL, clk_cfg[5], 24, 3, clk_cfg_update[0], 23), + CKSYS_MUX_UPD(CLK_CK_MFG_REF_SEL, clk_cfg[6], 0, 1, clk_cfg_update[0], 24), + CKSYS_MUX_UPD(CLK_CK_MFGSC_REF_SEL, clk_cfg[6], 8, 1, clk_cfg_update[0], 25), + CKSYS_MUX_UPD(CLK_CK_MFG_EB_SEL, clk_cfg[6], 16, 2, clk_cfg_update[0], 26), + CKSYS_MUX_UPD(CLK_CK_UART_SEL, clk_cfg[6], 24, 2, clk_cfg_update[0], 27), + CKSYS_MUX_UPD(CLK_CK_SPI0_BCLK_SEL, clk_cfg[7], 0, 3, clk_cfg_update[0], 28), + CKSYS_MUX_UPD(CLK_CK_SPI1_BCLK_SEL, clk_cfg[7], 8, 3, clk_cfg_update[0], 29), + CKSYS_MUX_UPD(CLK_CK_SPI2_BCLK_SEL, clk_cfg[7], 16, 3, clk_cfg_update[0], 30), + CKSYS_MUX_UPD(CLK_CK_SPI3_BCLK_SEL, clk_cfg[7], 24, 3, clk_cfg_update[1], 0), + CKSYS_MUX_UPD(CLK_CK_SPI4_BCLK_SEL, clk_cfg[8], 0, 3, clk_cfg_update[1], 1), + CKSYS_MUX_UPD(CLK_CK_SPI5_BCLK_SEL, clk_cfg[8], 8, 3, clk_cfg_update[1], 2), + CKSYS_MUX_UPD(CLK_CK_SPI6_BCLK_SEL, clk_cfg[8], 16, 3, clk_cfg_update[1], 3), + CKSYS_MUX_UPD(CLK_CK_SPI7_BCLK_SEL, clk_cfg[8], 24, 3, clk_cfg_update[1], 4), + CKSYS_MUX_UPD(CLK_CK_MSDC_MACRO_1P_SEL, clk_cfg[9], 0, 3, clk_cfg_update[1], 5), + CKSYS_MUX_UPD(CLK_CK_MSDC_MACRO_2P_SEL, clk_cfg[9], 8, 3, clk_cfg_update[1], 6), + CKSYS_MUX_UPD(CLK_CK_MSDC30_1_SEL, clk_cfg[9], 16, 3, clk_cfg_update[1], 7), + CKSYS_MUX_UPD(CLK_CK_MSDC30_2_SEL, clk_cfg[9], 24, 3, clk_cfg_update[1], 8), + CKSYS_MUX_UPD(CLK_CK_DISP_PWM_SEL, clk_cfg[10], 0, 3, clk_cfg_update[1], 9), + CKSYS_MUX_UPD(CLK_CK_USB_TOP_1P_SEL, clk_cfg[10], 8, 1, clk_cfg_update[1], 10), + CKSYS_MUX_UPD(CLK_CK_USB_XHCI_1P_SEL, clk_cfg[10], 16, 1, clk_cfg_update[1], 11), + CKSYS_MUX_UPD(CLK_CK_USB_FMCNT_P1_SEL, clk_cfg[10], 24, 1, clk_cfg_update[1], 12), + CKSYS_MUX_UPD(CLK_CK_I2C_P_SEL, clk_cfg[11], 0, 3, clk_cfg_update[1], 13), + CKSYS_MUX_UPD(CLK_CK_I2C_EAST_SEL, clk_cfg[11], 8, 3, clk_cfg_update[1], 14), + CKSYS_MUX_UPD(CLK_CK_I2C_WEST_SEL, clk_cfg[11], 16, 3, clk_cfg_update[1], 15), + CKSYS_MUX_UPD(CLK_CK_I2C_NORTH_SEL, clk_cfg[11], 24, 3, clk_cfg_update[1], 16), + CKSYS_MUX_UPD(CLK_CK_AES_UFSFDE_SEL, clk_cfg[12], 0, 3, clk_cfg_update[1], 17), + CKSYS_MUX_UPD(CLK_CK_SEL, clk_cfg[12], 8, 3, clk_cfg_update[1], 18), + CKSYS_MUX_UPD(CLK_CK_MBIST_SEL, clk_cfg[12], 16, 2, clk_cfg_update[1], 19), + CKSYS_MUX_UPD(CLK_CK_PEXTP_MBIST_SEL, clk_cfg[12], 24, 1, clk_cfg_update[1], 20), + CKSYS_MUX_UPD(CLK_CK_AUD_1_SEL, clk_cfg[13], 0, 1, clk_cfg_update[1], 21), + CKSYS_MUX_UPD(CLK_CK_AUD_2_SEL, clk_cfg[13], 8, 1, clk_cfg_update[1], 22), + CKSYS_MUX_UPD(CLK_CK_ADSP_SEL, clk_cfg[13], 16, 1, clk_cfg_update[1], 23), + CKSYS_MUX_UPD(CLK_CK_ADSP_UARTHUB_BCLK_SEL, clk_cfg[13], 24, 2, clk_cfg_update[1], 24), + CKSYS_MUX_UPD(CLK_CK_DPMAIF_MAIN_SEL, clk_cfg[14], 0, 4, clk_cfg_update[1], 25), + CKSYS_MUX_UPD(CLK_CK_PWM_SEL, clk_cfg[14], 8, 2, clk_cfg_update[1], 26), + CKSYS_MUX_UPD(CLK_CK_MCUPM_SEL, clk_cfg[14], 16, 3, clk_cfg_update[1], 27), + CKSYS_MUX_UPD(CLK_CK_SFLASH_SEL, clk_cfg[14], 24, 2, clk_cfg_update[1], 28), + CKSYS_MUX_UPD(CLK_CK_IPSEAST_SEL, clk_cfg[15], 0, 3, clk_cfg_update[1], 29), + CKSYS_MUX_UPD(CLK_CK_IPSWEST_SEL, clk_cfg[15], 8, 3, clk_cfg_update[1], 30), + CKSYS_MUX_UPD(CLK_CK_TL_SEL, clk_cfg[15], 16, 2, clk_cfg_update[2], 0), + CKSYS_MUX_UPD(CLK_CK_TL_P1_SEL, clk_cfg[15], 24, 2, clk_cfg_update[2], 1), + CKSYS_MUX_UPD(CLK_CK_TL_P2_SEL, clk_cfg[16], 0, 2, clk_cfg_update[2], 2), + CKSYS_MUX_UPD(CLK_CK_EMI_INTERFACE_546_SEL, clk_cfg[16], 8, 1, clk_cfg_update[2], 3), + CKSYS_MUX_UPD(CLK_CK_SDF_SEL, clk_cfg[16], 16, 3, clk_cfg_update[2], 4), + CKSYS_MUX_UPD(CLK_CK_UARTHUB_BCLK_SEL, clk_cfg[16], 24, 2, clk_cfg_update[2], 5), + CKSYS_MUX_UPD(CLK_CK_DPSW_CMP_26M_SEL, clk_cfg[17], 0, 1, clk_cfg_update[2], 6), + CKSYS_MUX_UPD(CLK_CK_SMAPCK_SEL, clk_cfg[17], 8, 1, clk_cfg_update[2], 7), + CKSYS_MUX_UPD(CLK_CK_SSR_PKA_SEL, clk_cfg[17], 16, 3, clk_cfg_update[2], 8), + CKSYS_MUX_UPD(CLK_CK_SSR_DMA_SEL, clk_cfg[17], 24, 3, clk_cfg_update[2], 9), + CKSYS_MUX_UPD(CLK_CK_SSR_KDF_SEL, clk_cfg[18], 0, 2, clk_cfg_update[2], 10), + CKSYS_MUX_UPD(CLK_CK_SSR_RNG_SEL, clk_cfg[18], 8, 2, clk_cfg_update[2], 11), + CKSYS_MUX_UPD(CLK_CK_SPU0_SEL, clk_cfg[18], 16, 3, clk_cfg_update[2], 12), + CKSYS_MUX_UPD(CLK_CK_SPU1_SEL, clk_cfg[18], 24, 3, clk_cfg_update[2], 13), + CKSYS_MUX_UPD(CLK_CK_DXCC_SEL, clk_cfg[19], 0, 2, clk_cfg_update[2], 14), + CKSYS_MUX_UPD(CLK_CK_SPU0_BOOT_SEL, clk_cfg[19], 8, 1, clk_cfg_update[2], 15), + CKSYS_MUX_UPD(CLK_CK_SPU1_BOOT_SEL, clk_cfg[19], 16, 1, clk_cfg_update[2], 16), + CKSYS_MUX_UPD(CLK_CK_SGMII0_REF_325M_SEL, clk_cfg[19], 24, 1, clk_cfg_update[2], 17), + CKSYS_MUX_UPD(CLK_CK_SGMII0_REG_SEL, clk_cfg[20], 0, 1, clk_cfg_update[2], 18), + CKSYS_MUX_UPD(CLK_CK_SGMII1_REF_325M_SEL, clk_cfg[20], 8, 1, clk_cfg_update[2], 19), + CKSYS_MUX_UPD(CLK_CK_SGMII1_REG_SEL, clk_cfg[20], 16, 1, clk_cfg_update[2], 20), + CKSYS_MUX_UPD(CLK_CK_GMAC_312P5M_SEL, clk_cfg[20], 24, 1, clk_cfg_update[2], 21), + CKSYS_MUX_UPD(CLK_CK_GMAC_125M_SEL, clk_cfg[21], 0, 1, clk_cfg_update[2], 22), + CKSYS_MUX_UPD(CLK_CK_GMAC_RMII_SEL, clk_cfg[21], 8, 1, clk_cfg_update[2], 23), + CKSYS_MUX_UPD(CLK_CK_GMAC_62P4M_PTP_SEL, clk_cfg[21], 16, 2, clk_cfg_update[2], 24), + CKSYS_MUX_UPD(CLK_CK_DUMMY1_SEL, clk_cfg[21], 24, 2, clk_cfg_update[2], 25), + CKSYS_MUX_UPD(CLK_CK_DUMMY2_SEL, clk_cfg[22], 0, 2, clk_cfg_update[2], 26), +}; + +static const struct mux_sel mux_sels[] = { + { .id = CLK_CK_AXI_SEL, .sel = 5 }, + { .id = CLK_CK_MEM_SUB_SEL, .sel = 10 }, + { .id = CLK_CK_IO_NOC_SEL, .sel = 5 }, + { .id = CLK_CK_P_AXI_SEL, .sel = 7 }, + { .id = CLK_CK_PEXTP0_AXI_SEL, .sel = 7 }, + { .id = CLK_CK_PEXTP1_USB_AXI_SEL, .sel = 7 }, + { .id = CLK_CK_P_FMEM_SUB_SEL, .sel = 10 }, + { .id = CLK_CK_PEXPT0_MEM_SUB_SEL, .sel = 10 }, + { .id = CLK_CK_PEXTP1_USB_MEM_SUB_SEL, .sel = 10 }, + { .id = CLK_CK_P_NOC_SEL, .sel = 11 }, + { .id = CLK_CK_EMI_N_SEL, .sel = 5 }, + { .id = CLK_CK_EMI_S_SEL, .sel = 5 }, + { .id = CLK_CK_EMI_SLICE_N_SEL, .sel = 2 }, + { .id = CLK_CK_EMI_SLICE_S_SEL, .sel = 2 }, + { .id = CLK_CK_AP2CONN_HOST_SEL, .sel = 1 }, + { .id = CLK_CK_ATB_SEL, .sel = 3 }, + { .id = CLK_CK_CIRQ_SEL, .sel = 2 }, + { .id = CLK_CK_PBUS_156M_SEL, .sel = 3 }, + { .id = CLK_CK_NOC_LOW_SEL, .sel = 5 }, + { .id = CLK_CK_NOC_MID_SEL, .sel = 7 }, + { .id = CLK_CK_EFUSE_SEL, .sel = 0 }, + { .id = CLK_CK_MCL3GIC_SEL, .sel = 3 }, + { .id = CLK_CK_MCINFRA_SEL, .sel = 5 }, + { .id = CLK_CK_DSP_SEL, .sel = 5 }, + { .id = CLK_CK_MFG_REF_SEL, .sel = 0 }, + { .id = CLK_CK_MFGSC_REF_SEL, .sel = 0 }, + { .id = CLK_CK_MFG_EB_SEL, .sel = 3 }, + { .id = CLK_CK_UART_SEL, .sel = 0 }, + { .id = CLK_CK_SPI0_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_SPI1_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_SPI2_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_SPI3_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_SPI4_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_SPI5_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_SPI6_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_SPI7_BCLK_SEL, .sel = 7 }, + { .id = CLK_CK_MSDC_MACRO_1P_SEL, .sel = 4 }, + { .id = CLK_CK_MSDC_MACRO_2P_SEL, .sel = 4 }, + { .id = CLK_CK_MSDC30_1_SEL, .sel = 4 }, + { .id = CLK_CK_MSDC30_2_SEL, .sel = 4 }, + { .id = CLK_CK_DISP_PWM_SEL, .sel = 5 }, + { .id = CLK_CK_USB_TOP_1P_SEL, .sel = 1 }, + { .id = CLK_CK_USB_XHCI_1P_SEL, .sel = 1 }, + { .id = CLK_CK_USB_FMCNT_P1_SEL, .sel = 1 }, + { .id = CLK_CK_I2C_P_SEL, .sel = 2 }, + { .id = CLK_CK_I2C_EAST_SEL, .sel = 2 }, + { .id = CLK_CK_I2C_WEST_SEL, .sel = 2 }, + { .id = CLK_CK_I2C_NORTH_SEL, .sel = 2 }, + { .id = CLK_CK_AES_UFSFDE_SEL, .sel = 5 }, + { .id = CLK_CK_SEL, .sel = 6 }, + { .id = CLK_CK_MBIST_SEL, .sel = 3 }, + { .id = CLK_CK_PEXTP_MBIST_SEL, .sel = 1 }, + { .id = CLK_CK_AUD_1_SEL, .sel = 1 }, + { .id = CLK_CK_AUD_2_SEL, .sel = 1 }, + { .id = CLK_CK_ADSP_SEL, .sel = 1 }, + { .id = CLK_CK_ADSP_UARTHUB_BCLK_SEL, .sel = 0 }, + { .id = CLK_CK_DPMAIF_MAIN_SEL, .sel = 3 }, + { .id = CLK_CK_PWM_SEL, .sel = 0 }, + { .id = CLK_CK_MCUPM_SEL, .sel = 4 }, + { .id = CLK_CK_SFLASH_SEL, .sel = 2 }, + { .id = CLK_CK_IPSEAST_SEL, .sel = 1 }, + { .id = CLK_CK_IPSWEST_SEL, .sel = 1 }, + { .id = CLK_CK_TL_SEL, .sel = 2 }, + { .id = CLK_CK_TL_P1_SEL, .sel = 3 }, + { .id = CLK_CK_TL_P2_SEL, .sel = 2 }, + { .id = CLK_CK_EMI_INTERFACE_546_SEL, .sel = 1 }, + { .id = CLK_CK_SDF_SEL, .sel = 5 }, + { .id = CLK_CK_UARTHUB_BCLK_SEL, .sel = 0 }, + { .id = CLK_CK_DPSW_CMP_26M_SEL, .sel = 1 }, + { .id = CLK_CK_SMAPCK_SEL, .sel = 1 }, + { .id = CLK_CK_SSR_PKA_SEL, .sel = 5 }, + { .id = CLK_CK_SSR_DMA_SEL, .sel = 5 }, + { .id = CLK_CK_SSR_KDF_SEL, .sel = 3 }, + { .id = CLK_CK_SSR_RNG_SEL, .sel = 3 }, + { .id = CLK_CK_SPU0_SEL, .sel = 1 }, + { .id = CLK_CK_SPU1_SEL, .sel = 1 }, + { .id = CLK_CK_DXCC_SEL, .sel = 0 }, + { .id = CLK_CK_SPU0_BOOT_SEL, .sel = 1 }, + { .id = CLK_CK_SPU1_BOOT_SEL, .sel = 1 }, + { .id = CLK_CK_SGMII0_REF_325M_SEL, .sel = 1 }, + { .id = CLK_CK_SGMII0_REG_SEL, .sel = 1 }, + { .id = CLK_CK_SGMII1_REF_325M_SEL, .sel = 1 }, + { .id = CLK_CK_SGMII1_REG_SEL, .sel = 1 }, + { .id = CLK_CK_GMAC_312P5M_SEL, .sel = 1 }, + { .id = CLK_CK_GMAC_125M_SEL, .sel = 1 }, + { .id = CLK_CK_GMAC_RMII_SEL, .sel = 1 }, + { .id = CLK_CK_GMAC_62P4M_PTP_SEL, .sel = 2 }, + { .id = CLK_CK_DUMMY1_SEL, .sel = 3 }, + { .id = CLK_CK_DUMMY2_SEL, .sel = 3 }, +}; + +static const struct mux cksys2_muxes[] = { + CKSYS2_MUX_UPD(CLK_CK2_SENINF0_SEL, cksys2_clk_cfg[0], 0, 4, + cksys2_clk_cfg_update, 0), + CKSYS2_MUX_UPD(CLK_CK2_SENINF1_SEL, cksys2_clk_cfg[0], 8, 4, + cksys2_clk_cfg_update, 1), + CKSYS2_MUX_UPD(CLK_CK2_SENINF2_SEL, cksys2_clk_cfg[0], 16, 4, + cksys2_clk_cfg_update, 2), + CKSYS2_MUX_UPD(CLK_CK2_SENINF3_SEL, cksys2_clk_cfg[0], 24, 4, + cksys2_clk_cfg_update, 3), + CKSYS2_MUX_UPD(CLK_CK2_SENINF4_SEL, cksys2_clk_cfg[1], 0, 4, + cksys2_clk_cfg_update, 4), + CKSYS2_MUX_UPD(CLK_CK2_SENINF5_SEL, cksys2_clk_cfg[1], 8, 4, + cksys2_clk_cfg_update, 5), + CKSYS2_MUX_UPD(CLK_CK2_IMG1_SEL, cksys2_clk_cfg[1], 16, 4, + cksys2_clk_cfg_update, 6), + CKSYS2_MUX_UPD(CLK_CK2_IPE_SEL, cksys2_clk_cfg[1], 24, 4, + cksys2_clk_cfg_update, 7), + CKSYS2_MUX_UPD(CLK_CK2_CAM_SEL, cksys2_clk_cfg[2], 0, 4, + cksys2_clk_cfg_update, 8), + CKSYS2_MUX_UPD(CLK_CK2_CAMTM_SEL, cksys2_clk_cfg[2], 8, 3, + cksys2_clk_cfg_update, 9), + CKSYS2_MUX_UPD(CLK_CK2_DPE_SEL, cksys2_clk_cfg[2], 16, 4, + cksys2_clk_cfg_update, 10), + CKSYS2_MUX_UPD(CLK_CK2_VDEC_SEL, cksys2_clk_cfg[2], 24, 4, + cksys2_clk_cfg_update, 11), + CKSYS2_MUX_UPD(CLK_CK2_CCUSYS_SEL, cksys2_clk_cfg[3], 0, 4, + cksys2_clk_cfg_update, 12), + CKSYS2_MUX_UPD(CLK_CK2_CCUTM_SEL, cksys2_clk_cfg[3], 8, 3, + cksys2_clk_cfg_update, 13), + CKSYS2_MUX_UPD(CLK_CK2_VENC_SEL, cksys2_clk_cfg[3], 16, 4, + cksys2_clk_cfg_update, 14), + CKSYS2_MUX_UPD(CLK_CK2_DVO_SEL, cksys2_clk_cfg[3], 24, 3, + cksys2_clk_cfg_update, 15), + CKSYS2_MUX_UPD(CLK_CK2_DVO_FAVT_SEL, cksys2_clk_cfg[4], 0, 3, + cksys2_clk_cfg_update, 16), + CKSYS2_MUX_UPD(CLK_CK2_DP1_SEL, cksys2_clk_cfg[4], 8, 3, + cksys2_clk_cfg_update, 17), + CKSYS2_MUX_UPD(CLK_CK2_DP0_SEL, cksys2_clk_cfg[4], 16, 3, + cksys2_clk_cfg_update, 18), + CKSYS2_MUX_UPD(CLK_CK2_DISP_SEL, cksys2_clk_cfg[4], 24, 4, + cksys2_clk_cfg_update, 19), + CKSYS2_MUX_UPD(CLK_CK2_MDP_SEL, cksys2_clk_cfg[5], 0, 4, + cksys2_clk_cfg_update, 20), + CKSYS2_MUX_UPD(CLK_CK2_MMINFRA_SEL, cksys2_clk_cfg[5], 8, 4, + cksys2_clk_cfg_update, 21), + CKSYS2_MUX_UPD(CLK_CK2_MMINFRA_SNOC_SEL, cksys2_clk_cfg[5], 16, 4, + cksys2_clk_cfg_update, 22), + CKSYS2_MUX_UPD(CLK_CK2_MMUP_SEL, cksys2_clk_cfg[5], 24, 3, + cksys2_clk_cfg_update, 23), + CKSYS2_MUX_UPD(CLK_CK2_DUMMY1_SEL, cksys2_clk_cfg[6], 0, 2, + cksys2_clk_cfg_update, 24), + CKSYS2_MUX_UPD(CLK_CK2_DUMMY2_SEL, cksys2_clk_cfg[6], 8, 2, + cksys2_clk_cfg_update, 25), + CKSYS2_MUX_UPD(CLK_CK2_MMINFRA_AO_SEL, cksys2_clk_cfg[6], 16, 2, + cksys2_clk_cfg_update, 26), +}; + +static const struct mux_sel cksys2_mux_sels[] = { + { .id = CLK_CK2_SENINF0_SEL, .sel = 9 }, + { .id = CLK_CK2_SENINF1_SEL, .sel = 9 }, + { .id = CLK_CK2_SENINF2_SEL, .sel = 9 }, + { .id = CLK_CK2_SENINF3_SEL, .sel = 9 }, + { .id = CLK_CK2_SENINF4_SEL, .sel = 9 }, + { .id = CLK_CK2_SENINF5_SEL, .sel = 9 }, + { .id = CLK_CK2_IMG1_SEL, .sel = 7 }, + { .id = CLK_CK2_IPE_SEL, .sel = 10 }, + { .id = CLK_CK2_CAM_SEL, .sel = 14 }, + { .id = CLK_CK2_CAMTM_SEL, .sel = 4 }, + { .id = CLK_CK2_DPE_SEL, .sel = 8 }, + { .id = CLK_CK2_VDEC_SEL, .sel = 12 }, + { .id = CLK_CK2_CCUSYS_SEL, .sel = 12 }, + { .id = CLK_CK2_CCUTM_SEL, .sel = 4 }, + { .id = CLK_CK2_VENC_SEL, .sel = 13 }, + { .id = CLK_CK2_DVO_SEL, .sel = 4 }, + { .id = CLK_CK2_DVO_FAVT_SEL, .sel = 6 }, + { .id = CLK_CK2_DP1_SEL, .sel = 4 }, + { .id = CLK_CK2_DP0_SEL, .sel = 4 }, + { .id = CLK_CK2_DISP_SEL, .sel = 8 }, + { .id = CLK_CK2_MDP_SEL, .sel = 12 }, + { .id = CLK_CK2_MMINFRA_SEL, .sel = 13 }, + { .id = CLK_CK2_MMINFRA_SNOC_SEL, .sel = 11 }, + { .id = CLK_CK2_MMUP_SEL, .sel = 7 }, + { .id = CLK_CK2_DUMMY1_SEL, .sel = 3 }, + { .id = CLK_CK2_DUMMY2_SEL, .sel = 3 }, + { .id = CLK_CK2_MMINFRA_AO_SEL, .sel = 2 }, +}; + +static const struct mux vlp_muxes[] = { + VLP_MUX_UPD(CLK_VLP_CK_SCP_SEL, vlp_clk_cfg[0], 0, 3, + vlp_clk_cfg_update[0], 0), + VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_clk_cfg[0], 8, 2, + vlp_clk_cfg_update[0], 1), + VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_clk_cfg[0], 16, 2, + vlp_clk_cfg_update[0], 2), + VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, vlp_clk_cfg[0], 24, 3, + vlp_clk_cfg_update[0], 3), + VLP_MUX_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_clk_cfg[1], 0, 2, + vlp_clk_cfg_update[0], 4), + VLP_MUX_UPD(CLK_VLP_CK_SPMI_M_TIA_32K_SEL, vlp_clk_cfg[1], 8, 3, + vlp_clk_cfg_update[0], 5), + VLP_MUX_UPD(CLK_VLP_CK_APXGPT_26M_BCLK_SEL, vlp_clk_cfg[1], 16, 1, + vlp_clk_cfg_update[0], 6), + VLP_MUX_UPD(CLK_VLP_CK_DPSW_SEL, vlp_clk_cfg[1], 24, 2, + vlp_clk_cfg_update[0], 7), + VLP_MUX_UPD(CLK_VLP_CK_DPSW_CENTRAL_SEL, vlp_clk_cfg[2], 0, 2, + vlp_clk_cfg_update[0], 8), + VLP_MUX_UPD(CLK_VLP_CK_SPMI_M_MST_SEL, vlp_clk_cfg[2], 8, 2, + vlp_clk_cfg_update[0], 9), + VLP_MUX_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_clk_cfg[2], 16, 1, + vlp_clk_cfg_update[0], 10), + VLP_MUX_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_clk_cfg[2], 24, 3, + vlp_clk_cfg_update[0], 11), + VLP_MUX_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_clk_cfg[3], 0, 3, + vlp_clk_cfg_update[0], 12), + VLP_MUX_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_clk_cfg[3], 8, 1, + vlp_clk_cfg_update[0], 13), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_SEL, vlp_clk_cfg[3], 16, 3, + vlp_clk_cfg_update[0], 14), + VLP_MUX_UPD(CLK_VLP_CK_SRCK_SEL, vlp_clk_cfg[3], 24, 1, + vlp_clk_cfg_update[0], 15), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG0_SEL, vlp_clk_cfg[4], 0, 4, + vlp_clk_cfg_update[0], 16), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG1_SEL, vlp_clk_cfg[4], 8, 4, + vlp_clk_cfg_update[0], 17), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG2_SEL, vlp_clk_cfg[4], 16, 4, + vlp_clk_cfg_update[0], 18), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG3_SEL, vlp_clk_cfg[4], 24, 4, + vlp_clk_cfg_update[0], 19), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG4_SEL, vlp_clk_cfg[5], 0, 4, + vlp_clk_cfg_update[0], 20), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG5_SEL, vlp_clk_cfg[5], 8, 4, + vlp_clk_cfg_update[0], 21), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG6_SEL, vlp_clk_cfg[5], 16, 4, + vlp_clk_cfg_update[0], 22), + VLP_MUX_UPD(CLK_VLP_CK_CAMTG7_SEL, vlp_clk_cfg[5], 24, 4, + vlp_clk_cfg_update[0], 23), + VLP_MUX_UPD(CLK_VLP_CK_IPS_SEL, vlp_clk_cfg[6], 0, 2, + vlp_clk_cfg_update[0], 24), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_26M_SEL, vlp_clk_cfg[6], 8, 1, + vlp_clk_cfg_update[0], 25), + VLP_MUX_UPD(CLK_VLP_CK_ULPOSC_SSPM_SEL, vlp_clk_cfg[6], 16, 2, + vlp_clk_cfg_update[0], 26), + VLP_MUX_UPD(CLK_VLP_CK_VLP_PBUS_26M_SEL, vlp_clk_cfg[6], 24, 1, + vlp_clk_cfg_update[0], 27), + VLP_MUX_UPD(CLK_VLP_CK_DEBUG_ERR_FLAG_SEL, vlp_clk_cfg[7], 0, 1, + vlp_clk_cfg_update[0], 28), + VLP_MUX_UPD(CLK_VLP_CK_DPMSRDMA_SEL, vlp_clk_cfg[7], 8, 1, + vlp_clk_cfg_update[0], 29), + VLP_MUX_UPD(CLK_VLP_CK_VLP_PBUS_156M_SEL, vlp_clk_cfg[7], 16, 2, + vlp_clk_cfg_update[0], 30), + VLP_MUX_UPD(CLK_VLP_CK_SPM_SEL, vlp_clk_cfg[7], 24, 1, + vlp_clk_cfg_update[1], 0), + VLP_MUX_UPD(CLK_VLP_CK_MMINFRA_VLP_SEL, vlp_clk_cfg[8], 0, 2, + vlp_clk_cfg_update[1], 1), + VLP_MUX_UPD(CLK_VLP_CK_USB_TOP_SEL, vlp_clk_cfg[8], 8, 1, + vlp_clk_cfg_update[1], 2), + VLP_MUX_UPD(CLK_VLP_CK_USB_XHCI_SEL, vlp_clk_cfg[8], 16, 1, + vlp_clk_cfg_update[1], 3), + VLP_MUX_UPD(CLK_VLP_CK_NOC_VLP_SEL, vlp_clk_cfg[8], 24, 2, + vlp_clk_cfg_update[1], 4), + VLP_MUX_UPD(CLK_VLP_CK_AUDIO_H_SEL, vlp_clk_cfg[9], 0, 2, + vlp_clk_cfg_update[1], 5), + VLP_MUX_UPD(CLK_VLP_CK_AUD_ENGEN1_SEL, vlp_clk_cfg[9], 8, 2, + vlp_clk_cfg_update[1], 6), + VLP_MUX_UPD(CLK_VLP_CK_AUD_ENGEN2_SEL, vlp_clk_cfg[9], 16, 2, + vlp_clk_cfg_update[1], 7), + VLP_MUX_UPD(CLK_VLP_CK_AUD_INTBUS_SEL, vlp_clk_cfg[9], 24, 2, + vlp_clk_cfg_update[1], 8), + VLP_MUX_UPD(CLK_VLP_CK_SPVLP_26M_SEL, vlp_clk_cfg[10], 0, 1, + vlp_clk_cfg_update[1], 9), + VLP_MUX_UPD(CLK_VLP_CK_SPU0_VLP_SEL, vlp_clk_cfg[10], 8, 3, + vlp_clk_cfg_update[1], 10), + VLP_MUX_UPD(CLK_VLP_CK_SPU1_VLP_SEL, vlp_clk_cfg[10], 16, 3, + vlp_clk_cfg_update[1], 11), + VLP_MUX_UPD(CLK_VLP_CK_VLP_DUMMY1_SEL, vlp_clk_cfg[10], 24, 3, + vlp_clk_cfg_update[1], 12), + VLP_MUX_UPD(CLK_VLP_CK_VLP_DUMMY2_SEL, vlp_clk_cfg[11], 0, 3, + vlp_clk_cfg_update[1], 13), +}; + +static const struct mux_sel vlp_mux_sels[] = { + { .id = CLK_VLP_CK_SCP_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_SPI_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_IIC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_PWRAP_ULPOSC_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_SPMI_M_TIA_32K_SEL, .sel = 2 }, + { .id = CLK_VLP_CK_APXGPT_26M_BCLK_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_DPSW_SEL, .sel = 2 }, + { .id = CLK_VLP_CK_DPSW_CENTRAL_SEL, .sel = 2 }, + { .id = CLK_VLP_CK_SPMI_M_MST_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_DVFSRC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_PWM_VLP_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_AXI_VLP_SEL, .sel = 4 }, + { .id = CLK_VLP_CK_SYSTIMER_26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SSPM_SEL, .sel = 4 }, + { .id = CLK_VLP_CK_SRCK_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_CAMTG0_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_CAMTG1_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_CAMTG2_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_CAMTG3_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_CAMTG4_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_CAMTG5_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_CAMTG6_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_CAMTG7_SEL, .sel = 7 }, + { .id = CLK_VLP_CK_IPS_SEL, .sel = 2 }, + { .id = CLK_VLP_CK_SSPM_26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_ULPOSC_SSPM_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_VLP_PBUS_26M_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_DEBUG_ERR_FLAG_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_DPMSRDMA_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_VLP_PBUS_156M_SEL, .sel = 3 }, + { .id = CLK_VLP_CK_SPM_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_MMINFRA_VLP_SEL, .sel = 2 }, + { .id = CLK_VLP_CK_USB_TOP_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_USB_XHCI_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_NOC_VLP_SEL, .sel = 2 }, + { .id = CLK_VLP_CK_AUDIO_H_SEL, .sel = 3 }, + { .id = CLK_VLP_CK_AUD_ENGEN1_SEL, .sel = 3 }, + { .id = CLK_VLP_CK_AUD_ENGEN2_SEL, .sel = 3 }, + { .id = CLK_VLP_CK_AUD_INTBUS_SEL, .sel = 3 }, + { .id = CLK_VLP_CK_SPVLP_26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SPU0_VLP_SEL, .sel = 6 }, + { .id = CLK_VLP_CK_SPU1_VLP_SEL, .sel = 6 }, + { .id = CLK_VLP_CK_VLP_DUMMY1_SEL, .sel = 4 }, + { .id = CLK_VLP_CK_VLP_DUMMY2_SEL, .sel = 4 }, +}; + +enum pll_id { + CLK_APMIXED_MAINPLL, + CLK_APMIXED_UNIVPLL, + CLK_APMIXED_MSDCPLL, + CLK_APMIXED_ADSPPLL, + CLK_APMIXED2_MAINPLL2, + CLK_APMIXED2_UNIVPLL2, + CLK_APMIXED2_MMPLL2, + CLK_APMIXED2_IMGPLL, + CLK_APMIXED2_TVDPLL1, + CLK_APMIXED2_TVDPLL2, + CLK_APMIXED2_TVDPLL3, + CLK_VLP_APLL1, + CLK_VLP_APLL2, +}; + +enum mcusys_pll_id { + CLK_CPLL_ARMPLL_LL, + CLK_CPBL_ARMPLL_BL, + CLK_CPB_ARMPLL_B, + CLK_CCIPLL, + CLK_PTPPLL, +}; + +enum mfg_pll_id { + CLK_MFG_AO_MFGPLL, + CLK_MFGSC0_AO_MFGPLL_SC0, + CLK_MFGSC1_AO_MFGPLL_SC1, +}; + +struct rate { + u8 id; + u32 rate; +}; + +static const struct rate pll_rates[] = { + { .id = CLK_APMIXED_MAINPLL, .rate = MAINPLL_HZ }, + { .id = CLK_APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, + { .id = CLK_APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, + { .id = CLK_APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, + { .id = CLK_APMIXED2_MAINPLL2, .rate = MAINPLL2_HZ }, + { .id = CLK_APMIXED2_UNIVPLL2, .rate = UNIVPLL2_HZ }, + { .id = CLK_APMIXED2_MMPLL2, .rate = MMPLL2_HZ }, + { .id = CLK_APMIXED2_IMGPLL, .rate = IMGPLL_HZ }, + { .id = CLK_APMIXED2_TVDPLL1, .rate = TVDPLL1_HZ }, + { .id = CLK_APMIXED2_TVDPLL2, .rate = TVDPLL2_HZ }, + { .id = CLK_APMIXED2_TVDPLL3, .rate = TVDPLL3_HZ }, + { .id = CLK_VLP_APLL1, .rate = VLP_APLL1_HZ }, + { .id = CLK_VLP_APLL2, .rate = VLP_APLL2_HZ }, +}; + +static const struct rate mcusys_pll_rates[] = { + { .id = CLK_CPLL_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, + { .id = CLK_CPBL_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, + { .id = CLK_CPB_ARMPLL_B, .rate = ARMPLL_B_HZ }, + { .id = CLK_CCIPLL, .rate = CCIPLL_HZ }, + { .id = CLK_PTPPLL, .rate = PTPPLL_HZ }, +}; + +static const struct rate mfg_pll_rates[] = { + { .id = CLK_MFG_AO_MFGPLL, .rate = MFGPLL_HZ }, + { .id = CLK_MFGSC0_AO_MFGPLL_SC0, .rate = MFGPLL_SC0_HZ }, + { .id = CLK_MFGSC1_AO_MFGPLL_SC1, .rate = MFGPLL_SC1_HZ }, +}; + +static const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +#define PLL_SYS(_id, _sys, _reg, _rstb, _pcwbits, _div_reg, _div_shift, \ + _pcw_reg, _pcw_shift, _div_rate) \ + [_id] = { \ + .reg = &_sys->_reg, \ + .rstb_shift = _rstb, \ + .pcwbits = _pcwbits, \ + .div_reg = &_sys->_div_reg, \ + .div_shift = _div_shift, \ + .pcw_reg = &_sys->_pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_rate = _div_rate, \ + } + +static const struct pll plls[] = { + PLL_SYS(CLK_APMIXED_MAINPLL, mtk_apmixed, mainpll_con[0], 23, 22, + mainpll_con[1], 24, mainpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_UNIVPLL, mtk_apmixed, univpll_con[0], 23, 22, + univpll_con[1], 24, univpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MSDCPLL, mtk_apmixed, msdcpll_con[0], NO_RSTB_SHIFT, 22, + msdcpll_con[1], 24, msdcpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_ADSPPLL, mtk_apmixed, adsppll_con[0], NO_RSTB_SHIFT, 22, + adsppll_con[1], 24, adsppll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED2_MAINPLL2, mtk_apmixed2, mainpll2_con[0], 23, 22, + mainpll2_con[1], 24, mainpll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED2_UNIVPLL2, mtk_apmixed2, univpll2_con[0], 23, 22, + univpll2_con[1], 24, univpll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED2_MMPLL2, mtk_apmixed2, mmpll2_con[0], 23, 22, + mmpll2_con[1], 24, mmpll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED2_IMGPLL, mtk_apmixed2, imgpll_con[0], 23, 22, + imgpll_con[1], 24, imgpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED2_TVDPLL1, mtk_apmixed2, tvdpll1_con[0], NO_RSTB_SHIFT, 22, + tvdpll1_con[1], 24, tvdpll1_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED2_TVDPLL2, mtk_apmixed2, tvdpll2_con[0], NO_RSTB_SHIFT, 22, + tvdpll2_con[1], 24, tvdpll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED2_TVDPLL3, mtk_apmixed2, tvdpll3_con[0], NO_RSTB_SHIFT, 22, + tvdpll3_con[1], 24, tvdpll3_con[1], 0, pll_div_rate), + PLL_SYS(CLK_VLP_APLL1, mtk_vlpsys, vlp_apll1_con[0], NO_RSTB_SHIFT, 32, + vlp_apll1_con[1], 24, vlp_apll1_con[2], 0, pll_div_rate), + PLL_SYS(CLK_VLP_APLL2, mtk_vlpsys, vlp_apll2_con[0], NO_RSTB_SHIFT, 32, + vlp_apll2_con[1], 24, vlp_apll2_con[2], 0, pll_div_rate), +}; + +static const struct pll mcusys_plls[] = { + PLL_SYS(CLK_CPLL_ARMPLL_LL, mtk_armpll_ll, pll_con[0], NO_RSTB_SHIFT, 22, + pll_con[1], 24, pll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_CPBL_ARMPLL_BL, mtk_armpll_bl, pll_con[0], NO_RSTB_SHIFT, 22, + pll_con[1], 24, pll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_CPB_ARMPLL_B, mtk_armpll_b, pll_con[0], NO_RSTB_SHIFT, 22, + pll_con[1], 24, pll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_CCIPLL, mtk_ccipll, pll_con[0], NO_RSTB_SHIFT, 22, + pll_con[1], 24, pll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_PTPPLL, mtk_ptppll, pll_con[0], NO_RSTB_SHIFT, 22, + pll_con[1], 24, pll_con[1], 0, pll_div_rate), +}; + +static const struct pll mfg_plls[] = { + PLL_SYS(CLK_MFG_AO_MFGPLL, mtk_mfgpll, pll_con[3], + NO_RSTB_SHIFT, 22, pll_con[1], 24, pll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_MFGSC0_AO_MFGPLL_SC0, mtk_mfgpll_sc0, pll_con[3], + NO_RSTB_SHIFT, 22, pll_con[1], 24, pll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_MFGSC1_AO_MFGPLL_SC1, mtk_mfgpll_sc1, pll_con[3], + NO_RSTB_SHIFT, 22, pll_con[1], 24, pll_con[1], 0, pll_div_rate), +}; + +enum fmeter_id { + VLP_CKSYS_CTRL, + MFGPLL_CTRL, + MFGPLL_SC0_CTRL, + MFGPLL_SC1_CTRL, + CCIPLL_CTRL, + ARMPLL_LL_CTRL, + ARMPLL_BL_CTRL, + ARMPLL_B_CTRL, + PTPPLL_CTRL, +}; + +struct fmeter_data { + u8 id; + void *pll_con0; + void *pll_con1; + void *pll_con5; + void *con0; + void *con1; +}; + +static const struct fmeter_data fmd[] = { + [VLP_CKSYS_CTRL] = { + VLP_CKSYS_CTRL, NULL, NULL, NULL, + &mtk_vlpsys->vlp_fqmtr_con[0], &mtk_vlpsys->vlp_fqmtr_con[1] }, + [MFGPLL_CTRL] = { + MFGPLL_CTRL, + &mtk_mfgpll->pll_con[0], &mtk_mfgpll->pll_con[1], + &mtk_mfgpll->pll_con[5], &mtk_mfgpll->fqmtr_con[0], + &mtk_mfgpll->fqmtr_con[1] }, + [MFGPLL_SC0_CTRL] = { + MFGPLL_SC0_CTRL, + &mtk_mfgpll_sc0->pll_con[0], &mtk_mfgpll_sc0->pll_con[1], + &mtk_mfgpll_sc0->pll_con[5], &mtk_mfgpll_sc0->fqmtr_con[0], + &mtk_mfgpll_sc0->fqmtr_con[1] }, + [MFGPLL_SC1_CTRL] = { + MFGPLL_SC1_CTRL, + &mtk_mfgpll_sc1->pll_con[0], &mtk_mfgpll_sc1->pll_con[1], + &mtk_mfgpll_sc1->pll_con[5], &mtk_mfgpll_sc1->fqmtr_con[0], + &mtk_mfgpll_sc1->fqmtr_con[1] }, + [CCIPLL_CTRL] = { + CCIPLL_CTRL, + &mtk_ccipll->pll_con[0], &mtk_ccipll->pll_con[1], 0, + &mtk_ccipll->fqmtr_con[0], &mtk_ccipll->fqmtr_con[1] }, + [ARMPLL_LL_CTRL] = { + ARMPLL_LL_CTRL, + &mtk_armpll_ll->pll_con[0], &mtk_armpll_ll->pll_con[1], 0, + &mtk_armpll_ll->fqmtr_con[0], &mtk_armpll_ll->fqmtr_con[1] }, + [ARMPLL_BL_CTRL] = { + ARMPLL_BL_CTRL, + &mtk_armpll_bl->pll_con[0], &mtk_armpll_bl->pll_con[1], 0, + &mtk_armpll_bl->fqmtr_con[0], &mtk_armpll_bl->fqmtr_con[1] }, + [ARMPLL_B_CTRL] = { + ARMPLL_B_CTRL, + &mtk_armpll_b->pll_con[0], &mtk_armpll_b->pll_con[1], 0, + &mtk_armpll_b->fqmtr_con[0], &mtk_armpll_b->fqmtr_con[1] }, + [PTPPLL_CTRL] = { + PTPPLL_CTRL, + &mtk_ptppll->pll_con[0], &mtk_ptppll->pll_con[1], 0, + &mtk_ptppll->fqmtr_con[0], &mtk_ptppll->fqmtr_con[1] }, +}; + +#define PM_DUMMY 63 + +#define VOTE_OFS(ofs) ((void *)(uintptr_t)(VOTE_BASE + ofs)) + +#define VOTE_CTRL VOTE_OFS(0x150C) +#define VOTE_DCM VOTE_OFS(0x1510) +#define VOTE_REG_EN0 VOTE_OFS(0x1514) +#define VOTE_REG_EN1 VOTE_OFS(0x1518) +#define VOTE_REG_EN6 VOTE_OFS(0x152C) +#define VOTE_APB_M_REG0 VOTE_OFS(0x1530) +#define VOTE_APB_M_REG5 VOTE_OFS(0x1544) +#define VOTE_TIMEOUT0 VOTE_OFS(0x154C) +#define VOTE_TIMEOUT1 VOTE_OFS(0x1550) +#define VOTE_REG_KEY VOTE_OFS(0x1560) +#define VOTE_MTCMOS_MODE_SEL_0 VOTE_OFS(0x1570) +#define VOTE_MTCMOS_MODE_SEL_1 VOTE_OFS(0x1574) +#define VOTE_MUX_MAPPING_LINK_EN_0 VOTE_OFS(0x1578) +#define VOTE_MUX_MAPPING_LINK_EN_1 VOTE_OFS(0x157C) +#define VOTE_MUX_MODE_SEL_0 VOTE_OFS(0x1580) +#define VOTE_MUX_MODE_SEL_1 VOTE_OFS(0x1584) +#define VOTE_MUX_MAPPING_LINK_EN_2 VOTE_OFS(0x1588) +#define VOTE_MUX_MODE_SEL_2 VOTE_OFS(0x158C) +#define VOTE_MTCMOS_DIS_MUX_0 VOTE_OFS(0x1590) +#define VOTE_MTCMOS_DIS_MUX_1 VOTE_OFS(0x1594) + +#define VOTE_LOCK_REG_CFG 0x80000000 + +#define VOTE_CG_MAP_MTCMOS(x) VOTE_OFS(0x15A0 + (x) * 0x4) +#define VOTE_CG_SET_ADDR(x) VOTE_OFS(0x1600 + (x) * 0x8) +#define VOTE_CG_CLR_ADDR(x) VOTE_OFS(0x1604 + (x) * 0x8) + +#define VOTE_CG_MTCMOS_DUMMY_RANGE_START1 0 +#define VOTE_CG_MTCMOS_DUMMY_RANGE_END1 14 +#define VOTE_CG_MTCMOS_DUMMY_RANGE_START2 30 +#define VOTE_CG_MTCMOS_DUMMY_RANGE_END2 49 + +#define VOTE_MAP(_id, _base, _set_val, _clr_val)\ + [_id] = { \ + .map_base = _base, \ + .set_addr = _set_val, \ + .clr_addr = _clr_val, \ + } + +struct range { + u32 start; + u32 end; +}; + +struct vote_map { + u32 map_base; + u16 set_addr; + u16 clr_addr; +}; + +struct cg_mtcmos_map { + u8 cg_idx; + u8 mtcmos_idx; +}; + +static const struct vote_map vote_maps[] = { + VOTE_MAP(0, IMP_IIC_WRAP_N_BASE, 0xE04, 0xE08), + VOTE_MAP(1, PERICFG_AO_BASE, 0x30, 0x2C), + VOTE_MAP(2, SSR_TOP_BASE, 0x0, 0x0), + VOTE_MAP(3, CKSYS_BASE, 0x0078, 0x0074), + VOTE_MAP(4, CKSYS_BASE, 0x0088, 0x0084), + VOTE_MAP(5, CKSYS_BASE, 0x0098, 0x0094), + VOTE_MAP(6, CKSYS_BASE, 0x00C8, 0x00C4), + VOTE_MAP(7, CKSYS_BASE, 0x0118, 0x0114), + VOTE_MAP(8, CKSYS_BASE, 0x0128, 0x0124), + VOTE_MAP(9, VLP_CKSYS_BASE, 0x0058, 0x0054), + VOTE_MAP(10, VLP_CKSYS_BASE, 0x0068, 0x0064), +}; + +static const struct range vote_cg_mtcmos_dummy_range[] = { + { VOTE_CG_MTCMOS_DUMMY_RANGE_START1, VOTE_CG_MTCMOS_DUMMY_RANGE_END1 }, + { VOTE_CG_MTCMOS_DUMMY_RANGE_START2, VOTE_CG_MTCMOS_DUMMY_RANGE_END2 }, +}; + +enum { + PM_ISP_TRAW, + PM_ISP_DIP, + PM_ISP_MAIN, + PM_ISP_VCORE, + PM_ISP_WPE_EIS, + PM_ISP_WPE_TNR, + PM_ISP_WPE_LITE, + PM_VDE0, + PM_VDE1, + PM_VDE_VCORE0, + PM_VEN0, + PM_VEN1, + PM_VEN2, + PM_CAM_MRAW, + PM_CAM_RAWA, + PM_CAM_RAWB, + PM_CAM_RAWC, + PM_CAM_RMSA, + PM_CAM_RMSB, + PM_CAM_RMSC, + PM_CAM_MAIN, + PM_CAM_VCORE, + PM_CAM_CCU, + PM_CAM_CCU_AO, + PM_DISP_VCORE, + PM_DIS0, + PM_DIS1, + PM_OVL0, + PM_OVL1, + PM_DISP_EDPTX, + PM_DISP_DPTX, + PM_MML0, + PM_MML1, + PM_MMINFRA0, + PM_MMINFRA1, + PM_MMINFRA_AO, + PM_DP_TX, + PM_CSI_BS_RX, + PM_CSI_LS_RX, + PM_DSI_PHY0, + PM_DSI_PHY1, + PM_DSI_PHY2, + PM_DUMMY1 = 63, + PM_DUMMY2, +}; + +enum { + CLK_SENINF0_SEL, + CLK_SENINF1_SEL, + CLK_SENINF2_SEL, + CLK_SENINF3_SEL, + CLK_SENINF4_SEL, + CLK_SENINF5_SEL, + CLK_IMG1_SEL, + CLK_IPE_SEL, + CLK_CAM_SEL, + CLK_CAMTM_SEL, + CLK_DPE_SEL, + CLK_VDEC_SEL, + CLK_CCUSYS_SEL, + CLK_CCUTM_SEL, + CLK_VENC_SEL, + CLK_DVO_SEL, + CLK_DVO_FAVT_SEL, + CLK_DP1_SEL, + CLK_DP0_SEL, + CLK_DISP_SEL, + CLK_MDP_SEL, + CLK_MMINFRA_SEL, + CLK_MMINFRA_SNOC_SEL, + CLK_MMUP_SEL, + CLK_MMINFRA_AO_SEL, +}; + +#define MMVOTE_OFS(ofs) ((void *)(uintptr_t)(MMVOTE_BASE + ofs)) + +#define MMVOTE_MTCMOS_MODE_SEL_0 MMVOTE_OFS(0x1570) +#define MMVOTE_MTCMOS_DIS_MUX_0 MMVOTE_OFS(0x1590) +#define MMVOTE_MTCMOS_DIS_MUX_1 MMVOTE_OFS(0x1594) + +#define MMVOTE_PRE_CLK_MUX(x) MMVOTE_OFS(0x4180 + (x) * 0x4) +#define MMVOTE_MTCMOS_MAP_MTCMOS(x) MMVOTE_OFS(0x5484 + (x) * 0x4) +#define MMVOTE_MTCMOS_MAP_MUX(t, x) MMVOTE_OFS(0x5108 + (t) * 0xc + (x) * 0x4) + +#define MMVOTE_CTRL MMVOTE_OFS(0x150C) +#define MMVOTE_REG_EN0 MMVOTE_OFS(0x1514) +#define MMVOTE_REG_EN1 MMVOTE_OFS(0x1518) +#define MMVOTE_REG_EN6 MMVOTE_OFS(0x152C) +#define MMVOTE_APB_M_REG0 MMVOTE_OFS(0x1530) +#define MMVOTE_APB_M_REG5 MMVOTE_OFS(0x1544) +#define MMVOTE_TIMEOUT0 MMVOTE_OFS(0x154C) +#define MMVOTE_TIMEOUT1 MMVOTE_OFS(0x1550) +#define MMVOTE_REG_KEY MMVOTE_OFS(0x1560) + +#define MMVOTE_UNLOCK_REG_CFG 0x10907 + +#define MMVOTE_CG_MAP_MTCMOS(x) MMVOTE_OFS(0x15A0 + (x) * 0x4) +#define MMVOTE_CG_SET_ADDR(x) MMVOTE_OFS(0x1600 + (x) * 0x8) +#define MMVOTE_CG_CLR_ADDR(x) MMVOTE_OFS(0x1604 + (x) * 0x8) + +#define MMVOTE_CG_MTCMOS_MAP_COUNT 50 + +#define MMVOTE_CG_MTCMOS_DUMMY_RANGE_START1 0 +#define MMVOTE_CG_MTCMOS_DUMMY_RANGE_END1 28 +#define MMVOTE_CG_MTCMOS_DUMMY_RANGE_START2 30 +#define MMVOTE_CG_MTCMOS_DUMMY_RANGE_END2 49 + +static const struct vote_map mmvote_maps[] = { + VOTE_MAP(0, MMVOTE_CAM_MAIN_R1A_BASE, 0x8, 0x4), + VOTE_MAP(1, MMVOTE_CAM_MAIN_R1A_BASE, 0xC0, 0xC0), + VOTE_MAP(2, MMVOTE_MMSYS1_CONFIG_BASE, 0x108, 0x104), + VOTE_MAP(3, MMVOTE_MMSYS1_CONFIG_BASE, 0x118, 0x114), + VOTE_MAP(4, MMVOTE_MMSYS_CONFIG_BASE, 0x108, 0x104), + VOTE_MAP(5, MMVOTE_MMSYS_CONFIG_BASE, 0x118, 0x114), + VOTE_MAP(6, MMVOTE_DISP_VDISP_AO_CONFIG_BASE, 0x108, 0x104), + VOTE_MAP(7, MMVOTE_IMGSYS_MAIN_BASE, 0x58, 0x54), + VOTE_MAP(8, MMVOTE_IMGSYS_MAIN_BASE, 0x8, 0x4), + VOTE_MAP(9, MMVOTE_IMG_VCORE_D1A_BASE, 0x8, 0x4), + VOTE_MAP(10, MMVOTE_OVLSYS1_CONFIG_BASE, 0x108, 0x104), + VOTE_MAP(11, MMVOTE_OVLSYS1_CONFIG_BASE, 0x118, 0x114), + VOTE_MAP(12, MMVOTE_OVLSYS_CONFIG_BASE, 0x108, 0x104), + VOTE_MAP(13, MMVOTE_OVLSYS_CONFIG_BASE, 0x118, 0x114), + VOTE_MAP(14, MMVOTE_CCU_MAIN_BASE, 0x8, 0x4), + VOTE_MAP(15, MMVOTE_VDEC_GCON_BASE, 0x8, 0xC), + VOTE_MAP(16, MMVOTE_VDEC_GCON_BASE, 0x200, 0x204), + VOTE_MAP(17, MMVOTE_VDEC_GCON_BASE, 0x0, 0x4), + VOTE_MAP(18, MMVOTE_VDEC_SOC_GCON_BASE, 0x8, 0xC), + VOTE_MAP(19, MMVOTE_VDEC_SOC_GCON_BASE, 0x200, 0x204), + VOTE_MAP(20, MMVOTE_VDEC_SOC_GCON_BASE, 0x0, 0x4), + VOTE_MAP(21, MMVOTE_VDEC_SOC_GCON_BASE, 0x1EC, 0x1EC), + VOTE_MAP(22, MMVOTE_VDEC_SOC_GCON_BASE, 0x1E0, 0x1E0), + VOTE_MAP(23, MMVOTE_VENC_GCON_BASE, 0x4, 0x8), + VOTE_MAP(24, MMVOTE_VENC_GCON_BASE, 0x14, 0x10), + VOTE_MAP(25, MMVOTE_VENC_GCON_CORE1_BASE, 0x4, 0x8), + VOTE_MAP(26, MMVOTE_VENC_GCON_CORE1_BASE, 0x14, 0x10), + VOTE_MAP(27, MMVOTE_VENC_GCON_CORE2_BASE, 0x4, 0x8), + VOTE_MAP(28, MMVOTE_VENC_GCON_CORE2_BASE, 0x14, 0x10), + VOTE_MAP(30, CKSYS_GP2_BASE, 0x0028, 0x0024), + VOTE_MAP(31, CKSYS_GP2_BASE, 0x0038, 0x0034), + VOTE_MAP(32, CKSYS_GP2_BASE, 0x0048, 0x0044), + VOTE_MAP(33, CKSYS_GP2_BASE, 0x0058, 0x0054), + VOTE_MAP(34, CKSYS_GP2_BASE, 0x0068, 0x0064), + VOTE_MAP(35, CKSYS_GP2_BASE, 0x0078, 0x0074), +}; + +static const struct range mmvote_cg_mtcmos_dummy_range[] = { + { MMVOTE_CG_MTCMOS_DUMMY_RANGE_START1, MMVOTE_CG_MTCMOS_DUMMY_RANGE_END1 }, + { MMVOTE_CG_MTCMOS_DUMMY_RANGE_START2, MMVOTE_CG_MTCMOS_DUMMY_RANGE_END2 }, +}; + +static const struct range mmvote_mtcmos_mtcmos_dummy_range[] = { + { PM_ISP_TRAW, PM_DSI_PHY2 }, + { PM_DUMMY1, PM_DUMMY2 }, +}; + +#define CG_VDEC_SOC_GCON_1 19 + +static const struct cg_mtcmos_map mmvote_cg_mtcmos_table[] = { + { CG_VDEC_SOC_GCON_1, PM_VDE_VCORE0 }, + { CG_VDEC_SOC_GCON_1, PM_VDE0 }, +}; + +struct mtcmos_mux_map { + u8 mtcmos_idx; + u8 mux_idx; +}; + +static const struct mtcmos_mux_map mmvote_mtcmos_mux_table[] = { + { PM_ISP_TRAW, CLK_IMG1_SEL }, + { PM_ISP_DIP, CLK_IMG1_SEL }, + { PM_ISP_MAIN, CLK_IMG1_SEL }, + { PM_ISP_MAIN, CLK_IPE_SEL }, + { PM_ISP_VCORE, CLK_IMG1_SEL }, + { PM_ISP_VCORE, CLK_IPE_SEL }, + { PM_ISP_WPE_EIS, CLK_IMG1_SEL }, + { PM_ISP_WPE_TNR, CLK_IMG1_SEL }, + { PM_ISP_WPE_LITE, CLK_IMG1_SEL }, + { PM_VDE0, CLK_VDEC_SEL }, + { PM_VDE1, CLK_VDEC_SEL }, + { PM_VDE_VCORE0, CLK_VDEC_SEL }, + { PM_VEN0, CLK_VENC_SEL }, + { PM_VEN1, CLK_VENC_SEL }, + { PM_VEN2, CLK_VENC_SEL }, + { PM_CAM_MRAW, CLK_DPE_SEL }, + { PM_CAM_RAWA, CLK_CAM_SEL }, + { PM_CAM_RAWB, CLK_CAM_SEL }, + { PM_CAM_RAWC, CLK_CAM_SEL }, + { PM_CAM_RMSA, CLK_CAM_SEL }, + { PM_CAM_RMSB, CLK_CAM_SEL }, + { PM_CAM_RMSC, CLK_CAM_SEL }, + { PM_CAM_MAIN, CLK_CAM_SEL }, + { PM_CAM_VCORE, CLK_CAM_SEL }, + { PM_CAM_VCORE, CLK_CAMTM_SEL }, + { PM_CAM_VCORE, CLK_CCUSYS_SEL }, + { PM_CAM_CCU, CLK_CCUSYS_SEL }, + { PM_CAM_CCU, CLK_CCUTM_SEL }, + { PM_CAM_CCU_AO, CLK_CCUSYS_SEL }, + { PM_DISP_VCORE, CLK_DISP_SEL }, + { PM_DIS0, CLK_DISP_SEL }, + { PM_DIS1, CLK_DISP_SEL }, + { PM_OVL0, CLK_DISP_SEL }, + { PM_OVL1, CLK_DISP_SEL }, + { PM_DISP_EDPTX, CLK_DISP_SEL }, + { PM_DISP_DPTX, CLK_DISP_SEL }, + { PM_MML0, CLK_MDP_SEL }, + { PM_MML1, CLK_MDP_SEL }, + { PM_MMINFRA0, CLK_MMINFRA_SEL }, + { PM_MMINFRA0, CLK_MMINFRA_SNOC_SEL }, + { PM_MMINFRA1, CLK_MMINFRA_SEL }, + { PM_MMINFRA1, CLK_MMINFRA_SNOC_SEL }, + { PM_MMINFRA_AO, CLK_MMINFRA_AO_SEL }, + { PM_CSI_BS_RX, CLK_SENINF2_SEL }, + { PM_CSI_BS_RX, CLK_SENINF3_SEL }, + { PM_CSI_BS_RX, CLK_SENINF4_SEL }, + { PM_CSI_BS_RX, CLK_SENINF5_SEL }, + { PM_CSI_LS_RX, CLK_SENINF0_SEL }, + { PM_CSI_LS_RX, CLK_SENINF1_SEL }, +}; + +#define CG_MTCMOS_FILED_WIDTH 7 +#define CG_MTCMOS_FIELD_COUNT 4 +#define CG_MTCMOS_FIELD_MASK GENMASK(6, 0) + +#define MTCMOS_MTCMOS_FILED_WIDTH 8 +#define MTCMOS_MTCMOS_FIELD_COUNT 4 +#define MTCMOS_MTCMOS_FIELD_MASK GENMASK(7, 0) +#define MTCMOS_LEVEL_SHIFT 6 + +static void vote_init(void) +{ + u32 group; + u32 offset; + void *addr; + u32 start, end; + + /* Vote map */ + for (int i = 0; i < ARRAY_SIZE(vote_maps); i++) { + if (!vote_maps[i].map_base) + continue; + + write32(VOTE_CG_SET_ADDR(i), vote_maps[i].map_base + vote_maps[i].set_addr); + write32(VOTE_CG_CLR_ADDR(i), vote_maps[i].map_base + vote_maps[i].clr_addr); + } + + /* VOTE_REG_EN0 0x1514 = 0x89FF8001 */ + write32(VOTE_REG_EN0, 0x89FF8001); + + /* VOTE_REG_EN1 0x1518 = 0x1FF */ + write32(VOTE_REG_EN1, 0x1FF); + + /* VOTE_REG_EN6 0x152C = 0x1400 */ + write32(VOTE_REG_EN6, BIT(12) | BIT(10)); + + /* VOTE_DCM 0x1510 = 0x1E7 */ + write32(VOTE_DCM, 0x1E7); + + /* VOTE_APB_M_REG0 0x1530 = 0x6 */ + write32(VOTE_APB_M_REG0, 0x6); + + /* VOTE_CTRL 0x150C = 0x80000001 */ + write32(VOTE_CTRL, BIT(31) | BIT(0)); + + /* Disable Timeout:0x0 */ + write32(VOTE_TIMEOUT0, 0); + write32(VOTE_TIMEOUT1, 0); + + /* VOTE_APB_M_REG0 0x1530[25:24] = 0x3 */ + setbits32(VOTE_APB_M_REG0, BIT(25) | BIT(24)); + + /* CG map MTCMOS */ + for (int i = 0; i < ARRAY_SIZE(mmvote_cg_mtcmos_dummy_range); i++) { + start = vote_cg_mtcmos_dummy_range[i].start; + end = vote_cg_mtcmos_dummy_range[i].end; + + for (int cg_idx = start; cg_idx <= end; cg_idx++) { + group = cg_idx / CG_MTCMOS_FIELD_COUNT; + offset = cg_idx % CG_MTCMOS_FIELD_COUNT; + offset *= CG_MTCMOS_FILED_WIDTH; + addr = VOTE_CG_MAP_MTCMOS(group); + + clrsetbits32(addr, CG_MTCMOS_FIELD_MASK << offset, PM_DUMMY << offset); + } + } + + /* Link setup */ + write32(VOTE_MTCMOS_MODE_SEL_0, 0); + write32(VOTE_MTCMOS_MODE_SEL_1, 0); + write32(VOTE_MUX_MAPPING_LINK_EN_0, 0); + write32(VOTE_MUX_MAPPING_LINK_EN_1, 0); + write32(VOTE_MUX_MODE_SEL_0, 0); + write32(VOTE_MUX_MODE_SEL_1, 0); + write32(VOTE_MUX_MAPPING_LINK_EN_2, 0); + write32(VOTE_MUX_MODE_SEL_2, 0); + write32(VOTE_MTCMOS_DIS_MUX_0, 0xFFFFFFFF); + write32(VOTE_MTCMOS_DIS_MUX_1, 0xFFFFFFFF); + + /* Lock donmain */ + write32(VOTE_REG_KEY, VOTE_LOCK_REG_CFG); + + /* Vote enable */ + write32(VOTE_APB_M_REG5, BIT(0)); +} + +static void mmvote_init(void) +{ + u32 group; + u32 offset; + u32 level_offset; + void *addr; + u32 start, end; + + /* Vote setup */ + for (int i = 0; i < ARRAY_SIZE(mmvote_maps); i++) { + if (!mmvote_maps[i].map_base) + continue; + + write32(MMVOTE_CG_SET_ADDR(i), + mmvote_maps[i].map_base + mmvote_maps[i].set_addr); + write32(MMVOTE_CG_CLR_ADDR(i), + mmvote_maps[i].map_base + mmvote_maps[i].clr_addr); + + } + + /* MMVOTE_REG_EN0 0x1514 = 0xBDFF8001 */ + write32(MMVOTE_REG_EN0, 0xBDFF8001); + + /* MMVOTE_REG_EN1 0x1518 = 0x1CB */ + write32(MMVOTE_REG_EN1, 0x1CB); + + /* MMVOTE_REG_EN6 0x152C = 0x1400 */ + write32(MMVOTE_REG_EN6, BIT(12) | BIT(10)); + + /* MMVOTE_APB_M_REG0 0x1530 = 0x7 */ + write32(MMVOTE_APB_M_REG0, BIT(2) | BIT(1) | BIT(0)); + + /* MMVOTE_CTRL 0x150C = 0x80000001 */ + write32(MMVOTE_CTRL, BIT(31) | BIT(0)); + + /* Disable Timeout: 0x0 */ + write32(MMVOTE_TIMEOUT0, 0); + write32(MMVOTE_TIMEOUT1, 0); + + /* MMVOTE_APB_M_REG0 0x1530[25:24] = 0x3 */ + setbits32(MMVOTE_APB_M_REG0, BIT(25) | BIT(24)); + + /* CG map MTCMOS */ + for (int i = 0; i < ARRAY_SIZE(mmvote_cg_mtcmos_dummy_range); i++) { + start = mmvote_cg_mtcmos_dummy_range[i].start; + end = mmvote_cg_mtcmos_dummy_range[i].end; + + for (int cg_idx = start; cg_idx <= end; cg_idx++) { + group = cg_idx / CG_MTCMOS_FIELD_COUNT; + offset = cg_idx % CG_MTCMOS_FIELD_COUNT; + offset *= CG_MTCMOS_FILED_WIDTH; + addr = MMVOTE_CG_MAP_MTCMOS(group); + + clrsetbits32(addr, CG_MTCMOS_FIELD_MASK << offset, PM_DUMMY1 << offset); + } + } + + for (int i = 0; i < ARRAY_SIZE(mmvote_cg_mtcmos_table); i++) { + group = mmvote_cg_mtcmos_table[i].cg_idx / CG_MTCMOS_FIELD_COUNT; + offset = mmvote_cg_mtcmos_table[i].cg_idx % CG_MTCMOS_FIELD_COUNT; + offset *= CG_MTCMOS_FILED_WIDTH; + addr = MMVOTE_CG_MAP_MTCMOS(group); + + clrsetbits32(addr, + CG_MTCMOS_FIELD_MASK << offset, + mmvote_cg_mtcmos_table[i].mtcmos_idx << offset); + } + + /* MTCMOS map MTCMOS */ + for (int i = 0; i < ARRAY_SIZE(mmvote_mtcmos_mtcmos_dummy_range); i++) { + start = mmvote_mtcmos_mtcmos_dummy_range[i].start; + end = mmvote_mtcmos_mtcmos_dummy_range[i].end; + + for (int mtcmos_idx = start; mtcmos_idx <= end; mtcmos_idx++) { + group = mtcmos_idx / MTCMOS_MTCMOS_FIELD_COUNT; + offset = mtcmos_idx % MTCMOS_MTCMOS_FIELD_COUNT; + offset *= MTCMOS_MTCMOS_FILED_WIDTH; + level_offset = offset + MTCMOS_LEVEL_SHIFT; + addr = MMVOTE_MTCMOS_MAP_MTCMOS(group); + + clrsetbits32(addr, MTCMOS_MTCMOS_FIELD_MASK << offset, + mtcmos_idx << offset | 3 << level_offset); + } + } + + /* MTCMOS map MUX */ + for (int i = 0; i < ARRAY_SIZE(mmvote_mtcmos_mux_table); i++) { + group = mmvote_mtcmos_mux_table[i].mux_idx / 32; + addr = MMVOTE_MTCMOS_MAP_MUX(mmvote_mtcmos_mux_table[i].mtcmos_idx, group); + + setbits32(addr, BIT(mmvote_mtcmos_mux_table[i].mux_idx % 32)); + } + write32(MMVOTE_PRE_CLK_MUX(0), 0x1785FC0); + write32(MMVOTE_PRE_CLK_MUX(1), 0); + + /* Link Setup */ + write32(MMVOTE_MTCMOS_DIS_MUX_0, 0x0); + write32(MMVOTE_MTCMOS_DIS_MUX_1, 0x3E0); + write32(MMVOTE_MTCMOS_MODE_SEL_0, 0xFFBFFFFF); + + /* Lock domain */ + write32(MMVOTE_REG_KEY, MMVOTE_UNLOCK_REG_CFG); + + /* mmvote enable */ + write32(MMVOTE_APB_M_REG5, BIT(0)); +} + +static u32 mt_get_subsys_freq(const struct fmeter_data *fm_data, u32 id) +{ + u32 freq, output; + u32 clk_div = 1, post_div = 1; + bool ckdiv_en = false; + + if (fm_data->pll_con0 != NULL) { + ckdiv_en = !!(read32(fm_data->pll_con0) & BIT(16)); + setbits32(fm_data->pll_con0, BIT(16) | BIT(12)); + } + + if (fm_data->id == MFGPLL_CTRL || fm_data->id == MFGPLL_SC0_CTRL || + fm_data->id == MFGPLL_SC1_CTRL) + setbits32(fm_data->pll_con5, BIT(4)); + + write32(fm_data->con0, 0); + setbits32(fm_data->con0, BIT(15)); + + if (fm_data->id == VLP_CKSYS_CTRL) + clrsetbits32(fm_data->con0, GENMASK(20, 16), id << 16); + else + clrsetbits32(fm_data->con0, GENMASK(2, 0), id); + + clrsetbits32(fm_data->con1, GENMASK(31, 16), 0x1FF << 16); + + clrbits32(fm_data->con0, GENMASK(31, 24)); + + setbits32(fm_data->con0, BIT(12)); + setbits32(fm_data->con0, BIT(4)); + clrbits32(fm_data->con0, BIT(1) | BIT(0)); + + /* wait frequency meter finish */ + if (fm_data->id == VLP_CKSYS_CTRL) { + udelay(VLP_FM_WAIT_TIME_MS); + } else if (!wait_us(1000, !(read32(fm_data->con0) & BIT(4)))) { + printk(BIOS_ERR, "mtcmos_vote disable timeout\n"); + return 0; + } + + output = read32(fm_data->con1) & 0xFFFF; + freq = output * 26000 / 512; + + if (fm_data->pll_con0 != NULL && fm_data->id != VLP_CKSYS_CTRL && id == FM_PLL_CKDIV_CK) + clk_div = (read32(fm_data->pll_con0) & GENMASK(10, 7)) >> 7; + + if (clk_div == 0) + clk_div = 1; + + if (fm_data->pll_con1 != NULL && fm_data->id != VLP_CKSYS_CTRL && id == FM_PLL_CKDIV_CK) + post_div = BIT((read32(fm_data->pll_con1) & GENMASK(26, 24)) >> 24); + + freq = freq * clk_div / post_div; + + if (fm_data->pll_con0 != NULL) { + if (ckdiv_en) + clrbits32(fm_data->pll_con0, BIT(12)); + else + clrbits32(fm_data->pll_con0, BIT(16) | BIT(12)); + } + + if (fm_data->id == MFGPLL_CTRL || fm_data->id == MFGPLL_SC0_CTRL || + fm_data->id == MFGPLL_SC1_CTRL) + clrbits32(fm_data->pll_con5, BIT(4)); + + write32(fm_data->con0, 0x8000); + + printk(BIOS_INFO, "meter[%d:%d] = %d Khz(output: %d, clk_div: %d, post_div: %d)\n", + fm_data->id, id, freq, output, clk_div, post_div); + + return freq; +} + +u32 mt_get_vlpck_freq(u32 id) +{ + return mt_get_subsys_freq(&fmd[VLP_CKSYS_CTRL], id); +} + +static inline u32 mt_get_cpu_freq(u32 id) +{ + return mt_get_subsys_freq(&fmd[id], FM_PLL_CKDIV_CK); +} + +static inline u32 mt_get_gpu_freq(u32 id) +{ + return mt_get_subsys_freq(&fmd[id], FM_PLL_CK); +} + +static void mt_dump_cpu_freq(void) +{ + mt_get_cpu_freq(ARMPLL_B_CTRL); + mt_get_cpu_freq(ARMPLL_BL_CTRL); + mt_get_cpu_freq(ARMPLL_LL_CTRL); + mt_get_cpu_freq(CCIPLL_CTRL); + mt_get_cpu_freq(PTPPLL_CTRL); +} + +static void mt_dump_gpu_freq(void) +{ + mt_get_gpu_freq(MFGPLL_CTRL); + mt_get_gpu_freq(MFGPLL_SC0_CTRL); + mt_get_gpu_freq(MFGPLL_SC1_CTRL); +} + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + write32(&mtk_apmixed->ref_clk_req_protected_con, 0); + write32(&mtk_apmixed2->gp2_ref_clk_req_protected_con, 0); + write32(&mtk_vlpsys->vlp_ref_clk_req_protected_con, 0); + + /* Set xPLL frequency */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) + pll_set_rate(&plls[pll_rates[i].id], pll_rates[i].rate); + + setbits32(&mtk_apmixed->univpll_con[0], BIT(17)); + setbits32(&mtk_apmixed2->univpll2_con[0], BIT(17)); + + setbits32(&mtk_vlpsys->vlp_ap_pll_con3, BIT(5) | BIT(0)); + + clrbits32(&mtk_mcusys->cpu_src_clk_config, BIT(0)); + clrbits32(&mtk_mcusys->dsu_pcsm_clk_src_config, BIT(0)); + clrbits32(&mtk_mcusys->infra_clk_src_config, BIT(0)); + + /* [1]: clk_en = 0 */ + clrbits32(&mtk_mcusys->cpu_src_clk_config, BIT(1)); + clrbits32(&mtk_mcusys->dsu_pcsm_clk_src_config, BIT(1)); + clrbits32(&mtk_mcusys->infra_clk_src_config, BIT(1)); + clrbits32(&mtk_mcusys->ses_clk_free_ck_en, BIT(1)); + + /* MCUSYS PLL set frequency */ + for (i = 0; i < ARRAY_SIZE(mcusys_pll_rates); i++) + pll_set_rate(&mcusys_plls[mcusys_pll_rates[i].id], mcusys_pll_rates[i].rate); + + /* PLL all enable */ + write32(&mtk_apmixed->pllen_all_set, 0xF); + write32(&mtk_apmixed2->gp2_pllen_all_set, 0x7F); + write32(&mtk_vlpsys->vlp_pllen_apll_set, 0x3); + + setbits32(&mtk_ccipll->pll_con[0], BIT(0)); + setbits32(&mtk_armpll_ll->pll_con[0], BIT(0)); + setbits32(&mtk_armpll_bl->pll_con[0], BIT(0)); + setbits32(&mtk_armpll_b->pll_con[0], BIT(0)); + setbits32(&mtk_ptppll->pll_con[0], BIT(0)); + + setbits32(&mtk_spm_mtcmos->spm2gpupm_con, BIT(4)); + + /* Set MFGPLLs Frequency */ + for (i = 0; i < ARRAY_SIZE(mfg_pll_rates); i++) + pll_set_rate(&mfg_plls[mfg_pll_rates[i].id], mfg_pll_rates[i].rate); + + setbits32(&mtk_mfgpll->pll_con[0], BIT(0)); + setbits32(&mtk_mfgpll_sc0->pll_con[0], BIT(0)); + setbits32(&mtk_mfgpll_sc1->pll_con[0], BIT(0)); + + /* Wait PLL stable (20us) */ + udelay(PLL_EN_DELAY); + + setbits32(&mtk_mcusys->ses_clk_free_ck_en, BIT(1)); + setbits32(&mtk_mcusys->cpu_src_clk_config, BIT(2) | BIT(1) | BIT(0)); + setbits32(&mtk_mcusys->dsu_pcsm_clk_src_config, BIT(2) | BIT(1) | BIT(0)); + setbits32(&mtk_mcusys->infra_clk_src_config, BIT(2) | BIT(1) | BIT(0)); + + /* pll all rstb */ + write32(&mtk_apmixed->pll_div_rstb_all_set, 0x3); + write32(&mtk_apmixed2->gp2_pll_div_rstb_all_set, 0xF); + + setbits32(&mtk_apmixed->mainpll_con[0], 0xFF000000); + setbits32(&mtk_apmixed->univpll_con[0], 0xFF000000); + + clrsetbits32(&mtk_mcusys->cpu_plldiv0_cfg, GENMASK(10, 8), 0x100); + clrsetbits32(&mtk_mcusys->cpu_plldiv1_cfg, GENMASK(10, 8), 0x100); + clrsetbits32(&mtk_mcusys->cpu_plldiv2_cfg, GENMASK(10, 8), 0x100); + clrsetbits32(&mtk_mcusys->bus_plldiv_cfg, GENMASK(10, 8), 0x100); + + /* [10]: toggle mux update */ + setbits32(&mtk_mcusys->cpu_plldiv0_cfg, BIT(10)); + setbits32(&mtk_mcusys->cpu_plldiv1_cfg, BIT(10)); + setbits32(&mtk_mcusys->cpu_plldiv2_cfg, BIT(10)); + setbits32(&mtk_mcusys->bus_plldiv_cfg, BIT(10)); + + clrbits32(&mtk_apinfra_io_ctrl->clk_io_intx_bus_ctrl, BIT(4) | BIT(2)); + + clrbits32(&mtk_apinfra_io_noc->clk_io_noc_ctrl, BIT(4) | BIT(2)); + + /* free run */ + clrbits32(&mtk_apinfra_mem_ctrl->vdnr_dcm_mem_intx_bus_ctrl, GENMASK(4, 2)); + clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[0], BIT(7) | BIT(4)); + clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[1], BIT(21)); + clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[2], BIT(22)); + clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[3], BIT(20)); + clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[4], BIT(24)); + clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[5], BIT(23)); + clrbits32(&mtk_apinfra_mem_noc->vdnr_mem_intf_par_bus_ctrl, BIT(4) | BIT(2)); + + /* BUS idle to cksys protect release */ + write32(&mtk_topckgen->clk_prot_idle_reg, 0xFFFFFFFF); + write32(&mtk_topckgen2->cksys2_clk_prot_idle_reg, 0xFFFFFFFF); + write32(&mtk_vlpsys->vlp_clk_prot_idle_reg, 0xFFFFFFFF); + + setbits32(&mtk_peri->vdnr_dcm_top_peri_par_bus_u_peri_par_bus_ctrl, + BIT(14) | BIT(11) | BIT(8) | BIT(5)); + + setbits32(&mtk_usb->vdnr_dcm_top_usb_bus_u_usb_bus_ctrl, BIT(10) | BIT(7) | BIT(4)); + + write32(&mtk_topckgen->clk_cfg[0].clr, 0x7); + write32(&mtk_topckgen->clk_cfg[0].set, 0x5); + write32(&mtk_topckgen->clk_cfg_update[0], 0x1); + + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[2], 0x7FFF); + + for (i = 0; i < ARRAY_SIZE(cksys2_mux_sels); i++) + pll_mux_set_sel(&cksys2_muxes[cksys2_mux_sels[i].id], cksys2_mux_sels[i].sel); + + write32(&mtk_topckgen2->cksys2_clk_cfg_update, 0x7FFFFFF); + + for (i = 0; i < ARRAY_SIZE(vlp_mux_sels); i++) + pll_mux_set_sel(&vlp_muxes[vlp_mux_sels[i].id], vlp_mux_sels[i].sel); + + write32(&mtk_vlpsys->vlp_clk_cfg_update[0], 0x7FFFFFFF); + write32(&mtk_vlpsys->vlp_clk_cfg_update[1], 0x3FFF); + + mt_dump_cpu_freq(); + mt_dump_gpu_freq(); + + write32(&mtk_apifrbus->apifrbus_ao_mem_reg_module_cg.clr, 0x10); + + write32(&mtk_pericfg->pericfg_ao_peri_cg_0_set, 0x40000); + write32(&mtk_pericfg->pericfg_ao_peri_cg_1_clr, 0x01FFFA44); + write32(&mtk_pericfg->pericfg_ao_peri_cg_1_set, 0x00000002); + write32(&mtk_pericfg->pericfg_ao_peri_cg_2_clr, 0x1C0000); + + setbits32(&mtk_ssr->ssr_top_ssr_top_clk_cfg[0], BIT(24) | BIT(16) | BIT(8) | BIT(0)); + setbits32(&mtk_ssr->ssr_top_ssr_top_clk_cfg[1], BIT(24)); +} + +void mt_pll_set_tvd_pll1_freq(u32 freq) +{ + const struct pll *pll = &plls[CLK_APMIXED2_TVDPLL3]; + + clrbits32(pll->reg, MT8196_PLL_EN); + pll_set_rate(pll, freq); + setbits32(pll->reg, MT8196_PLL_EN); + + udelay(PLL_EN_DELAY); +} + +void mt_pll_edp_mux_set_sel(u32 sel) +{ + pll_mux_set_sel(&cksys2_muxes[CLK_CK2_DVO_SEL], sel); +} + +void mt_pll_post_init(void) +{ + /* fenc setup */ + write32(&mtk_topckgen->clk_prot_idle_all_reg[0], 0); + write32(&mtk_topckgen->clk_prot_idle_all_reg[1], 0); + write32(&mtk_topckgen->clk_prot_idle_all_reg[2], 0); + write32(&mtk_topckgen->clk_prot_idle_all_inv_reg[0], 0); + write32(&mtk_topckgen->clk_prot_idle_all_inv_reg[1], 0); + write32(&mtk_topckgen->clk_prot_idle_all_inv_reg[2], 0); + write32(&mtk_topckgen->clk_prot_vote_ck_en_reg[0], 0xFFFFFFFF); + write32(&mtk_topckgen->clk_prot_vote_ck_en_reg[1], 0xFFFFFFFF); + write32(&mtk_topckgen->clk_prot_vote_ck_en_reg[2], 0xFFFFFFFF); + write32(&mtk_topckgen->clk_prot_spm_ck_en_reg, 0xFFFFFFFF); + write32(&mtk_topckgen2->cksys2_clk_prot_idle_all_reg, 0); + write32(&mtk_topckgen2->cksys2_clk_prot_idle_all_inv_reg, 0); + write32(&mtk_topckgen2->cksys2_clk_prot_vote_ck_en_reg, 0xFFFFFFFF); + write32(&mtk_topckgen2->cksys2_clk_prot_spm_ck_en_reg, 0xFFFFFFFF); + write32(&mtk_vlpsys->vlp_clk_prot_idle_all_reg[0], 0); + write32(&mtk_vlpsys->vlp_clk_prot_idle_all_reg[1], 0); + write32(&mtk_vlpsys->vlp_clk_prot_idle_all_inv_reg[0], 0); + write32(&mtk_vlpsys->vlp_clk_prot_idle_all_inv_reg[1], 0); + write32(&mtk_apmixed->fenc_protected_con, 0xFFFFFFFF); + write32(&mtk_apmixed2->gp2_fenc_protected_con, 0xFFF7FFFF); + write32(&mtk_vlpsys->vlp_fenc_protected_con, 0xFFFFFFFF); + write32(&mtk_apmixed->child_enable_mask_con, 0xFFFFFFFF); + write32(&mtk_apmixed2->gp2_child_enable_mask_con, 0xFFFFFFFF); + write32(&mtk_vlpsys->vlp_child_enable_mask_con, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_fenc_bypass_reg[0], 0); + write32(&mtk_topckgen->clk_fenc_bypass_reg[1], 0); + write32(&mtk_topckgen->clk_fenc_bypass_reg[2], 0); + write32(&mtk_topckgen2->cksys2_clk_fenc_bypass_reg, 0); + write32(&mtk_vlpsys->vlp_clk_fenc_bypass_reg[0], 0); + write32(&mtk_vlpsys->vlp_clk_fenc_bypass_reg[1], 0); + write32(&mtk_apmixed->fenc_bypass_con, 0); + write32(&mtk_apmixed2->gp2_fenc_bypass_con, 0); + write32(&mtk_vlpsys->vlp_fenc_bypass_con, 0); + write32(&mtk_apmixed->pllen_all_clr, 0xFFFFFFFF); + write32(&mtk_apmixed2->gp2_pllen_all_clr, 0xFFFFFFFF); + write32(&mtk_vlpsys->vlp_pllen_apll_clr, 0x3); + + /* power down unused mux */ + write32(&mtk_topckgen->clk_cfg[3].set, 0x8080); + write32(&mtk_topckgen->clk_cfg[4].set, 0x80800000); + write32(&mtk_topckgen->clk_cfg[6].set, 0x8000); + write32(&mtk_topckgen->clk_cfg[9].set, 0x8080); + write32(&mtk_topckgen->clk_cfg[12].set, 0x80800000); + write32(&mtk_topckgen->clk_cfg[15].set, 0x8000); + write32(&mtk_topckgen->clk_cfg[16].set, 0x800000); + write32(&mtk_topckgen->clk_cfg[18].set, 0x80000000); + write32(&mtk_topckgen->clk_cfg[19].set, 0x80808000); + write32(&mtk_topckgen->clk_cfg[20].set, 0x80808080); + write32(&mtk_topckgen->clk_cfg[21].set, 0x80808080); + write32(&mtk_topckgen->clk_cfg[22].set, 0x80); + + write32(&mtk_vlpsys->vlp_clk_cfg[6].set, 0x80); + write32(&mtk_vlpsys->vlp_clk_cfg[10].set, 0x80800000); + write32(&mtk_vlpsys->vlp_clk_cfg[11].set, 0x80); + + write32(&mtk_topckgen2->cksys2_clk_cfg[0].set, 0x80808080); + write32(&mtk_topckgen2->cksys2_clk_cfg[1].set, 0x80808080); + write32(&mtk_topckgen2->cksys2_clk_cfg[2].set, 0x80808080); + write32(&mtk_topckgen2->cksys2_clk_cfg[3].set, 0x80808080); + write32(&mtk_topckgen2->cksys2_clk_cfg[4].set, 0x80808080); + write32(&mtk_topckgen2->cksys2_clk_cfg[5].set, 0x808080); + write32(&mtk_topckgen2->cksys2_clk_cfg[6].set, 0x80808080); + + vote_init(); + mmvote_init(); +} + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + const struct pll *pll = &mcusys_plls[CLK_CPLL_ARMPLL_LL]; + + clrbits32(&mtk_mcusys->cpu_plldiv0_cfg, GENMASK(10, 8)); + setbits32(&mtk_mcusys->cpu_plldiv0_cfg, BIT(10)); + + clrbits32(pll->reg, MT8196_PLL_EN); + pll_set_rate(pll, freq); + setbits32(pll->reg, MT8196_PLL_EN); + + clrsetbits32(&mtk_mcusys->cpu_plldiv0_cfg, GENMASK(10, 8), BIT(8)); + setbits32(&mtk_mcusys->cpu_plldiv0_cfg, BIT(10)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Gerrit-Change-Number: 84495 Gerrit-PatchSet: 29 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: [RFC] device/resource: IOINDEX_SUBTRACTIVE oddities
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Kyösti Mälkki. Yu-Ping Wu has posted comments on this change by Kyösti Mälkki. ( https://review.coreboot.org/c/coreboot/+/64972?usp=email ) Change subject: [RFC] device/resource: IOINDEX_SUBTRACTIVE oddities ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/64972/comment/272cedd1_ac7e94c0?us… : PS6, Line 179: res->size = conf->mmio_res_io.size; Despite of many unrelated changes, this patch mainly does two things: 1. Replace `res->limit` assignment with `res->size` 2. Add `IORESOURCE_FIXED` to `res->flags` Could you please explain the reason in the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/64972?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieff703ed39d69c8ef9edb2e8292ce82eb4e41351 Gerrit-Change-Number: 64972 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 07:35:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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