coreboot-gerrit November 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reduce stack usage by 18KiB
by Lean Sheng Tan (Code Review) 08 Nov '24

08 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84832?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Reduce stack usage by 18KiB ...................................................................... soc/intel/xeon_sp: Reduce stack usage by 18KiB Reduce stack usage of acpi_fill_srat_memory() by 18KiB. Directly write the SRAT table entries instead of using a temporary buffer on the stack. FIXES: Crash on ocp/tiogapass when writing SRAT table TEST: Still boots on intel/archercity_crb Change-Id: I91a6787ade8b465da7837b241c0aab00251f7de4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84832 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/uncore_acpi.c 2 files changed, 59 insertions(+), 66 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 0618147..0e93dc2 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -6,7 +6,6 @@ #include <acpi/acpi.h> #define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 -#define MAX_ACPI_MEMORY_AFFINITY_COUNT 256 /** Select C-state map set in config cstate_states diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 099b235..949c88b 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -74,90 +74,84 @@ return current; } -static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) +static void acpi_fill_srat_memory(int *cnt, acpi_srat_mem_t *current, + const struct SystemMemoryMapElement *e) { - const struct SystemMemoryMapHob *memory_map; - unsigned int mmap_index; + acpi_srat_mem_t srat; + uint64_t addr, size; - memory_map = get_system_memory_map(); - assert(memory_map); - printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); + addr = ((uint64_t)e->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); + size = ((uint64_t)e->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); - mmap_index = 0; - for (int e = 0; e < memory_map->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; - uint64_t addr = - (uint64_t)((uint64_t)mem_element->BaseAddress << - MEM_ADDR_64MB_SHIFT_BITS); - uint64_t size = - (uint64_t)((uint64_t)mem_element->ElementSize << - MEM_ADDR_64MB_SHIFT_BITS); + printk(BIOS_DEBUG, "SRAT: sysmemmap addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " + "ElementSize: 0x%x, type: %d, reserved: %d\n", addr, e->BaseAddress, + size, e->ElementSize, e->Type, is_memtype_reserved(e->Type)); - printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, type: %d, reserved: %d\n", - e, addr, mem_element->BaseAddress, size, - mem_element->ElementSize, mem_element->Type, - is_memtype_reserved(mem_element->Type)); + /* skip reserved memory region */ + if (is_memtype_reserved(e->Type)) + return; - assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); + /* skip all non processor attached memory regions */ + if (CONFIG(SOC_INTEL_HAS_CXL) && + (!is_memtype_processor_attached(e->Type))) + return; - /* skip reserved memory region */ - if (is_memtype_reserved(mem_element->Type)) - continue; - /* skip all non processor attached memory regions */ - if (CONFIG(SOC_INTEL_HAS_CXL) && - (!is_memtype_processor_attached(mem_element->Type))) - continue; + /* Prepare ACPI table entry */ + memset(&srat, 0, sizeof(acpi_srat_mem_t)); - /* skip if this address is already added */ - bool skip = false; - for (int idx = 0; idx < mmap_index; ++idx) { - uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + - srat_mem[idx].base_address_low; - if (addr == base_addr) { - skip = true; - break; - } + srat.type = 1; /* Memory affinity structure */ + srat.length = sizeof(acpi_srat_mem_t); + srat.base_address_low = (uint32_t)(addr & 0xffffffff); + srat.base_address_high = (uint32_t)(addr >> 32); + srat.length_low = (uint32_t)(size & 0xffffffff); + srat.length_high = (uint32_t)(size >> 32); + srat.proximity_domain = memory_to_pd(e); + srat.flags = ACPI_SRAT_MEMORY_ENABLED; + if (is_memtype_non_volatile(e->Type)) + srat.flags |= ACPI_SRAT_MEMORY_NONVOLATILE; + + /* skip if this address is already added */ + bool skip = false; + for (int i = 0; i < *cnt; i++) { + if ((srat.base_address_high == current[-i].base_address_high) && + (srat.base_address_low == current[-i].base_address_low)) { + skip = true; + break; } - if (skip) - continue; - - srat_mem[mmap_index].type = 1; /* Memory affinity structure */ - srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t)(addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t)(addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t)(size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t)(size >> 32); - srat_mem[mmap_index].proximity_domain = memory_to_pd(mem_element); - srat_mem[mmap_index].flags = ACPI_SRAT_MEMORY_ENABLED; - if (is_memtype_non_volatile(mem_element->Type)) - srat_mem[mmap_index].flags |= ACPI_SRAT_MEMORY_NONVOLATILE; - ++mmap_index; } - return mmap_index; + if (!skip) { + printk(BIOS_DEBUG, "SRAT: adding memory %d entry length: %d, addr: 0x%x%x, " + "length: 0x%x%x, proximity_domain: %d, flags: %x\n", + *cnt, srat.length, srat.base_address_high, srat.base_address_low, + srat.length_high, srat.length_low, srat.proximity_domain, srat.flags); + + memcpy(current, &srat, sizeof(acpi_srat_mem_t)); + (*cnt)++; + } } static unsigned long acpi_fill_srat(unsigned long current) { - acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; - unsigned int mem_count; + const struct SystemMemoryMapHob *memory_map; + acpi_srat_mem_t *acpi_srat; + int cnt = 0; + + memory_map = get_system_memory_map(); + assert(memory_map); + printk(BIOS_DEBUG, "SRAT: memory_map: %p\n", memory_map); /* create all subtables for processors */ current = acpi_create_srat_lapics(current); + acpi_srat = (acpi_srat_mem_t *)current; - memset(srat_mem, 0, sizeof(srat_mem)); - mem_count = get_srat_memory_entries(srat_mem); - for (int i = 0; i < mem_count; ++i) { - printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - i, srat_mem[i].length, - srat_mem[i].base_address_high, srat_mem[i].base_address_low, - srat_mem[i].length_high, srat_mem[i].length_low, - srat_mem[i].proximity_domain, srat_mem[i].flags); - memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); - current += srat_mem[i].length; + for (int i = 0; i < memory_map->numberEntries; ++i) { + const struct SystemMemoryMapElement *e = &memory_map->Element[i]; + acpi_fill_srat_memory(&cnt, &acpi_srat[cnt], e); } + printk(BIOS_DEBUG, "SRAT: Added %d memory entries\n", cnt); + + current = (unsigned long)&acpi_srat[cnt]; if (CONFIG(SOC_INTEL_HAS_CXL)) current = cxl_fill_srat(current); -- To view, visit https://review.coreboot.org/c/coreboot/+/84832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91a6787ade8b465da7837b241c0aab00251f7de4 Gerrit-Change-Number: 84832 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/common: sata: Opt out in sata_acpi_fill_ssdt() when not named
by Lean Sheng Tan (Code Review) 08 Nov '24

08 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84830?usp=email ) Change subject: soc/intel/common: sata: Opt out in sata_acpi_fill_ssdt() when not named ...................................................................... soc/intel/common: sata: Opt out in sata_acpi_fill_ssdt() when not named When soc_acpi_name() returns NULL do not create the AML code. This prevents errors on the OS side when it tries to parse the AML code and doesn't find a name string for the device: ACPI Warning: Invalid character(s) in name (0x44415F08), repaired: [*_AD] Change-Id: I72225a975663a1028283437cac3b9231b7c77ead Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84830 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 96b7390..ca61c68 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -10,12 +10,13 @@ static void sata_acpi_fill_ssdt(const struct device *dev) { const char *scope = acpi_device_scope(dev); + const char *name = soc_acpi_name(dev); - if (!scope) + if (!scope || !name) return; acpigen_write_scope(scope); - acpigen_write_device(soc_acpi_name(dev)); + acpigen_write_device(name); acpigen_write_ADR_pci_device(dev); acpigen_write_STA(acpi_device_status(dev)); acpigen_pop_len(); /* Device */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84830?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72225a975663a1028283437cac3b9231b7c77ead Gerrit-Change-Number: 84830 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Subrata Banik (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Bora Guvendik, Kapil Porwal, Li1 Feng, Pranava Y N, YH Lin. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/84998/comment/9d7bffb7_17a75e93?us… : PS3, Line 457: /* GPP_D05: NC */ : PAD_NC(GPP_D05, NONE), : /* GPP_D06: NC */ : PAD_NC(GPP_D06, NONE), : /* GPP_E05: NC */ : PAD_NC(GPP_E05, NONE), > > Can we keep these as default case in gpio.c itself and enable ISH GPIOs when ISH is enabled? > > Yes, we can do that, but it won't save anything. Instead, we have a good differentiation here that tells us which GPIOs we should care about when disaligning the ISH. > > Anyway, we are not adding these GPIOs in side GPIO.c that means no redundant programming. But based on your suggestion, it will cause redundant GPIO programming for same PAD if we add it in default inside GPIO.c and then override in fw_config.c isn't it. The current approach is avoiding that need. -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 07:33:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update SAF base address
by Subrata Banik (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Anil Kumar K, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/84863?usp=email ) Change subject: soc/intel/pantherlake: Update SAF base address ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14fa8cf06144f46369cc8cab6087c790280e9859 Gerrit-Change-Number: 84863 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 07:29:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/common: sata: Opt out in sata_acpi_fill_ssdt() when not named
by Subrata Banik (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Felix Held, Patrick Rudolph, Paul Menzel, Shuo Liu. Subrata Banik has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84830?usp=email ) Change subject: soc/intel/common: sata: Opt out in sata_acpi_fill_ssdt() when not named ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84830?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72225a975663a1028283437cac3b9231b7c77ead Gerrit-Change-Number: 84830 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 07:25:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller
by Lean Sheng Tan (Code Review) 08 Nov '24

08 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84842?usp=email ) Change subject: soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller ...................................................................... soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller In coreboot, LPC ACPI objects with its attached devices are usually provided by static DSDT. For Xeon-SP Gen6 LPC, its logical attached devices are created from dynamic SSDT (e.g. super IO). Create a simple SSDT for LPC in dynamic way as well to complete the device relationship chain. Fix below issues during Linux OS boot. The issue will block Windows OS boot as well. [ 22.986142] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.DI00.LPCB], AE_NOT_FOUND (20230628/dswload2-162) [ 22.986792] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) [ 22.987786] ACPI: Skipping parse of AML opcode: Scope (0x0010) Change-Id: I08543fc77f0f3e633b05889e921c5183e6e20d8e Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84842 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/xeon_sp/lpc_gen6.c 3 files changed, 37 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 0c4780b..bb28fc3 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -53,6 +53,9 @@ /* Init SoC Specific LPC features. Common definition will be weak and each soc will need to define the init. */ void lpc_soc_init(struct device *dev); +/* Create SoC specific SSDT, by default it does nothing so that static +DSDT could be used. */ +void lpc_soc_fill_ssdt(const struct device *dev); /* Fill up LPC IO resource structure inside SoC directory */ void pch_lpc_soc_fill_io_resources(struct device *dev); /* Set LPC BIOS Control BILD bit. */ diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index b05ee59..db06db9 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -16,6 +16,15 @@ /* no-op */ } +/* Create SoC specific SSDT */ +__weak void lpc_soc_fill_ssdt(const struct device *dev) +{ + /* + * no-op + * by default it does nothing so that static DSDT could be used + */ +} + /* Fill up LPC IO resource structure inside SoC directory */ __weak void pch_lpc_soc_fill_io_resources(struct device *dev) { @@ -134,6 +143,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = southbridge_write_acpi_tables, .acpi_name = lpc_acpi_name, + .acpi_fill_ssdt = lpc_soc_fill_ssdt, #endif .init = lpc_soc_init, .scan_bus = scan_static_bus, diff --git a/src/soc/intel/xeon_sp/lpc_gen6.c b/src/soc/intel/xeon_sp/lpc_gen6.c index d2aaec1..d4045a8 100644 --- a/src/soc/intel/xeon_sp/lpc_gen6.c +++ b/src/soc/intel/xeon_sp/lpc_gen6.c @@ -6,6 +6,30 @@ #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> + +void lpc_soc_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(name); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + acpigen_write_ADR_pci_device(dev); + + acpigen_write_device_end(); /* Device */ + acpigen_write_scope_end(); /* Scope */ +} + void lpc_soc_init(struct device *dev) { printk(BIOS_SPEW, "pch: lpc_init\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/84842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08543fc77f0f3e633b05889e921c5183e6e20d8e Gerrit-Change-Number: 84842 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Enable IRQ routing
by Lean Sheng Tan (Code Review) 08 Nov '24

08 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84328?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Enable IRQ routing ...................................................................... soc/intel/xeon_sp/gnr: Enable IRQ routing Enable IRQ routing per PCH IRQ usage convention and report domain _PRT. Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84328 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/gnr/Makefile.mk M src/soc/intel/xeon_sp/gnr/soc_acpi.c M src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/lpc_gen1.c A src/soc/intel/xeon_sp/lpc_gen6.c M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/spr/Makefile.mk 8 files changed, 39 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index fca7fe5..a24b50e 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -11,7 +11,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c -ramstage-y += ../chip_gen1.c +ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.mk b/src/soc/intel/xeon_sp/gnr/Makefile.mk index 1618301..9b07408 100644 --- a/src/soc/intel/xeon_sp/gnr/Makefile.mk +++ b/src/soc/intel/xeon_sp/gnr/Makefile.mk @@ -20,7 +20,7 @@ ramstage-y += soc_util.c ramstage-y += ramstage.c ramstage-y += soc_acpi.c -ramstage-y += ../chip_gen6.c +ramstage-y += ../chip_gen6.c ../lpc_gen6.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr/include CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c index 54c0cd2..76fabd2 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c @@ -84,6 +84,9 @@ acpigen_write_name("_PXM"); acpigen_write_integer(device_to_pd(domain)); + /* _PRT */ + acpigen_write_PRT_pre_routed(domain); + /* _OSC */ acpigen_write_OSC_pci_domain_fixed_caps(domain, get_granted_pcie_features(), diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 7b46564..bf1dedd 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -17,14 +17,6 @@ gen_io_dec[3] = config->gen4_dec; } -void lpc_soc_init(struct device *dev) -{ - printk(BIOS_SPEW, "pch: lpc_init\n"); - - /* FSP configures IOAPIC and PCHInterrupt Config */ - /* Should read back the ID to fill ACPI IOAPIC accordingly. */ -} - void pch_lpc_soc_fill_io_resources(struct device *dev) { } diff --git a/src/soc/intel/xeon_sp/lpc_gen1.c b/src/soc/intel/xeon_sp/lpc_gen1.c new file mode 100644 index 0000000..9a1c629 --- /dev/null +++ b/src/soc/intel/xeon_sp/lpc_gen1.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/lpc_lib.h> + +void lpc_soc_init(struct device *dev) +{ + printk(BIOS_SPEW, "pch: lpc_init\n"); + + /* FSP configures IOAPIC and PCHInterrupt Config */ + /* Should read back the ID to fill ACPI IOAPIC accordingly. */ +} diff --git a/src/soc/intel/xeon_sp/lpc_gen6.c b/src/soc/intel/xeon_sp/lpc_gen6.c new file mode 100644 index 0000000..d2aaec1 --- /dev/null +++ b/src/soc/intel/xeon_sp/lpc_gen6.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +void lpc_soc_init(struct device *dev) +{ + printk(BIOS_SPEW, "pch: lpc_init\n"); + + /* Program irq pin/line for PCI devices by PCH convention */ + pch_pirq_init(); + + /* Explicitly set polarity low for PIRQA to PIRQH */ + for (int i = 0; i < PIRQ_COUNT; i++) { + itss_set_irq_polarity(pcr_read8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + i), 1); + } +} diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk index 58d783a..456e932 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.mk +++ b/src/soc/intel/xeon_sp/skx/Makefile.mk @@ -16,7 +16,7 @@ ramstage-y += soc_acpi.c ramstage-y += chip.c -ramstage-y += ../chip_gen1.c +ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-y += soc_util.c ramstage-y += cpu.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 0c4f063..c5f9ece 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -15,7 +15,7 @@ ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c ramstage-y += crashlog.c ioat.c -ramstage-y += ../chip_gen1.c +ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr -- To view, visit https://review.coreboot.org/c/coreboot/+/84328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Gerrit-Change-Number: 84328 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 50: (1 comment) File src/soc/intel/snowridge/Kconfig: https://review.coreboot.org/c/coreboot/+/83321/comment/ce96e56a_f28c168b?us… : PS28, Line 270: config UNDEFINED_REGISTER : int : default 0 : help : To reuse intel common blocks, some undefined registers should be defined. > This is defined for reusing the common system agent code. […] I just pushed another patch that using a Kconfig item `HAVE_GPMR_REGISTERS` to select code, see https://review.coreboot.org/c/coreboot/+/85041 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 50 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 08 Nov 2024 07:20:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS General Purpose Memory Range registers may be not exposed on specific platforms, this patch adds a Kconfig item HAVE_GPMR_REGISTERS to select this feature. Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/gpmr/Kconfig M src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h 3 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85041/1 diff --git a/src/soc/intel/common/block/gpmr/Kconfig b/src/soc/intel/common/block/gpmr/Kconfig index 313b0cc..d1d3a73bb 100644 --- a/src/soc/intel/common/block/gpmr/Kconfig +++ b/src/soc/intel/common/block/gpmr/Kconfig @@ -8,10 +8,16 @@ if SOC_INTEL_COMMON_BLOCK_GPMR +config HAVE_GPMR_REGISTERS + bool + default y + help + Specify if the SoC has GPMR registers. + config USE_SOC_GPMR_DEFS bool default n help - Specify if the SoC have specific GPMR register definitions. + Specify if the SoC has specific GPMR register definitions. endif diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c index cef2e57..06ac5da 100644 --- a/src/soc/intel/common/block/gpmr/gpmr.c +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -33,6 +33,7 @@ return pcr_or32(PID_DMI, offset, ordata); } +#if CONFIG(HAVE_GPMR_REGISTERS) /* Check for available free gpmr */ static int get_available_gpmr(void) { @@ -85,3 +86,4 @@ return CB_SUCCESS; } +#endif diff --git a/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h index 98ee837..3cbfb69 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h +++ b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h @@ -18,6 +18,7 @@ #define GPMR_TCOBASE 0x2778 #define GPMR_TCOEN (1 << 1) +#if CONFIG(HAVE_GPMR_REGISTERS) #define MAX_GPMR_REGS 3 #define GPMR_OFFSET(x) (0x277c + (x) * 8) @@ -27,7 +28,8 @@ #define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) #define GPMR_EN BIT(31) +#endif /* CONFIG(HAVE_GPMR_REGISTERS) */ -#endif +#endif /* CONFIG(USE_SOC_GPMR_DEFS) */ #endif /* SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83322?usp=email to look at the new patch set (#54). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- A src/mainboard/intel/frost_creek/Kconfig A src/mainboard/intel/frost_creek/Kconfig.name A src/mainboard/intel/frost_creek/Makefile.mk A src/mainboard/intel/frost_creek/acpi_tables.c A src/mainboard/intel/frost_creek/board.fmd A src/mainboard/intel/frost_creek/board_id.c A src/mainboard/intel/frost_creek/board_id.h A src/mainboard/intel/frost_creek/board_info.txt A src/mainboard/intel/frost_creek/devicetree.cb A src/mainboard/intel/frost_creek/dsdt.asl A src/mainboard/intel/frost_creek/gpio.c A src/mainboard/intel/frost_creek/ramstage.c A src/mainboard/intel/frost_creek/ramstage.h A src/mainboard/intel/frost_creek/romstage.c A src/mainboard/intel/frost_creek/romstage.h 15 files changed, 614 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 54 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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coreboot-gerrit November 2024