coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2237 discussions

[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Máté Kukri (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Angel Pons, Felix Singer, Máté Kukri. Hello Angel Pons, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82053?usp=email to look at the new patch set (#17). Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) - Boots Linux 6.11 (Debian) - GRUB and SeaBIOS payloads work - SMSC SCH5553 SIO/EC + Serial port works + PWM fan control works - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/plugins/gitiles/deguard - Audio works - Currently limited to the Micro form factor, but others are very similar - HDA verbs and VBT by Leah Rowe - FIXME: USB port list Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- A src/mainboard/dell/optiplex_3050/Kconfig A src/mainboard/dell/optiplex_3050/Kconfig.name A src/mainboard/dell/optiplex_3050/Makefile.mk A src/mainboard/dell/optiplex_3050/acpi/ec.asl A src/mainboard/dell/optiplex_3050/acpi/superio.asl A src/mainboard/dell/optiplex_3050/board_info.txt A src/mainboard/dell/optiplex_3050/bootblock.c A src/mainboard/dell/optiplex_3050/cmos.default A src/mainboard/dell/optiplex_3050/cmos.layout A src/mainboard/dell/optiplex_3050/data.vbt A src/mainboard/dell/optiplex_3050/devicetree.cb A src/mainboard/dell/optiplex_3050/dsdt.asl A src/mainboard/dell/optiplex_3050/gma-mainboard.ads A src/mainboard/dell/optiplex_3050/hda_verb.c A src/mainboard/dell/optiplex_3050/include/early_gpio.h A src/mainboard/dell/optiplex_3050/include/gpio.h A src/mainboard/dell/optiplex_3050/ramstage.c A src/mainboard/dell/optiplex_3050/romstage.c A src/mainboard/dell/optiplex_3050/sch5555_ec.c A src/mainboard/dell/optiplex_3050/sch5555_ec.h 20 files changed, 1,331 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 17 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

1 0

[XL] Change in coreboot[main]: [WIP] OptiPlex 3050 Micro port
by Máté Kukri (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Angel Pons, Felix Singer, Máté Kukri. Hello Angel Pons, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82053?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [WIP] OptiPlex 3050 Micro port ...................................................................... [WIP] OptiPlex 3050 Micro port - Boots Linux - SMSC SCH5553 SIO/EC + Serial port works + PWM fan control works - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/plugins/gitiles/deguard - Audio works - Currently limited to the Micro form factor, but others are very similar - HDA verbs and VBT by Leah Rowe - FIXME: USB port list Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- A src/mainboard/dell/optiplex_3050/Kconfig A src/mainboard/dell/optiplex_3050/Kconfig.name A src/mainboard/dell/optiplex_3050/Makefile.mk A src/mainboard/dell/optiplex_3050/acpi/ec.asl A src/mainboard/dell/optiplex_3050/acpi/superio.asl A src/mainboard/dell/optiplex_3050/board_info.txt A src/mainboard/dell/optiplex_3050/bootblock.c A src/mainboard/dell/optiplex_3050/cmos.default A src/mainboard/dell/optiplex_3050/cmos.layout A src/mainboard/dell/optiplex_3050/data.vbt A src/mainboard/dell/optiplex_3050/devicetree.cb A src/mainboard/dell/optiplex_3050/dsdt.asl A src/mainboard/dell/optiplex_3050/gma-mainboard.ads A src/mainboard/dell/optiplex_3050/hda_verb.c A src/mainboard/dell/optiplex_3050/include/early_gpio.h A src/mainboard/dell/optiplex_3050/include/gpio.h A src/mainboard/dell/optiplex_3050/ramstage.c A src/mainboard/dell/optiplex_3050/romstage.c A src/mainboard/dell/optiplex_3050/sch5555_ec.c A src/mainboard/dell/optiplex_3050/sch5555_ec.h 20 files changed, 1,343 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 16 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

1 0

[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
by Felix Singer (Code Review) 05 Nov '24

05 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M920q (Coffee Lake) ...................................................................... mb/lenovo: Add ThinkCentre M920q (Coffee Lake) It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here. Works: - Serial adapter from daughter board (COM1 connector) - USB ports front and back - USB-C port (charging, data) - HDMI - Ethernet - SATA - NVMe - internal speaker - TPM2.0 - PCIe x8 port (x8 riser tested, x4 not) Does not work: - front audio jacks Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/m920q.md A src/mainboard/lenovo/m920q/Kconfig A src/mainboard/lenovo/m920q/Kconfig.name A src/mainboard/lenovo/m920q/Makefile.mk A src/mainboard/lenovo/m920q/acpi/ec.asl A src/mainboard/lenovo/m920q/acpi/mainboard.asl A src/mainboard/lenovo/m920q/acpi/superio.asl A src/mainboard/lenovo/m920q/board_info.txt A src/mainboard/lenovo/m920q/bootblock.c A src/mainboard/lenovo/m920q/cmos.default A src/mainboard/lenovo/m920q/cmos.layout A src/mainboard/lenovo/m920q/data.vbt A src/mainboard/lenovo/m920q/devicetree.cb A src/mainboard/lenovo/m920q/dsdt.asl A src/mainboard/lenovo/m920q/gma-mainboard.ads A src/mainboard/lenovo/m920q/gpio.c A src/mainboard/lenovo/m920q/hda_verb.c A src/mainboard/lenovo/m920q/include/mainboard/gpio.h A src/mainboard/lenovo/m920q/ramstage.c A src/mainboard/lenovo/m920q/romstage.c 21 files changed, 822 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3cae8f1..468e3c2 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -176,6 +176,7 @@ R60 <lenovo/r60.md> T4xx common <lenovo/t4xx_series.md> X2xx common <lenovo/x2xx_series.md> +M920 Tiny <lenovo/m920q.md> vboot <lenovo/vboot.md> ``` diff --git a/Documentation/mainboard/lenovo/m920q.md b/Documentation/mainboard/lenovo/m920q.md new file mode 100644 index 0000000..092aebf --- /dev/null +++ b/Documentation/mainboard/lenovo/m920q.md @@ -0,0 +1,102 @@ +# Lenovo M920 Tiny + +This page describes how to run coreboot on Lenovo M920 Tiny (M920q, M920x). + +## Technology + +```{eval-rst} ++------------+---------------------------------------------------------------+ +| CPU | Intel Core 8th Gen or 9th Gen (Coffee Lake (Refresh)) | ++------------+---------------------------------------------------------------+ +| DRAM | 2 SO-DIMM slots, DDR4-2400/2666 | ++------------+---------------------------------------------------------------+ +| Chipset | Intel Q370 | ++------------+---------------------------------------------------------------+ +| Super I/O | NCT6686D-L | ++------------+---------------------------------------------------------------+ +| TPM | Infineon SLB 9670VQ2.0 | ++------------+---------------------------------------------------------------+ +| Boot | USB, SATA (on-board SATA1 port, M.2 ports), NVMe | ++------------+---------------------------------------------------------------+ +| Power | 65-135 W power adapter | ++------------+---------------------------------------------------------------+ +``` + +More specifications on [Lenovo M920 Tiny specifications]. + +## Flashing coreboot + +```{eval-rst} ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | W25Q128JV + W25Q64JV | ++---------------------+--------------------------+ +| Size | 16 + 8 MiB | ++---------------------+--------------------------+ +| Package | SOIC-8 + SOIC-8 | ++---------------------+--------------------------+ +| Write protection | chipset PRR | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | after flashing coreboot | ++---------------------+--------------------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + + flashrom -p internal -N -w coreboot.rom --ifd -i bios + +Internal programming can be used after the coreboot has been flashed externally +for the first time. Internal programming when migrating from original UEFI +firmware **has not been tested**. + +### External programming + +The external access to flash chip is available through standard SOP-8 clip. The +voltage of both SPI chips is 3.3V. + +It is recommended to flash firmware without supplying power from power adapter. + +The resulting coreboot.rom file must be split into two binaries, one for each +flash chip: + + dd if=build/coreboot.rom of=build/coreboot_flash_1.rom bs=16M count=1 + dd if=build/coreboot.rom of=build/coreboot_flash_2.rom bs=8M skip=2 + +The flash chips are marked on the mainboard as BIOS1 and BIOS2 respectively. +They can be flashed with following commands: + + flashrom -p ch341a_spi -w build/coreboot_flash_1.rom + flashrom -p ch341a_spi -w build/coreboot_flash_2.rom -c "W25Q64JV-.Q" + +## Known issues + +- front audio jacks do not work + +## Working + +Tested with edk2 payload (mrchromebox) and Ubuntu 22.04 (Linux 6.2.0): + +- Serial adapter from daughter board (COM1 connector) +- USB 3.0 and 2.0 rear and front ports (edk2 and Linux 6.2.0) +- USB-C port (charging, data) +- Gigabit Ethernet +- SATA +- internal speaker +- TPM2.0 +- WiFi slot +- HDMI +- NVMe +- PCIe x8 port + - PCIe x8 tested using BA7H70 Rev 1.2 riser and Intel X540-T2 10G dual 10GbE card + - another riser with PCIe x4 connector remains untested - please modify this + page if you do test it! + +[flashrom]: https://flashrom.org/Flashrom +[Lenovo M920 Tiny specifications]: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M920_Tiny/… diff --git a/src/mainboard/lenovo/m920q/Kconfig b/src/mainboard/lenovo/m920q/Kconfig new file mode 100644 index 0000000..a83b477 --- /dev/null +++ b/src/mainboard/lenovo/m920q/Kconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_LENOVO_M920Q + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_24576 + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SUPERIO_NUVOTON_NCT6687D + +config MAINBOARD_DIR + default "lenovo/m920q" + +config MAINBOARD_PART_NUMBER + default "ThinkCentre M920 Tiny" + +config CBFS_SIZE + default 0x900000 + +endif diff --git a/src/mainboard/lenovo/m920q/Kconfig.name b/src/mainboard/lenovo/m920q/Kconfig.name new file mode 100644 index 0000000..ccdd21a --- /dev/null +++ b/src/mainboard/lenovo/m920q/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LENOVO_M920Q + bool "ThinkCentre M920 Tiny" diff --git a/src/mainboard/lenovo/m920q/Makefile.mk b/src/mainboard/lenovo/m920q/Makefile.mk new file mode 100644 index 0000000..4be8345 --- /dev/null +++ b/src/mainboard/lenovo/m920q/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/m920q/acpi/ec.asl b/src/mainboard/lenovo/m920q/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/m920q/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/m920q/acpi/mainboard.asl b/src/mainboard/lenovo/m920q/acpi/mainboard.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/m920q/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/m920q/acpi/superio.asl b/src/mainboard/lenovo/m920q/acpi/superio.asl new file mode 100644 index 0000000..13623c5 --- /dev/null +++ b/src/mainboard/lenovo/m920q/acpi/superio.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6687D_SHOW_SP1 +#define NCT6687D_SHOW_EC + +#include <superio/nuvoton/nct6687d/acpi/superio.asl> diff --git a/src/mainboard/lenovo/m920q/board_info.txt b/src/mainboard/lenovo/m920q/board_info.txt new file mode 100644 index 0000000..02e3e32 --- /dev/null +++ b/src/mainboard/lenovo/m920q/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://psref.lenovo.com/Product/ThinkCentre_M920_Tiny +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2021 diff --git a/src/mainboard/lenovo/m920q/bootblock.c b/src/mainboard/lenovo/m920q/bootblock.c new file mode 100644 index 0000000..7839cf7 --- /dev/null +++ b/src/mainboard/lenovo/m920q/bootblock.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <mainboard/gpio.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6687D_SP2) +#define POWER_DEV PNP_DEV(0x2e, NCT6687D_SLEEP_PWR) + +void bootblock_mainboard_early_init(void) +{ + /* Replicate vendor settings for multi-function pins in global config LDN */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x13, 0xff); + pnp_write_config(SERIAL_DEV, 0x14, 0xff); + + /* Below are multi-pin function */ + pnp_write_config(SERIAL_DEV, 0x1b, 0xf8); + pnp_write_config(SERIAL_DEV, 0x1f, 0xf0); + pnp_write_config(SERIAL_DEV, 0x20, 0xd4); + pnp_write_config(SERIAL_DEV, 0x21, 0x41); + pnp_write_config(SERIAL_DEV, 0x22, 0xbc); + pnp_write_config(SERIAL_DEV, 0x23, 0xff); + pnp_write_config(SERIAL_DEV, 0x24, 0x07); + pnp_write_config(SERIAL_DEV, 0x25, 0xff); + pnp_write_config(SERIAL_DEV, 0x26, 0x80); + pnp_write_config(SERIAL_DEV, 0x28, 0x08); + pnp_write_config(SERIAL_DEV, 0x29, 0x95); + pnp_write_config(SERIAL_DEV, 0x2a, 0xcf); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x18); + + nuvoton_pnp_exit_conf_state(POWER_DEV); + + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/lenovo/m920q/cmos.default b/src/mainboard/lenovo/m920q/cmos.default new file mode 100644 index 0000000..f3330e5 --- /dev/null +++ b/src/mainboard/lenovo/m920q/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable diff --git a/src/mainboard/lenovo/m920q/cmos.layout b/src/mainboard/lenovo/m920q/cmos.layout new file mode 100644 index 0000000..4dea5d2 --- /dev/null +++ b/src/mainboard/lenovo/m920q/cmos.layout @@ -0,0 +1,59 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Disable +2 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/m920q/data.vbt b/src/mainboard/lenovo/m920q/data.vbt new file mode 100644 index 0000000..38acf19 --- /dev/null +++ b/src/mainboard/lenovo/m920q/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/m920q/devicetree.cb b/src/mainboard/lenovo/m920q/devicetree.cb new file mode 100644 index 0000000..61fa868 --- /dev/null +++ b/src/mainboard/lenovo/m920q/devicetree.cb @@ -0,0 +1,142 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/cannonlake + register "power_limits_config" = "{ + .tdp_pl2_override = 65, + }" + + # Unmap unused CLKREQ lines, otherwise CLKSRC #0 won't work + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[7]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[8]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[9]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[11]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[12]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[13]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[14]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[15]" = "PCIE_CLK_NOTUSED" + + device domain 0 on + subsystemid 0x17aa 0x3136 inherit + # Slot JP3 + device ref peg0 on + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + end + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), // Internal USB header + [1] = USB2_PORT_TYPE_C(OC1), // Front port (charger) + [3] = USB2_PORT_TYPE_C(OC2), // Front Type C port + [4] = USB2_PORT_MID(OC4), // Rear USB 3.1 port 1 + [5] = USB2_PORT_MID(OC6), // Rear USB 3.1 port 2 + [6] = USB2_PORT_MID(OC3), // Rear USB 3.0 port 1 + [7] = USB2_PORT_MID(OC5), // Rear USB 3.0 port 2 + [13] = USB2_PORT_SHORT(OC_SKIP), // M.2 2230 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), // Front port (charger) + [1] = USB3_PORT_DEFAULT(OC2), // Front Type C port + [2] = USB3_PORT_DEFAULT(OC4), // Rear USB 3.1 port 1 + [3] = USB3_PORT_DEFAULT(OC6), // Rear USB 3.2 port 2 + [4] = USB3_PORT_DEFAULT(OC3), // Rear USB 3.0 port 1 + [5] = USB3_PORT_DEFAULT(OC5), // Rear USB 3.0 port 2 + [6] = USB3_PORT_DEFAULT(OC0), // Internal USB header + }" + end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end + device ref heci1 on end + device ref heci3 on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, // on-board SATA1 + [4] = 1, // M.2 SATA on M920x + }" + end + + device ref pcie_rp6 on # WLAN + register "PcieRpEnable[5]" = "1" + register "PcieRpSlotImplemented[5]" = "1" + register "PcieClkSrcUsage[3]" = "5" + register "PcieClkSrcClkReq[3]" = "3" + end + + device ref pcie_rp9 on # PCIe x4 + register "PcieRpEnable[8]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieClkSrcUsage[2]" = "8" + register "PcieClkSrcClkReq[2]" = "2" + end + + device ref pcie_rp17 on # M.2 SSD #2 + register "PcieRpEnable[16]" = "1" + register "PcieRpSlotImplemented[16]" = "1" + register "PcieClkSrcUsage[10]" = "16" + register "PcieClkSrcClkReq[10]" = "10" + end + + device ref pcie_rp21 on # M.2 SSD #1 + register "PcieRpEnable[20]" = "1" + register "PcieRpSlotImplemented[20]" = "1" + register "PcieClkSrcUsage[4]" = "20" + register "PcieClkSrcClkReq[4]" = "4" + end + + device ref lpc_espi on + chip superio/nuvoton/nct6687d + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 off end # UARTA (USB debug port?) + device pnp 2e.3 on # UARTB - COM1 header - optional sub-board + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0xf0 = 0 + irq 0xf1 = 0 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO0-7 + device pnp 2e.8 off end # P80 UART + device pnp 2e.9 off end # GPIO8-9, GPIO1-8 AF + device pnp 2e.a on # ACPI + io 0x60 = 0x00 + irq 0x70 = 0x40 + end + device pnp 2e.b on # EC + io 0x60 = 0xa20 + irq 0x70 = 0 + end + device pnp 2e.c off end # RTC + device pnp 2e.d off end # Deep Sleep + device pnp 2e.e on # TACH/PWM assignment + irq 0xe4 = 0x10 + irq 0xe5 = 0x09 + end + device pnp 2e.f off end # Function register + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref hda on + register "PchHdaAudioLinkHda" = "1" + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on + register "PcieClkSrcUsage[6]" = "PCIE_CLK_LAN" + register "PcieClkSrcClkReq[6]" = "6" + end + end +end diff --git a/src/mainboard/lenovo/m920q/dsdt.asl b/src/mainboard/lenovo/m920q/dsdt.asl new file mode 100644 index 0000000..09825c3 --- /dev/null +++ b/src/mainboard/lenovo/m920q/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/m920q/gma-mainboard.ads b/src/mainboard/lenovo/m920q/gma-mainboard.ads new file mode 100644 index 0000000..fa35825 --- /dev/null +++ b/src/mainboard/lenovo/m920q/gma-mainboard.ads @@ -0,0 +1,20 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/m920q/gpio.c b/src/mainboard/lenovo/m920q/gpio.c new file mode 100644 index 0000000..339d819 --- /dev/null +++ b/src/mainboard/lenovo/m920q/gpio.c @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_NC(GPP_A0, NONE), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF3), /* ESPI_CS0# */ + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF3), /* ESPI_CLK */ + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), /* ESPI_RESET# */ + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_NC(GPP_B0, NONE), + PAD_NC(GPP_B1, NONE), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPO(GPP_B22, 0, DEEP), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), /* MODEM_CLKREQ */ + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), /* GP_BSSB_DI */ + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */ + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), /* DMIC_DATA1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */ + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ + PAD_CFG_GPI_TRIG_OWN(GPD1, UP_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PRWBTN# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 0, RSMRST), + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* LANPHYPC */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_NC(GPP_K3, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K8, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K9, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_K11, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, LEVEL, INVERT), + PAD_NC(GPP_K13, NONE), + PAD_NC(GPP_K14, NONE), + PAD_NC(GPP_K15, NONE), + PAD_CFG_GPO(GPP_K16, 0, PLTRST), + PAD_NC(GPP_K17, NONE), + PAD_NC(GPP_K18, NONE), + PAD_NC(GPP_K19, NONE), + PAD_CFG_NF(GPP_K20, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_K22, 1, PLTRST), + PAD_NC(GPP_K23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), /* SRCCLKREQ6# */ + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* SRCCLKREQ10# */ + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_CFG_GPO(GPP_H12, 0, DEEP), + PAD_NC(GPP_H13, NONE), + PAD_CFG_GPO(GPP_H14, 0, PLTRST), + PAD_NC(GPP_H15, NONE), + PAD_CFG_GPO(GPP_H16, 0, PLTRST), + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + PAD_CFG_GPO(GPP_H18, 0, PLTRST), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ + PAD_CFG_GPI_SCI(GPP_E2, NONE, PLTRST, LEVEL, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPO(GPP_E6, 0, PLTRST), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATALED# */ + PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1), /* USB2_OC0# */ + PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1), /* USB2_OC1# */ + PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1), /* USB2_OC2# */ + PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), /* USB2_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ + PAD_CFG_NF(GPP_F1, NONE, PLTRST, NF1), /* SATAXPCIE4 */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2), /* PS_ON# */ + PAD_CFG_NF(GPP_F15, NONE, PLTRST, NF1), /* USB2_OC4# */ + PAD_CFG_NF(GPP_F16, NONE, PLTRST, NF1), /* USB2_OC5# */ + PAD_CFG_NF(GPP_F17, NONE, PLTRST, NF1), /* USB2_OC6# */ + PAD_NC(GPP_F18, NONE), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* eDP_VDDEN */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* eDP_BKLTEN */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* eDP_BKLTCTL */ + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, PLTRST), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DDPB_HPD0 */ + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DDPB_HPD1 */ + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), /* DDPB_HPD2 */ + PAD_NC(GPP_I3, NONE), + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), /* EDP_HPD */ + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* DDPD_CTRLCLK */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* DDPD_CTRLDATA */ + PAD_NC(GPP_I11, NONE), + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + + /* ------- GPIO Group GPP_J ------- */ + PAD_NC(GPP_J0, NONE), + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), /* CPU_C10_GATE# */ + PAD_NC(GPP_J2, NONE), + PAD_NC(GPP_J3, NONE), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_NC(GPP_J8, NONE), + PAD_CFG_GPO(GPP_J9, 0, DEEP), + PAD_NC(GPP_J10, NONE), + PAD_CFG_NF(GPP_J11, DN_20K, DEEP, NF1), /* A4WP_PRESENT */ +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/lenovo/m920q/hda_verb.c b/src/mainboard/lenovo/m920q/hda_verb.c new file mode 100644 index 0000000..6e6d679 --- /dev/null +++ b/src/mainboard/lenovo/m920q/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0235, /* Codec Vendor / Device ID: Realtek ALC233 */ + 0x17aa3136, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa3136), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, 0x02a11020), + AZALIA_PIN_CFG(0, 0x1a, 0x02a11030), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x40400001), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, 0x0221101f), + + 0x8086280b, /* Codec Vendor / Device ID: Intel Kabylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/m920q/include/mainboard/gpio.h b/src/mainboard/lenovo/m920q/include/mainboard/gpio.h new file mode 100644 index 0000000..ef2a21c --- /dev/null +++ b/src/mainboard/lenovo/m920q/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/lenovo/m920q/ramstage.c b/src/mainboard/lenovo/m920q/ramstage.c new file mode 100644 index 0000000..e94ca02 --- /dev/null +++ b/src/mainboard/lenovo/m920q/ramstage.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> +#include <soc/ramstage.h> + +static void mainboard_enable(struct device *dev) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/m920q/romstage.c b/src/mainboard/lenovo/m920q/romstage.c new file mode 100644 index 0000000..99f0f68 --- /dev/null +++ b/src/mainboard/lenovo/m920q/romstage.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg baseboard_mem_cfg = { + /* Access memory info through SMBUS. */ + .spd[0] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa0}}, + .spd[1] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa4}}, + + /* Rcomp resistors on CFL-S are located on the CPU itself */ + .rcomp_resistor = {121, 75, 100}, + + /* Rcomp target values for CFL-S, DDR4 and 1 DIMM per channel */ + .rcomp_targets = {50, 26, 20, 20, 26}, + + /* Baseboard is an interleaved design */ + .dq_pins_interleaved = 1, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &baseboard_mem_cfg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Gerrit-Change-Number: 80609 Gerrit-PatchSet: 19 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Update power limits config
by Jamie Ryu (Code Review) 05 Nov '24

05 Nov '24

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85006?usp=email ) Change subject: soc/intel/pantherlake: Update power limits config ...................................................................... soc/intel/pantherlake: Update power limits config This updates power_limits_config for Panther Lake U and H. Source: Intel PTL PDG 813278 Intel PTL FSP Power limit profiles table BUG=b:357011633 TEST=Build fatcat and boot with Panther Lake SoC and RVP. Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85006/1 diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 59aad4f..b59ce5e 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -65,9 +65,9 @@ } cpuid_to_ptl[] = { { PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W }, { PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W }, - { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_3_CORE, TDP_45W }, - { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_1_CORE, TDP_25W }, - { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_1_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W }, }; /* Types of display ports */ diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb index 4f6c8e04..f4c1b26 100644 --- a/src/soc/intel/pantherlake/chipset.cb +++ b/src/soc/intel/pantherlake/chipset.cb @@ -4,20 +4,20 @@ register "power_limits_config[PTL_U_1_CORE]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 54, - .tdp_pl4 = 142, + .tdp_pl2_override = 55, + .tdp_pl4 = 152, }" register "power_limits_config[PTL_H_1_CORE]" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 64, - .tdp_pl4 = 154, + .tdp_pl2_override = 95, + .tdp_pl4 = 239, }" register "power_limits_config[PTL_H_2_CORE]" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 80, - .tdp_pl4 = 240, + .tdp_pl2_override = 64, + .tdp_pl4 = 154, }" # NOTE: if any variant wants to override this value, use the same format -- To view, visit https://review.coreboot.org/c/coreboot/+/85006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Gerrit-Change-Number: 85006 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com>

1 0

[XS] Change in coreboot[main]: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info
by Caveh Jalali (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Forest Mittelberg, Karthik Ramasubramanian, Nick Vaccaro, Nick Vaccaro, Subrata Banik. Caveh Jalali has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85005?usp=email ) Change subject: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Gerrit-Change-Number: 85005 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 20:15:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: mb/google/brox: Hint romstage init about upcoming reset
by Karthik Ramasubramanian (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Bob Moragues, Paul Menzel, Shyam Sundar Radjacoumar, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84937?usp=email ) Change subject: mb/google/brox: Hint romstage init about upcoming reset ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/brox/variants/baseboard/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/84937/comment/637e8267_3087d657?us… : PS5, Line 24: ret = google_chromeec_get_num_pd_ports(&num_ports); : if (ret < 0 || !num_ports) { : printk(BIOS_INFO, "%s: Cannot resolve # of USB PD ports\n", __func__); : return mismatch; : } > I'm wondering if we need to call this API at all. […] Done https://review.coreboot.org/c/coreboot/+/84937/comment/57cb9645_7a94886d?us… : PS5, Line 30: google_chromeec_get_pd_chip_infoi > is this a typo ? […] Acknowledged. Fixed the typo in API as well as here. Thanks for catching that. -- To view, visit https://review.coreboot.org/c/coreboot/+/84937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Gerrit-Change-Number: 84937 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Nov 2024 19:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[XS] Change in coreboot[main]: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info
by Karthik Ramasubramanian (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Caveh Jalali, Forest Mittelberg. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85005?usp=email ) Change subject: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info ...................................................................... ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info An unintended suffix got added in google_chromeec_get_pd_chip_info. Fix the typo by removing that suffix. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85005/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 38f7e87..af5c235 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1170,7 +1170,7 @@ return 0; } -int google_chromeec_get_pd_chip_infoi(int port, int renew, +int google_chromeec_get_pd_chip_info(int port, int renew, struct ec_response_pd_chip_info *r) { const struct ec_params_pd_chip_info p = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 5a65f2d..31c7671 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -346,7 +346,7 @@ * * @return 0 if ok, -1 on error */ -int google_chromeec_get_pd_chip_infoi(int port, int renew, +int google_chromeec_get_pd_chip_info(int port, int renew, struct ec_response_pd_chip_info *r); /* Structure representing the capabilities of a USB-PD port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Gerrit-Change-Number: 85005 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com>

1 0

[M] Change in coreboot[main]: mb/google/brox: Hint romstage init about upcoming reset
by Karthik Ramasubramanian (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Bob Moragues, Karthik Ramasubramanian, Paul Menzel, Shyam Sundar Radjacoumar. Hello Bob Moragues, Paul Menzel, Shyam Sundar Radjacoumar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84937?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Hint romstage init about upcoming reset ...................................................................... mb/google/brox: Hint romstage init about upcoming reset Add support for the mainboard to check for any potential firmware component update and hence the assosicated reset. This indication can be used to avoid any redundant resets during the boot flow. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are provided correctly and 2 redundant resets are filtered out. Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk A src/mainboard/google/brox/variants/baseboard/brox/romstage.c M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brox/variants/brox/Makefile.mk M src/mainboard/google/brox/variants/brox/variant.c M src/mainboard/google/brox/variants/jubilant/Makefile.mk M src/mainboard/google/brox/variants/jubilant/variant.c M src/mainboard/google/brox/variants/lotso/Makefile.mk M src/mainboard/google/brox/variants/lotso/variant.c 9 files changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/84937/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Gerrit-Change-Number: 84937 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

1 0

[L] Change in coreboot[main]: Add UPL FDT handoff
by Julius Werner (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, Jakub Czapiga, Jérémy Compostella, Maximilian Brune, Philipp Hug, Simon Glass, ron minnich. Julius Werner has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/76591?usp=email ) Change subject: Add UPL FDT handoff ...................................................................... Patch Set 24: (1 comment) File src/drivers/uart/pl011.c: https://review.coreboot.org/c/coreboot/+/76591/comment/fb7a6f35_8e1e04ec?us… : PS24, Line 96: uint8_t Are you sure this shouldn't be uint32_t? -- To view, visit https://review.coreboot.org/c/coreboot/+/76591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae Gerrit-Change-Number: 76591 Gerrit-PatchSet: 24 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 19:11:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
by Karthik Ramasubramanian (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Eric Lai, Subrata Banik, hualin wei. Karthik Ramasubramanian has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email ) Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Gerrit-Change-Number: 84951 Gerrit-PatchSet: 4 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 17:41:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2024