coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: mb/google/brox: Reduce PL4 only for battery disconnected scenario
by Karthik Ramasubramanian (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Sowmya Aralguppe. Karthik Ramasubramanian has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85002?usp=email ) Change subject: mb/google/brox: Reduce PL4 only for battery disconnected scenario ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59a1028ce9cd3a6cf98f865d9c085a64f391f201 Gerrit-Change-Number: 85002 Gerrit-PatchSet: 2 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 17:03:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Subrata Banik (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Bora Guvendik, Li1 Feng, Pranava Y N, YH Lin. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84998/comment/8f800de9_85cd7710?us… : PS1, Line 236: chip drivers/intel/ish : register "firmware_name" = ""ish_fw.bin"" : register "add_acpi_dma_property" = "true" > Li Feng was telling me that firmware_name property is not needed anymore since kernel has hard coded the name. > > Li can you please confirm? that is good piece of information, what I did is copied the ISH configuration from Trulo. -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 16:14:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com>

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[XS] Change in coreboot[main]: drivers/spi/spi_flash: make 'do_spi_flash_cmd' available to other files
by Felix Held (Code Review) 05 Nov '24

05 Nov '24

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84789?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/spi/spi_flash: make 'do_spi_flash_cmd' available to other files ...................................................................... Patch Set 4: (1 comment) Patchset: PS1: > or would it be better to add a new function that can be called from other compilation units in the s […] discussed this one with Matt and we both think that introducing 'spi_flash_cmd_multi' would be the better way; will update the patch -- To view, visit https://review.coreboot.org/c/coreboot/+/84789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e Gerrit-Change-Number: 84789 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2024 16:14:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Update ext_vr for board version > 0xb
by Karthik Ramasubramanian (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Paul Menzel, Robert Chen, Shou-Chieh Hsu. Karthik Ramasubramanian has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/84953?usp=email ) Change subject: mb/google/dedede/var/drawcia: Update ext_vr for board version > 0xb ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Gerrit-Change-Number: 84953 Gerrit-PatchSet: 17 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 16:06:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Bora Guvendik (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Li1 Feng, Pranava Y N, Subrata Banik, YH Lin. Bora Guvendik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84998/comment/922c2a4a_6740bb4c?us… : PS1, Line 236: chip drivers/intel/ish : register "firmware_name" = ""ish_fw.bin"" : register "add_acpi_dma_property" = "true" Li Feng was telling me that firmware_name property is not needed anymore since kernel has hard coded the name. Li can you please confirm? -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 16:05:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/common/psp_smi_flash: refactor SPI controller busy check
by Felix Held (Code Review) 05 Nov '24

05 Nov '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84920?usp=email ) Change subject: soc/amd/common/psp_smi_flash: refactor SPI controller busy check ...................................................................... soc/amd/common/psp_smi_flash: refactor SPI controller busy check Since the functions that call 'spi_controller_available' end up checking if the SPI controller is busy, refactor the function into 'spi_controller_busy' to simplify the logic on the caller's side. Also move printing of the notice that the SPI controller is busy to 'spi_controller_busy' to not have that duplicated in caller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibc21ab6eacf07c4adffdb4658142c2f9dfcbf2a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84920 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/psp/psp_smi_flash.c 1 file changed, 11 insertions(+), 10 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c index ca59553..abddcdf 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash.c @@ -92,9 +92,14 @@ return MBOX_PSP_SUCCESS; } -static bool spi_controller_available(void) +static bool spi_controller_busy(void) { - return !(spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED); + const bool busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED); + + if (busy) + printk(BIOS_NOTICE, "PSP: SPI controller busy\n"); + + return busy; } enum mbox_p2c_status psp_smi_spi_get_info(struct mbox_default_buffer *buffer) @@ -113,8 +118,7 @@ if (!is_valid_psp_spi_info(cmd_buf)) return MBOX_PSP_COMMAND_PROCESS_ERROR; - if (!spi_controller_available()) { - printk(BIOS_NOTICE, "PSP: SPI controller busy\n"); + if (spi_controller_busy()) { return MBOX_PSP_SPI_BUSY; } @@ -156,8 +160,7 @@ if (!is_valid_psp_spi_read_write(cmd_buf)) return MBOX_PSP_COMMAND_PROCESS_ERROR; - if (!spi_controller_available()) { - printk(BIOS_NOTICE, "PSP: SPI controller busy\n"); + if (spi_controller_busy()) { return MBOX_PSP_SPI_BUSY; } @@ -205,8 +208,7 @@ if (!is_valid_psp_spi_read_write(cmd_buf)) return MBOX_PSP_COMMAND_PROCESS_ERROR; - if (!spi_controller_available()) { - printk(BIOS_NOTICE, "PSP: SPI controller busy\n"); + if (spi_controller_busy()) { return MBOX_PSP_SPI_BUSY; } @@ -253,8 +255,7 @@ if (!is_valid_psp_spi_erase(cmd_buf)) return MBOX_PSP_COMMAND_PROCESS_ERROR; - if (!spi_controller_available()) { - printk(BIOS_NOTICE, "PSP: SPI controller busy\n"); + if (spi_controller_busy()) { return MBOX_PSP_SPI_BUSY; } -- To view, visit https://review.coreboot.org/c/coreboot/+/84920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc21ab6eacf07c4adffdb4658142c2f9dfcbf2a1 Gerrit-Change-Number: 84920 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/common/psp_smi_flash: factor out get_flash_device
by Felix Held (Code Review) 05 Nov '24

05 Nov '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84905?usp=email ) Change subject: soc/amd/common/psp_smi_flash: factor out get_flash_device ...................................................................... soc/amd/common/psp_smi_flash: factor out get_flash_device Since the RPMC-related functions will only need the spi_flash struct, but not the region_device struct of the store region corresponding to the 'target_nv_id', factor out 'get_flash_device' from 'find_psp_spi_flash_device_region'. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84905 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ana Carolina Cabral --- M src/soc/amd/common/block/psp/psp_smi_flash.c 1 file changed, 11 insertions(+), 3 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Ana Carolina Cabral: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c index d78db48..ca59553 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash.c @@ -66,9 +66,7 @@ return rdev_chain(rstore, rdev, 0, region_device_sz(rdev)); } -static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_id, - struct region_device *store, - const struct spi_flash **flash) +static enum mbox_p2c_status get_flash_device(const struct spi_flash **flash) { *flash = boot_device_spi_flash(); if (*flash == NULL) { @@ -76,6 +74,16 @@ return MBOX_PSP_COMMAND_PROCESS_ERROR; } + return MBOX_PSP_SUCCESS; +} + +static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_id, + struct region_device *store, + const struct spi_flash **flash) +{ + if (get_flash_device(flash) != MBOX_PSP_SUCCESS) + return MBOX_PSP_COMMAND_PROCESS_ERROR; + if (lookup_store(target_nv_id, store) < 0) { printk(BIOS_ERR, "PSP: Unable to find PSP SPI region\n"); return MBOX_PSP_COMMAND_PROCESS_ERROR; -- To view, visit https://review.coreboot.org/c/coreboot/+/84905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313 Gerrit-Change-Number: 84905 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/spi/spi_flash: make 'do_spi_flash_cmd' available to other files
by Felix Held (Code Review) 05 Nov '24

05 Nov '24

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84789?usp=email ) Change subject: drivers/spi/spi_flash: make 'do_spi_flash_cmd' available to other files ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > not crazy about the function name since it doesn't really distinguish itself from the single-byte ve […] see my comment on the first patchset; hope to get some second opinion on that one -- To view, visit https://review.coreboot.org/c/coreboot/+/84789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e Gerrit-Change-Number: 84789 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2024 15:02:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel/common: Add RAMTOP size in ramtop_table
by Subrata Banik (Code Review) 05 Nov '24

05 Nov '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85003?usp=email ) Change subject: soc/intel/common: Add RAMTOP size in ramtop_table ...................................................................... soc/intel/common: Add RAMTOP size in ramtop_table This patch adds a new field, `size`, to the `ramtop_table` structure to store the size of the RAMTOP region. The RAMTOP size is calculated as the difference between the cbmem top and the FSP reserved memory base address, aligned up to the nearest 4MB boundary. This change allows for more accurate tracking of the RAMTOP region and improves compatibility with different memory configurations. Previously, the RAMTOP size was always assumed to be 16MB. This could lead to boot hangs on systems with different memory configurations, where the actual RAMTOP size exceeded 16MB. By dynamically calculating and storing the RAMTOP size, this patch ensures that the correct memory range is used for intermediate caching, preventing boot hangs and improving boot speed. The `update_ramtop()` function is updated to write the calculated RAMTOP size to CMOS along with the RAMTOP address. The `early_ramtop_enable_cache_range()` function is also updated to use the RAMTOP size from CMOS to set the correct MTRR range. TEST=Built and booted successfully on various platforms. Verified that the RAMTOP size is correctly calculated and stored in CMOS Change-Id: I16d610c5791895b59da57d543c54da6621617912 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/basecode/ramtop/ramtop.c 1 file changed, 58 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85003/1 diff --git a/src/soc/intel/common/basecode/ramtop/ramtop.c b/src/soc/intel/common/basecode/ramtop/ramtop.c index 9cef9b1..59490b8 100644 --- a/src/soc/intel/common/basecode/ramtop/ramtop.c +++ b/src/soc/intel/common/basecode/ramtop/ramtop.c @@ -4,13 +4,14 @@ #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> +#include <fsp/util.h> #include <intelbasecode/ramtop.h> #include <pc80/mc146818rtc.h> #include <stdint.h> /* We need a region in CMOS to store the RAMTOP address */ -#define RAMTOP_SIGNATURE 0x52544F50 /* 'RTOP' */ +#define RAMTOP_SIGNATURE 0x504F5452 /* 'RTOP' */ /* * Address of the ramtop byte in CMOS. Should be reserved @@ -39,6 +40,7 @@ struct ramtop_table { uint32_t signature; uint32_t addr; + size_t size; uint16_t checksum; } __packed; @@ -57,6 +59,12 @@ return -1; } + /* Verify RAMTOP size */ + if (ramtop->size == 0) { + printk(BIOS_DEBUG, "ramtop_table holds invalid size\n"); + return -1; + } + /* Verify checksum over signature and counter only */ csum = ipchksum(ramtop, offsetof(struct ramtop_table, checksum)); @@ -80,6 +88,36 @@ cmos_write(*p, (CMOS_VSTART_ramtop / 8) + i); } +/* + * RAMTOP range: + * + * This defines the memory range covered by RAMTOP, which extends from + * cbmem_top down to FSP TOLUM. This range includes essential components: + * + * +---------------------------+ TOLUM / top_of_ram / cbmem_top + * | CBMEM Root | + * +---------------------------+ + * | FSP Reserved Memory | + * +---------------------------+ + * | various CBMEM entries | + * +---------------------------+ top_of_stack (8 byte aligned) + * | stack (CBMEM entry) | + * +---------------------------+ FSP TOLUM + * | | + * +---------------------------+ 0 +*/ +static size_t calculate_ramtop_size(uint32_t addr) +{ + struct range_entry fsp_mem; + uint32_t fsp_reserve_base; + fsp_find_reserved_memory(&fsp_mem); + + fsp_reserve_base = range_entry_base(&fsp_mem); + size_t ramtop_size = ALIGN_UP(addr - fsp_reserve_base, 4 * MiB); + + return ramtop_size; +} + /* Update the RAMTOP if required based on the input top_of_ram address */ void update_ramtop(uint32_t addr) { @@ -90,18 +128,23 @@ /* Structure invalid, re-initialize */ ramtop.signature = RAMTOP_SIGNATURE; ramtop.addr = 0; + ramtop.size = 0; } + size_t size = calculate_ramtop_size(addr); + /* Update ramtop if required */ - if (ramtop.addr == addr) + if ((ramtop.addr == addr) && (ramtop.size == size)) return; ramtop.addr = addr; + ramtop.size = size; /* Write the new top_of_ram address to CMOS */ ramtop_cmos_write(&ramtop); - printk(BIOS_DEBUG, "Updated the RAMTOP address into CMOS 0x%x\n", ramtop.addr); + printk(BIOS_DEBUG, "Updated the RAMTOP address (0x%x) with size (0x%lx) into CMOS\n", + ramtop.addr, ramtop.size); } uint32_t get_ramtop_addr(void) @@ -114,6 +157,16 @@ return ramtop.addr; } +static uint32_t get_ramtop_size(void) +{ + struct ramtop_table ramtop; + + if (ramtop_cmos_read(&ramtop) < 0) + return 0; + + return ramtop.size; +} + /* Early caching of top_of_ram region */ void early_ramtop_enable_cache_range(void) { @@ -127,6 +180,7 @@ return; } + size_t ramtop_size = get_ramtop_size(); /* * Background: Some SoCs have a critical bug inside the NEM logic which is responsible * for mapping cached memory to physical memory during tear down and @@ -145,5 +199,5 @@ if (is_cache_sets_power_of_two()) mtrr_type = MTRR_TYPE_WRBACK; - set_var_mtrr(mtrr, ramtop - 16 * MiB, 16 * MiB, mtrr_type); + set_var_mtrr(mtrr, ramtop - ramtop_size, ramtop_size, mtrr_type); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16d610c5791895b59da57d543c54da6621617912 Gerrit-Change-Number: 85003 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXART
by Subrata Banik (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kyle Lin, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/84999?usp=email ) Change subject: mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXART ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacf09cd46d4a97fb79f91043c84452f76689462f Gerrit-Change-Number: 84999 Gerrit-PatchSet: 8 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Nov 2024 13:27:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit November 2024