coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Yidi Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 02:56:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek: Obtain LPDDR type from trained memory info
by Yidi Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85033?usp=email ) Change subject: soc/mediatek: Obtain LPDDR type from trained memory info ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Gerrit-Change-Number: 85033 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 02:56:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Configure Acoustic noise mitigation
by Eric Lai (Code Review) 08 Nov '24

08 Nov '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84908?usp=email ) Change subject: mb/google/nissa/var/riven: Configure Acoustic noise mitigation ...................................................................... mb/google/nissa/var/riven: Configure Acoustic noise mitigation Follow the power team’s recommendation: - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:376165743 TEST=built firmware and verified by power team, the acoustic noise can be improved a lot. Change-Id: Ia71985ef21d634763fc5ae22e4f611f7f5e9652a Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84908 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/brya/variants/riven/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved Jayvik Desai: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb index d565897..00947c4 100644 --- a/src/mainboard/google/brya/variants/riven/overridetree.cb +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -24,6 +24,13 @@ end chip soc/intel/alderlake + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "sagv" = "SaGv_Enabled" # EMMC Tx CMD Delay -- To view, visit https://review.coreboot.org/c/coreboot/+/84908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia71985ef21d634763fc5ae22e4f611f7f5e9652a Gerrit-Change-Number: 84908 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo. Hello Crystal Guo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85034?usp=email to review the following change. Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... mem_chip_info: Add LPDDR5 enums to mem_chip_type Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. BUG=b:357743097 TEST=build pass Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85034/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h index 5d4d37c..f191cc7 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h +++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h @@ -6,11 +6,15 @@ #include <stddef.h> enum mem_chip_type { + MEM_CHIP_UNDEFINED = 0x00, MEM_CHIP_DDR3 = 0x30, MEM_CHIP_LPDDR3 = 0x38, MEM_CHIP_DDR4 = 0x40, MEM_CHIP_LPDDR4 = 0x48, MEM_CHIP_LPDDR4X = 0x49, + MEM_CHIP_DDR5 = 0x50, + MEM_CHIP_LPDDR5 = 0x58, + MEM_CHIP_LPDDR5X = 0x59, }; #define MEM_CHIP_STRUCT_VERSION 0 /* Hopefully we'll never have to bump this... */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/mediatek: Obtain LPDDR type from trained memory info
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo. Hello Crystal Guo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85033?usp=email to review the following change. Change subject: soc/mediatek: Obtain LPDDR type from trained memory info ...................................................................... soc/mediatek: Obtain LPDDR type from trained memory info Add lpddr_type to ddr_base_info struct to obtain LPDDR type from trained memory info. BUG=b:357743097 TEST=build pass Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/dramc_param_common.h M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/common/memory.c 3 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85033/1 diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h index 7dd8bba..a1fac9a 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param_common.h +++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h @@ -92,7 +92,8 @@ struct ddr_base_info { u32 config_dvfs; /* SDRAM_DVFS_FLAG */ struct sdram_info sdram; - u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ + u16 lpddr_type; + u16 voltage_type; /* SDRAM_VOLTAGE_TYPE */ u32 support_ranks; u64 rank_size[RANK_MAX]; struct emi_mdl emi_config; diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h index 0070ec1..313ccff 100644 --- a/src/soc/mediatek/common/include/soc/emi.h +++ b/src/soc/mediatek/common/include/soc/emi.h @@ -16,5 +16,6 @@ u32 get_ddr_geometry(void); u32 get_ddr_type(void); void init_dram_by_params(struct dramc_param *dparam); +enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type); #endif /* SOC_MEDIATEK_COMMON_EMI_H */ diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 72ea37e..fff9c4e 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -109,6 +109,11 @@ return size; } +__weak enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type) +{ + return MEM_CHIP_LPDDR4X; +} + static void fill_dram_info(struct mem_chip_info *mc, const struct ddr_base_info *ddr) { unsigned int c, r; @@ -121,7 +126,7 @@ for (r = 0; r < ddr->mrr_info.rank_nums; r++) { entry->channel = c; entry->rank = r; - entry->type = MEM_CHIP_LPDDR4X; + entry->type = map_to_lpddr_dram_type(ddr->lpddr_type); entry->channel_io_width = DQ_DATA_WIDTH_LP4; entry->density_mbits = ddr->mrr_info.mr8_density[r] / CHANNEL_MAX / (MiB / 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/85033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Gerrit-Change-Number: 85033 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Karthik Ramasubramanian (Code Review) 08 Nov '24

08 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:377400590 TEST=Tested on Drawman with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 BRANCH=firmware-dedede-13606.B Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/85011 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 67c9262..6c745d9 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -7,6 +7,9 @@ end chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Lean Sheng Tan, Paul Menzel, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 29: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83318/comment/73b83d7f_b1d157fb?us… : PS29, Line 9: Intel server process has > Intel server processors have Done File src/soc/intel/common/block/systemagent-server/memmap.c: https://review.coreboot.org/c/coreboot/+/83318/comment/ca9f6259_c43ac4cd?us… : PS29, Line 25: die("NO_FSP_TEMP_RAM_EXIT is not supportted currently!"); > This could be implemented as a static assertion to cause a build-time error. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 29 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 00:35:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Lean Sheng Tan, Paul Menzel, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 29: (3 comments) File src/soc/intel/common/block/systemagent-server/Kconfig: https://review.coreboot.org/c/coreboot/+/83318/comment/99979e66_3a4b6a67?us… : PS26, Line 15: treated as 1s. > to clean up? Done https://review.coreboot.org/c/coreboot/+/83318/comment/15b71f23_b93595f1?us… : PS26, Line 26: default 0x100000 > to clean up? Done File src/soc/intel/common/block/systemagent-server/common.c: https://review.coreboot.org/c/coreboot/+/83318/comment/5fa90248_59b603b9?us… : PS29, Line 8: pci_moving_config32 > I thought this existed in common code, any reason not to use it? The common code is aimed to be used in ramstage, i.e., the first parameter is `struct device *`, but I need this function in romstage to probe the alignment of TSEG base. -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 29 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 00:35:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email ) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... Patch Set 53: (4 comments) File src/mainboard/intel/frost_creek/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/83322/comment/37c2aa7a_3e0ecff8?us… : PS19, Line 3: Scope (\_SB) > where is this included? This file is not used and I removed it. https://review.coreboot.org/c/coreboot/+/83322/comment/28f8ad43_5aeaecde?us… : PS19, Line 10: Name(_PRW, Package(){0x1d, 0x05}) > S3 is supported? This file has been removed. File src/mainboard/intel/frost_creek/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/83322/comment/1dc950f9_fb5992dd?us… : PS19, Line 3: // IO-Trap at 0x800. This is the ACPI->SMI communication interface. > the scope is \SB? The object and method defined in this file is not referenced any where in the whole ASL source file, so it could be removed. File src/mainboard/intel/frost_creek/romstage.c: https://review.coreboot.org/c/coreboot/+/83322/comment/50b48565_fe3a371b?us… : PS44, Line 12: void mainboard_config_gpios(void) > I renamed `gpio.inc` to `gpio.c` and move this function into it. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 53 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 08 Nov 2024 00:34:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: mb/topton/adl: Add initial support for X2F N100 FW appliance
by Alicja Michalska (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/84175?usp=email ) Change subject: mb/topton/adl: Add initial support for X2F N100 FW appliance ...................................................................... Patch Set 9: (2 comments) File src/mainboard/topton/adl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84175/comment/cec59996_543bd25b?us… : PS2, Line 43: # TODO: SATA doesn't work. EDK2 returns "Unsupported", not sure how to fix (yet). > I meant these: […] I believe ADL-N has two SATA ports, but when I tried adding what you just mentioned - drive wasn't recognized in EDK2. While testing Windows, it complained about I/O bus error (which is honestly my first time seeing this issue, SATA usually "just works). I did check it of course, here's a list of lspci from stock firmware (I don't enable TB4, HDA or I2C in devicetree, as there's nothing on those buses): ``` 00:00.0 Host bridge [0600]: Intel Corporation Device [8086:461c] 00:02.0 VGA compatible controller [0300]: Intel Corporation Alder Lake-N [UHD Graphics] [8086:46d1] (prog-if 00 [VGA controller]) 00:0d.0 USB controller [0c03]: Intel Corporation Alder Lake-N Thunderbolt 4 USB Controller [8086:464e] (prog-if 30 [XHCI]) 00:14.0 USB controller [0c03]: Intel Corporation Alder Lake-N PCH USB 3.2 xHCI Host Controller [8086:54ed] (prog-if 30 [XHCI]) 00:14.2 RAM memory [0500]: Intel Corporation Alder Lake-N PCH Shared SRAM [8086:54ef] 00:16.0 Communication controller [0780]: Intel Corporation Alder Lake-N PCH HECI Controller [8086:54e0] 00:17.0 SATA controller [0106]: Intel Corporation Alder Lake-N SATA AHCI Controller [8086:54d3] (prog-if 01 [AHCI 1.0]) DeviceName: Onboard - SATA Subsystem: Intel Corporation Device [8086:7270] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 125 Region 0: Memory at 81100000 (32-bit, non-prefetchable) [size=8K] Region 1: Memory at 81103000 (32-bit, non-prefetchable) [size=256] Region 2: I/O ports at 3090 [size=8] Region 3: I/O ports at 3080 [size=4] Region 4: I/O ports at 3060 [size=32] Region 5: Memory at 81102000 (32-bit, non-prefetchable) [size=2K] Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee002f8 Data: 0000 Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a8] SATA HBA v1.0 BAR4 Offset=00000004 Kernel driver in use: ahci 00:1c.0 PCI bridge [0604]: Intel Corporation Device [8086:54b8] (prog-if 00 [Normal decode]) 00:1c.1 PCI bridge [0604]: Intel Corporation Device [8086:54b9] (prog-if 00 [Normal decode]) 00:1c.2 PCI bridge [0604]: Intel Corporation Device [8086:54ba] (prog-if 00 [Normal decode]) 00:1c.6 PCI bridge [0604]: Intel Corporation Device [8086:54be] (prog-if 00 [Normal decode]) 00:1d.0 PCI bridge [0604]: Intel Corporation Alder Lake-N PCI Express Root Port #9 [8086:54b0] (prog-if 00 [Normal decode]) 00:1f.0 ISA bridge [0601]: Intel Corporation Alder Lake-N PCH eSPI Controller [8086:5481] 00:1f.3 Audio device [0403]: Intel Corporation Alder Lake-N PCH High Definition Audio Controller [8086:54c8] 00:1f.4 SMBus [0c05]: Intel Corporation Alder Lake-N SMBus [8086:54a3] 00:1f.5 Serial bus controller [0c80]: Intel Corporation Alder Lake-N SPI (flash) Controller [8086:54a4] 01:00.0 Ethernet controller [0200]: Intel Corporation Ethernet Controller I226-V [8086:125c] (rev 04) 02:00.0 Ethernet controller [0200]: Intel Corporation Ethernet Controller I226-V [8086:125c] (rev 04) 03:00.0 Ethernet controller [0200]: Intel Corporation Ethernet Controller I226-V [8086:125c] (rev 04) 04:00.0 Ethernet controller [0200]: Intel Corporation Ethernet Controller I226-V [8086:125c] (rev 04) 05:00.0 Non-Volatile memory controller [0108]: Kingston Technology Company, Inc. OM3PDP3 NVMe SSD [2646:500d] (rev 01) (prog-if 02 [NVM Express]) ``` File src/mainboard/topton/adl/mainboard.c: https://review.coreboot.org/c/coreboot/+/84175/comment/356fa809_d4e024d3?us… : PS9, Line 17: params->PchLegacyIoLowLatency = 1; > I think I commented on what this was, could you please add a comment so that I don't ask over and ov […] It disables some DMI-related power saving features, I probably could remove it if I do a bit more testing. I had a lot of issues with NVME on my previous port without it. ``` Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency. Note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent and ITSS Clock Gating are forced to disabled. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65 Gerrit-Change-Number: 84175 Gerrit-PatchSet: 9 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 00:09:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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