coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: add touchpad init config and rtd3 for wifi7...
by Rui Zhou (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84997?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: add touchpad init config and rtd3 for wifi7 and change ssd timeing ...................................................................... mb/google/nissa/var/rull: add touchpad init config and rtd3 for wifi7 and change ssd timeing We initialize the touchpad initialization configuration. Change wifi7 gpio_padbased mode to rtd3. At the same time, the previous GPIO configuration will cause the SSD device to not be recognized. We adjust the position of the enable and reset pins. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully 3. touchpad Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab --- M src/mainboard/google/brya/variants/rull/gpio.c M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 3 files changed, 55 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84997/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Gerrit-Change-Number: 84997 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: add touchpad init config and change ssd ti...
by Rui Zhou (Code Review) 05 Nov '24

05 Nov '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84997?usp=email ) Change subject: mb/google/nissa/var/rull: add touchpad init config and change ssd timeing ...................................................................... mb/google/nissa/var/rull: add touchpad init config and change ssd timeing We initialize the touchpad initialization configuration. At the same time, the previous GPIO configuration will cause the SSD device to not be recognized. We adjust the position of the enable and reset pins. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully 3. touchpad Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab --- M src/mainboard/google/brya/variants/rull/gpio.c M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 3 files changed, 55 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84997/1 diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c index 13d6469..03cadaa 100644 --- a/src/mainboard/google/brya/variants/rull/gpio.c +++ b/src/mainboard/google/brya/variants/rull/gpio.c @@ -23,14 +23,17 @@ /* A22 : GPP_A22 ==> NC */ PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), - /* B4 : I2C2_SDA ==> SSD1_RST_L */ - PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : I2C2_SDA ==> NA */ PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : I2C2_SCL ==> NA */ PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B11 : NC ==> EN_PP3300_WLAN_X*/ - PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_GPO(GPP_B11, 1, DEEP), + + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NA */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), @@ -38,8 +41,7 @@ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), - /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D13 : EN_PP1800_WCAM_X ==> NA */ PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D15 : EN_PP2800_WCAM_X ==> NA */ @@ -56,6 +58,8 @@ /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), + /* F11 : NC ==> WWAN_PWR_ON */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : WWAN_RST_L ==> NA */ PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : SOC_PEN_DETECT_R_ODL ==> NA */ @@ -78,7 +82,9 @@ PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), /* H23 : WWAN_SAR_DETECT_ODL ==> NA */ PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), - + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */ @@ -105,6 +111,9 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* B4 : I2C2_SDA ==> SSD1_RST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), @@ -116,11 +125,6 @@ /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), - /* F11 : NC ==> WWAN_PWR_ON */ - PAD_CFG_GPO(GPP_F11, 1, DEEP), - /* F12 : GSXDOUT ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), - /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ @@ -132,9 +136,12 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { + }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d91a7aa..b59a0de 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -231,7 +231,27 @@ device i2c 1a on end end end - device ref i2c5 off end # Touchpad + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""PIXART Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 68 on end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" @@ -254,6 +274,13 @@ register "add_acpi_dma_property" = "true" device pci 00.0 on end end + chip soc/intel/common/block/pcie/rtd3 + # # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end probe WIFI WIFI_PCIE_WIFI7 probe unprovisioned end @@ -405,13 +432,14 @@ }" chip soc/intel/common/block/pcie/rtd3 # enable_gpio is EN_PP3300_SSD - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D11)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" register "srcclk_pin" = "1" - device generic 0 on end + device generic 0 on + probe STORAGE STORAGE_NVME + probe unprovisioned + end end - probe STORAGE STORAGE_NVME - probe unprovisioned end device ref emmc on probe STORAGE STORAGE_EMMC diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index a2fffb4..1f51c09 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -16,29 +16,12 @@ return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); } -static const struct pad_config wifi_pcie_enable_pad[] = { - /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), - /* B11 : NC ==> EN_PP3300_WLAN_X*/ - PAD_CFG_GPO(GPP_B11, 1, DEEP), -}; - void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_is_provisioned()) { - printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); - config->cnvi_bt_core = false; - printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n"); - config->cnvi_bt_audio_offload = false; - } -} - -void fw_config_gpio_padbased_override(struct pad_config *padbased_table) -{ if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || !fw_config_is_provisioned()) { - printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n"); - gpio_padbased_override(padbased_table, wifi_pcie_enable_pad, - ARRAY_SIZE(wifi_pcie_enable_pad)); + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + config->cnvi_bt_audio_offload = true; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/84997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Gerrit-Change-Number: 84997 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Update ext_vr for board version > b
by Robert Chen (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Derek Huang, Karthik Ramasubramanian, Paul Menzel, Shou-Chieh Hsu. Robert Chen has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/84953?usp=email ) Change subject: mb/google/dedede/var/drawcia: Update ext_vr for board version > b ...................................................................... Patch Set 15: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84953/comment/5714585b_a9f1b804?us… : PS14, Line 13: > Too many blank lines. Please leave just one blank line between here and BUG line. Done File src/mainboard/google/dedede/variants/drawcia/ramstage.c: https://review.coreboot.org/c/coreboot/+/84953/comment/476a36e1_41476ba8?us… : PS14, Line 39: if (board_version != 0xa && : board_version != 0xb && : board_version != 0xf) > Can be wrapped into one line? Sorry I missed this earlier. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Gerrit-Change-Number: 84953 Gerrit-PatchSet: 15 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 06:20:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Update ext_vr for board version > b
by Robert Chen (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Derek Huang, Paul Menzel, Robert Chen, Shou-Chieh Hsu. Hello Derek Huang, Karthik Ramasubramanian, Shou-Chieh Hsu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84953?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/dedede/var/drawcia: Update ext_vr for board version > b ...................................................................... mb/google/dedede/var/drawcia: Update ext_vr for board version > b ext_vr_update should be run after board version 0xb, but skipped by return. Drawper LTE board version was set after 0x9, but there are more board added after that. Specific Drawper board version as 0xa, 0xb and 0xf. BUG=b:376828839 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage and test on DUTs. Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/drawcia/ramstage.c 1 file changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/84953/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/84953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Gerrit-Change-Number: 84953 Gerrit-PatchSet: 15 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
by Karthik Ramasubramanian (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Hualin Wei, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Hualin Wei. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email ) Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/dedede/variants/awasuki/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84951/comment/62ad6698_f53e02f0?us… : PS3, Line 3: PcieRpLtrEnable This field does not exist in soc_intel_jasperlake_config. Are you sure you are updating the right field? -- To view, visit https://review.coreboot.org/c/coreboot/+/84951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Gerrit-Change-Number: 84951 Gerrit-PatchSet: 3 Gerrit-Owner: Hualin Wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Hualin Wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 05:38:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update SAF base address
by Subrata Banik (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Anil Kumar K, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/84863?usp=email ) Change subject: soc/intel/pantherlake: Update SAF base address ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/pantherlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/84863/comment/8f341bca_643a6e9d?us… : PS2, Line 19: SAF_BASE_ADDRESS > Hi Subrata. We are in the process of updating external document . The address 0xFA000000 is the correct address for SAF do you have an ETA, depending on that, either I can wait or land this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/84863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14fa8cf06144f46369cc8cab6087c790280e9859 Gerrit-Change-Number: 84863 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 05:24:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix uninitialized usb_cfg pointer
by Subrata Banik (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84939?usp=email ) Change subject: soc/intel/alderlake: Fix uninitialized usb_cfg pointer ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84939/comment/c5262132_7135ccfe?us… : PS2, Line 908: : usb_cfg = port->chip_info; > The next line confirms that usb_cfg is not NULL. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Gerrit-Change-Number: 84939 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 05:22:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Hint romstage init about upcoming reset
by Subrata Banik (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Bob Moragues, Karthik Ramasubramanian, Paul Menzel, Shyam Sundar Radjacoumar. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84937?usp=email ) Change subject: mb/google/brox: Hint romstage init about upcoming reset ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/brox/variants/baseboard/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/84937/comment/5aae302d_7909457f?us… : PS5, Line 24: ret = google_chromeec_get_num_pd_ports(&num_ports); : if (ret < 0 || !num_ports) { : printk(BIOS_INFO, "%s: Cannot resolve # of USB PD ports\n", __func__); : return mismatch; : } I'm wondering if we need to call this API at all. This is mainboard-specific code and we know Brox has PD ports, so this may not be needed for mainboard code alone. Perhaps if you moved this code into SOC or a common location, then checking for the presence of PD ports would make more sense. In Brox's case, reading the PDC info looks more meaningful. thoughts ? https://review.coreboot.org/c/coreboot/+/84937/comment/308a5d55_386c6af2?us… : PS5, Line 30: google_chromeec_get_pd_chip_infoi is this a typo ? `_infoi` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Gerrit-Change-Number: 84937 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 05:22:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Generate RAM ID for MT62F2G32D4DS-020 WT:F
by 9elements QA (Code Review) 05 Nov '24

05 Nov '24

9elements QA has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/84781?usp=email ) Change subject: mb/google/fatcat/var/francka: Generate RAM ID for MT62F2G32D4DS-020 WT:F ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/223434 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/223432 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/223431 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/223430 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/223429 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/223428 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/223427 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/223426 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/223425 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/223424 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/223423 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/223422 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/84781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2de56c8c7a028edefbd3dc53f8b1e26dee3286f7 Gerrit-Change-Number: 84781 Gerrit-PatchSet: 6 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 05:20:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Add initial LTE related settings
by Subrata Banik (Code Review) 05 Nov '24

05 Nov '24

Attention is currently required from: Anson Tseng, Daniel Peng, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Ricky Chang. Subrata Banik has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/84925?usp=email ) Change subject: mb/google/nissa/var/glassway: Add initial LTE related settings ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Gerrit-Change-Number: 84925 Gerrit-PatchSet: 5 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Tue, 05 Nov 2024 05:14:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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