coreboot-gerrit November 2024

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84929?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. TEST=build pass, When we encounter a bus hang and hw watchdog causes the platform to restart, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/common/include/soc/tracker_common.h M src/soc/mediatek/common/tracker.c M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 7 files changed, 191 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Jarried Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84932?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Configure TPM ...................................................................... mb/google/rauru: Configure TPM 1. Add TPM support 2. Configure I2C speed to I2C_SPEED_FAST_PLUS 3. Pass GPIO_GSC_AP_INT_ODL to the payload 4. Configure IRQ type to IRQ_TYPE_LEVEL_LOW for now TEST=build pass, boot ok and there is no CR50 TPM timeout log BUG=b:317009620 Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/bootblock.c M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 4 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84932/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Pass reset gpio parameter to BL31
by Yidi Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84933?usp=email ) Change subject: mb/google/rauru: Pass reset gpio parameter to BL31 ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84933?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4 Gerrit-Change-Number: 84933 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 13:02:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Yidi Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84932?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rauru: Configure TPM ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/rauru/bootblock.c: https://review.coreboot.org/c/coreboot/+/84932/comment/6efb0d7f_b9a102ba?us… : PS9, Line 27: IRQ_TYPE_LEVEL_LOW This should be `IRQ_TYPE_EDGE_RISING`. `IRQ_TYPE_LEVEL_LOW` was a workaround for the buggy EINT driver at the bringup stage. Please verify the communication between AP and GSC after changing to `IRQ_TYPE_EDGE_RISING`. -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 13:01:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/rauru: Enable ChromeOS EC
by Yidi Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84931?usp=email ) Change subject: mb/google/rauru: Enable ChromeOS EC ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059 Gerrit-Change-Number: 84931 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 12:51:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add SPI driver support
by Yidi Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84930?usp=email ) Change subject: soc/mediatek/mt8196: Add SPI driver support ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84930?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Gerrit-Change-Number: 84930 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 12:51:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add support for audio codec/amp
by Tyler Wang (Code Review) 07 Nov '24

07 Nov '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85023?usp=email ) Change subject: mb/google/rex/var/kanix: Add support for audio codec/amp ...................................................................... mb/google/rex/var/kanix: Add support for audio codec/amp Add support for audio codec ALC5882I and audio amp ALC1019. BUG=none TEST=none Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/kanix/overridetree.cb 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85023/1 diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 272f92f..79b42b4 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -340,7 +340,25 @@ device generic 0 on end end end - device ref i2c0 on end #I2C0 + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on end + end + end #I2C0 device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" @@ -514,6 +532,13 @@ end end end - device ref hda on end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "rt1019" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457 Gerrit-Change-Number: 85023 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Add new board variant Hylia
by Yu-Ping Wu (Code Review) 07 Nov '24

07 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84924?usp=email ) Change subject: mb/google/rauru: Add new board variant Hylia ...................................................................... mb/google/rauru: Add new board variant Hylia Add a new Rauru follower 'Hylia'. BRANCH=rauru BUG=b:376357839 TEST=emerge-rauru coreboot chromeos-bootimage Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84924 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/Kconfig.name 2 files changed, 8 insertions(+), 3 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 3d9c3e6..457b5fb 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -2,7 +2,8 @@ # Umbrella option to be selected by variant boards. config BOARD_GOOGLE_RAURU_COMMON - def_bool BOARD_GOOGLE_NAVI || \ + def_bool BOARD_GOOGLE_HYLIA || \ + BOARD_GOOGLE_NAVI || \ BOARD_GOOGLE_RAURU if BOARD_GOOGLE_RAURU_COMMON @@ -27,6 +28,7 @@ config MAINBOARD_PART_NUMBER string + default "Hylia" if BOARD_GOOGLE_HYLIA default "Navi" if BOARD_GOOGLE_NAVI default "Rauru" if BOARD_GOOGLE_RAURU diff --git a/src/mainboard/google/rauru/Kconfig.name b/src/mainboard/google/rauru/Kconfig.name index a16c331..589e131 100644 --- a/src/mainboard/google/rauru/Kconfig.name +++ b/src/mainboard/google/rauru/Kconfig.name @@ -2,8 +2,11 @@ comment "Rauru" -config BOARD_GOOGLE_RAURU - bool "-> Rauru" +config BOARD_GOOGLE_HYLIA + bool "-> Hylia" config BOARD_GOOGLE_NAVI bool "-> Navi" + +config BOARD_GOOGLE_RAURU + bool "-> Rauru" -- To view, visit https://review.coreboot.org/c/coreboot/+/84924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Gerrit-Change-Number: 84924 Gerrit-PatchSet: 4 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) - Boots Linux 6.11 (Debian) - GRUB and SeaBIOS payloads work - SMSC SCH5553 SIO/EC + Serial port works + PWM fan control works - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/admin/repos/deguard,general - Audio works - All USB ports work - Currently limited to the Micro form factor, but others are very similar - HDA verbs and VBT by Leah Rowe Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82053 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/optiplex_3050/Kconfig A src/mainboard/dell/optiplex_3050/Kconfig.name A src/mainboard/dell/optiplex_3050/Makefile.mk A src/mainboard/dell/optiplex_3050/acpi/ec.asl A src/mainboard/dell/optiplex_3050/acpi/superio.asl A src/mainboard/dell/optiplex_3050/board_info.txt A src/mainboard/dell/optiplex_3050/bootblock.c A src/mainboard/dell/optiplex_3050/cmos.default A src/mainboard/dell/optiplex_3050/cmos.layout A src/mainboard/dell/optiplex_3050/data.vbt A src/mainboard/dell/optiplex_3050/devicetree.cb A src/mainboard/dell/optiplex_3050/dsdt.asl A src/mainboard/dell/optiplex_3050/gma-mainboard.ads A src/mainboard/dell/optiplex_3050/hda_verb.c A src/mainboard/dell/optiplex_3050/include/early_gpio.h A src/mainboard/dell/optiplex_3050/include/gpio.h A src/mainboard/dell/optiplex_3050/ramstage.c A src/mainboard/dell/optiplex_3050/romstage.c A src/mainboard/dell/optiplex_3050/sch5555_ec.c A src/mainboard/dell/optiplex_3050/sch5555_ec.h 20 files changed, 1,317 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig new file mode 100644 index 0000000..6c8e729 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_DELL_OPTIPLEX_3050 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_ADD_VBT + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_SUPPORTS_KABYLAKE_CPU + select MAINBOARD_SUPPORTS_SKYLAKE_CPU + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SUPERIO_SMSC_SCH555x + +config CBFS_SIZE + default 0x900000 + +config MAINBOARD_DIR + default "dell/optiplex_3050" + +config MAINBOARD_PART_NUMBER + default "OptiPlex 3050 Micro" + +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" + +config DIMM_SPD_SIZE + default 512 # DDR4 + +endif diff --git a/src/mainboard/dell/optiplex_3050/Kconfig.name b/src/mainboard/dell/optiplex_3050/Kconfig.name new file mode 100644 index 0000000..14eab7f --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_OPTIPLEX_3050 + bool "OptiPlex 3050 Micro" diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk new file mode 100644 index 0000000..0bd72fe --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += sch5555_ec.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += sch5555_ec.c +ramstage-y += hda_verb.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/optiplex_3050/acpi/ec.asl b/src/mainboard/dell/optiplex_3050/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/optiplex_3050/acpi/superio.asl b/src/mainboard/dell/optiplex_3050/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/optiplex_3050/board_info.txt b/src/mainboard/dell/optiplex_3050/board_info.txt new file mode 100644 index 0000000..47a4a3a --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.dell.com/support/kbdoc/en-uk/000124265/dell-optiplex-3050-syste… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/dell/optiplex_3050/bootblock.c b/src/mainboard/dell/optiplex_3050/bootblock.c new file mode 100644 index 0000000..10689c4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/bootblock.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <soc/gpio.h> +#include <superio/smsc/sch555x/sch555x.h> +#include "include/early_gpio.h" +#include "sch5555_ec.h" + +struct ec_init_entry { + uint16_t addr; + uint8_t val; +}; + +static void bootblock_ec_init(void) +{ + /* + * Early EC init + */ + + static const struct ec_init_entry init_table1[] = { + {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, + {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, + {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, + {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, + {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, + {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) + sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); + + static const struct ec_init_entry init_table2[] = { + {0x0040, 0x00}, {0x00f8, 0x10}, {0x00f9, 0x00}, {0x00f0, 0x30}, + {0x00fa, 0x00}, {0x00fb, 0x00}, {0x00ea, 0x00}, {0x00eb, 0x00}, + {0x00ef, 0x7c}, {0x0005, 0x0f}, {0x0014, 0x01}, {0x0018, 0x2f}, + {0x0019, 0x2f}, {0x001a, 0x2f}, {0x001b, 0x2f}, {0x01d8, 0x01}, + {0x0040, 0x11}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) + sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); + + sch5555_mbox_write(1, 0x000b, 0x01); + sch5555_mbox_write(4, 0x001a, 0x04); + sch5555_mbox_write(4, 0x0028, 0x18); + sch5555_mbox_write(4, 0x001a, 0x00); + sch5555_mbox_write(1, 0x000b, 0x03); + + /* + * Early HWM init + */ + + sch5555_mbox_read(1, 0xcb); + sch5555_mbox_read(1, 0xb8); + + static const struct ec_init_entry hwm_init_table[] = { + {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, + {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, + {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, + {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, + {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, + {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, + {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, + {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, + {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, + {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, + {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, + {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, + {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, + {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, + {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, + {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, + {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, + {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, + {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, {0x0015, 0x33}, + {0x018b, 0x00}, {0x018c, 0x00}, {0x02f8, 0x5e}, {0x02f9, 0x01}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) + sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); +} + + +#define SCH555x_IOBASE 0x2e +#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) +#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) + +void bootblock_mainboard_early_init(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + + // Super I/O early init will map Runtime and EMI registers + sch555x_early_init(GLOBAL_DEV); + + // Changes LED color among a few other things + outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); + outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); + outb(0xf, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); + outb(1, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); + + // Perform bootblock EC initialization + bootblock_ec_init(); + + // Bootblock EC initialization is required for UART1 to work + sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/dell/optiplex_3050/cmos.default b/src/mainboard/dell/optiplex_3050/cmos.default new file mode 100644 index 0000000..79961f4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/cmos.default @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable diff --git a/src/mainboard/dell/optiplex_3050/cmos.layout b/src/mainboard/dell/optiplex_3050/cmos.layout new file mode 100644 index 0000000..54a5147 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/cmos.layout @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/dell/optiplex_3050/data.vbt b/src/mainboard/dell/optiplex_3050/data.vbt new file mode 100644 index 0000000..6dc40cd --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/data.vbt Binary files differ diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb new file mode 100644 index 0000000..039709a --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/devicetree.cb @@ -0,0 +1,103 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + device domain 0 on + device ref igpu on + register "PrimaryDisplay" = "Display_iGFX" + end + + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), // Front panel (blue) + [1] = USB2_PORT_MID(OC0), // Front panel (blue) + [2] = USB2_PORT_MID(OC3), // Back panel (black) + [3] = USB2_PORT_MID(OC2), // Back panel (blue) + [4] = USB2_PORT_MID(OC1), // Back panel (blue) + [6] = USB2_PORT_MID(OC1), // Back panel (black) + [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) + [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) + [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) + [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) + }" + end + + # ME interface is 'off' to avoid HECI reset delay due to HAP + device ref heci1 off end + + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + end + + # M.2 SSD + device ref pcie_rp21 on + register "PcieRpEnable[20]" = "1" + register "PcieRpClkReqSupport[20]" = "1" + register "PcieRpClkReqNumber[20]" = "3" + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" + register "PcieRpClkSrcNumber[20]" = "3" + register "PcieRpHotPlug[20]" = "1" + end + + # Realtek LAN + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + register "PcieRpHotPlug[4]" = "0" + end + + # M.2 WiFi + device ref pcie_rp8 on + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "0" + register "PcieRpHotPlug[7]" = "1" + end + + # UART0 is exposed on test points on the bottom of the board + device ref uart0 on + register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci" + end + + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # I/O decode for EMI/Runtime registers + register "gen1_dec" = "0x007c0a01" + + # SCH5553 + chip superio/smsc/sch555x + device pnp 2e.0 on # EMI + io 0x60 = 0xa00 + end + device pnp 2e.1 off end # 8042 + device pnp 2e.7 on # UART1 + io 0x60 = 0x3f8 + irq 0x0f = 2 + irq 0x70 = 4 + end + device pnp 2e.8 off end # UART2 + device pnp 2e.c on # LPC interface + io 0x60 = 0x2e + end + device pnp 2e.a on # Runtime registers + io 0x60 = 0xa40 + end + device pnp 2e.b off end # Floppy Controller + device pnp 2e.11 off end # Parallel Port + end + end + + device ref hda on end + + device ref smbus on end + end +end diff --git a/src/mainboard/dell/optiplex_3050/dsdt.asl b/src/mainboard/dell/optiplex_3050/dsdt.asl new file mode 100644 index 0000000..9762f6f --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/dell/optiplex_3050/gma-mainboard.ads b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads new file mode 100644 index 0000000..cb4c22f --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- External HDMI + DP2, -- External DP (native) + HDMI2, -- External DP (DP++) + DP3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) + HDMI3, -- Video I/O card: VGA (0PKGGG), DP (H64DC) + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/optiplex_3050/hda_verb.c b/src/mainboard/dell/optiplex_3050/hda_verb.c new file mode 100644 index 0000000..621e4f7 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/hda_verb.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header, codec 0 */ + 0x10ec0255, /* Realtek ALC3234 */ + 0x102807a3, /* Subsystem ID */ + 11, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_SUBVENDOR(0, 0x102807a3), + + AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 5, 0 + )), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x1d, 0x4054c029), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 5, 15 + )), + + /* coreboot specific header, codec 2 */ + 0x80862809, /* Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_3050/include/early_gpio.h b/src/mainboard/dell/optiplex_3050/include/early_gpio.h new file mode 100644 index 0000000..17a1637 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/include/early_gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __OPTIPLEX_3050_EARLY_GPIO_H__ +#define __OPTIPLEX_3050_EARLY_GPIO_H__ + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ +}; + +#endif diff --git a/src/mainboard/dell/optiplex_3050/include/gpio.h b/src/mainboard/dell/optiplex_3050/include/gpio.h new file mode 100644 index 0000000..83293c3 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/include/gpio.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __OPTIPLEX_3050_GPIO_H__ +#define __OPTIPLEX_3050_GPIO_H__ + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, PLTRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */ + PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* PME# */ + PAD_CFG_GPO(GPP_A12, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), /* SUSWARN#/SUSPWRDNACK */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_A15, UP_20K, PLTRST, NF1), /* SUS_ACK# */ + PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A18, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A19, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A22, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B1, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B2, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B3, 1, RSMRST), /* GPIO (ME_CNTL, B3 -> LOW => HDA_SDO -> HIGH) */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B5, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B6, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B7, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B9, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B10, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */ + PAD_CFG_GPO(GPP_B15, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* GSPIO_MOSI */ + PAD_CFG_GPO(GPP_B19, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GSPI1_MOSI */ + PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* PCHHOT# */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_C2, DN_20K, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, PLTRST, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, PLTRST, NF1), /* SML0DATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ + PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C11, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C12, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C13, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C14, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* I2C0_SCL */ + PAD_CFG_GPO(GPP_C18, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C19, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C20, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C21, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C22, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D1, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D2, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D3, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D7, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D9, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D11, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D13, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D14, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D15, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D19, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D20, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D21, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D22, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D23, 0, PLTRST), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E6, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ + PAD_CFG_NF(GPP_E9, UP_20K, PLTRST, NF1), /* USB_OC0# */ + PAD_CFG_NF(GPP_E10, UP_20K, PLTRST, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_E11, UP_20K, PLTRST, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_E12, UP_20K, PLTRST, NF1), /* USB_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* SATAXPCIE3 */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* SATAXPCIE4 */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* SATAXPCIE5 */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* SATAXPCIE6 */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* SATAXPCIE7 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_F6, NONE, RSMRST, NF1), /* SATA_DEVSLP4 */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_F9, 0, RSMRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_F13, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), /* USB_OC4# */ + PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), /* USB_OC5# */ + PAD_CFG_NF(GPP_F17, UP_20K, PLTRST, NF1), /* USB_OC6# */ + PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F21, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F22, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 1, RSMRST), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_G9, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_G12, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_G14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G15, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G16, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G17, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G18, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G19, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G23, 0, PLTRST), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H2, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H3, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H4, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H5, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H6, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H7, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H8, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H9, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H10, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H11, 0, PLTRST), /* GPIO */ + PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H16, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H19, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H20, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H21, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H22, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H23, 0, PLTRST), /* GPIO */ + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ + PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 1, RSMRST), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 1, RSMRST), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */ + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */ +}; + +#endif diff --git a/src/mainboard/dell/optiplex_3050/ramstage.c b/src/mainboard/dell/optiplex_3050/ramstage.c new file mode 100644 index 0000000..94778f6 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/ramstage.c @@ -0,0 +1,512 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <arch/cpuid.h> +#include <cpu/x86/msr.h> +#include <soc/gpio.h> +#include <soc/ramstage.h> +#include "include/gpio.h" +#include "sch5555_ec.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +#define FORM_FACTOR_MICRO 0 +#define FORM_FACTOR_SFF 1 +// Probably DT and MT +#define FORM_FACTOR_UNK2 2 +#define FORM_FACTOR_UNK3 3 + +#define HWM_TAB_ADD_TEMP_TARGET 1 +#define HWM_TAB_PKG_POWER_ANY 0xffff + +struct hwm_tab_entry { + uint16_t addr; + uint8_t val; + uint8_t flags; + uint16_t pkg_power; +}; + +static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x01b, 0x0f, 0, 0xffff }, + { 0x057, 0xff, 0, 0xffff }, + { 0x059, 0xff, 0, 0xffff }, + { 0x05b, 0xff, 0, 0xffff }, + { 0x05d, 0xff, 0, 0xffff }, + { 0x05f, 0xff, 0, 0xffff }, + { 0x061, 0xff, 0, 0xffff }, + { 0x06e, 0x00, 0, 0xffff }, + { 0x06f, 0x03, 0, 0xffff }, + { 0x070, 0x03, 0, 0xffff }, + { 0x071, 0x02, 0, 0xffff }, + { 0x072, 0x02, 0, 0xffff }, + { 0x073, 0x01, 0, 0xffff }, + { 0x074, 0x06, 0, 0xffff }, + { 0x075, 0x07, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x80, 0, 0xffff }, + { 0x082, 0x80, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0xf1, 0, 0xffff }, + { 0x086, 0x88, 0, 0xffff }, + { 0x087, 0x61, 0, 0xffff }, + { 0x088, 0x08, 0, 0xffff }, + { 0x089, 0x00, 0, 0xffff }, + { 0x08a, 0x73, 0, 0xffff }, + { 0x08b, 0x73, 0, 0xffff }, + { 0x08c, 0x73, 0, 0xffff }, + { 0x090, 0x6d, 0, 0xffff }, + { 0x091, 0x7e, 0, 0xffff }, + { 0x092, 0x66, 0, 0xffff }, + { 0x093, 0xa4, 0, 0xffff }, + { 0x094, 0x7c, 0, 0xffff }, + { 0x095, 0xa4, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0xa4, 0, 0xffff }, + { 0x099, 0xa4, 0, 0xffff }, + { 0x09a, 0xa4, 0, 0xffff }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x2e, 0, 0xffff }, + { 0x0a1, 0x00, 0, 0xffff }, + { 0x0a2, 0x00, 0, 0xffff }, + { 0x0ae, 0xa4, 0, 0xffff }, + { 0x0af, 0xa4, 0, 0xffff }, + { 0x0b0, 0xa4, 0, 0xffff }, + { 0x0b1, 0xa4, 0, 0xffff }, + { 0x0b2, 0xa4, 0, 0xffff }, + { 0x0b3, 0xa4, 0, 0xffff }, + { 0x0b6, 0x00, 0, 0xffff }, + { 0x0b7, 0x00, 0, 0xffff }, + { 0x0d1, 0xff, 0, 0xffff }, + { 0x0d6, 0xff, 0, 0xffff }, + { 0x0db, 0xff, 0, 0xffff }, + { 0x0ea, 0x5c, 0, 0xffff }, + { 0x0eb, 0x5c, 0, 0xffff }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x184, 0xff, 0, 0xffff }, + { 0x186, 0xff, 0, 0xffff }, + { 0x1a1, 0xce, 0, 0xffff }, + { 0x1a2, 0x0c, 0, 0xffff }, + { 0x1a3, 0x0c, 0, 0xffff }, + { 0x1a6, 0x00, 0, 0xffff }, + { 0x1a7, 0x00, 0, 0xffff }, + { 0x1a8, 0xa4, 0, 0xffff }, + { 0x1a9, 0xa4, 0, 0xffff }, + { 0x1ab, 0x2d, 0, 0xffff }, + { 0x1ac, 0x2d, 0, 0xffff }, + { 0x1b1, 0x00, 0, 0xffff }, + { 0x1bb, 0x00, 0, 0xffff }, + { 0x1bc, 0x00, 0, 0xffff }, + { 0x1bd, 0x00, 0, 0xffff }, + { 0x1be, 0x01, 0, 0xffff }, + { 0x1bf, 0x01, 0, 0xffff }, + { 0x1c0, 0x01, 0, 0xffff }, + { 0x1c1, 0x01, 0, 0xffff }, + { 0x1c2, 0x01, 0, 0xffff }, + { 0x280, 0x00, 0, 0xffff }, + { 0x281, 0x00, 0, 0xffff }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff }, + { 0x040, 0x01, 0, 0xffff }, +}; + +static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x01b, 0x0f, 0, 0xffff }, + { 0x057, 0xff, 0, 0xffff }, + { 0x059, 0xff, 0, 0xffff }, + { 0x05b, 0xff, 0, 0xffff }, + { 0x05d, 0xff, 0, 0xffff }, + { 0x05f, 0xff, 0, 0xffff }, + { 0x061, 0xff, 0, 0xffff }, + { 0x06e, 0x00, 0, 0xffff }, + { 0x06f, 0x03, 0, 0xffff }, + { 0x070, 0x03, 0, 0xffff }, + { 0x071, 0x02, 0, 0xffff }, + { 0x072, 0x02, 0, 0xffff }, + { 0x073, 0x01, 0, 0xffff }, + { 0x074, 0x06, 0, 0xffff }, + { 0x075, 0x07, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x80, 0, 0xffff }, + { 0x082, 0x80, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0xf6, 0, 0xffff }, + { 0x086, 0x88, 0, 0xffff }, + { 0x087, 0x61, 0, 0xffff }, + { 0x088, 0x08, 0, 0xffff }, + { 0x089, 0x00, 0, 0xffff }, + { 0x08a, 0x73, 0, 0xffff }, + { 0x08b, 0x73, 0, 0xffff }, + { 0x08c, 0x73, 0, 0xffff }, + { 0x090, 0x6d, 0, 0xffff }, + { 0x091, 0x86, 0, 0xffff }, + { 0x092, 0x66, 0, 0xffff }, + { 0x093, 0xa4, 0, 0xffff }, + { 0x094, 0x7c, 0, 0xffff }, + { 0x095, 0xa4, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0xa4, 0, 0xffff }, + { 0x099, 0xa4, 0, 0xffff }, + { 0x09a, 0xa4, 0, 0xffff }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x2e, 0, 0xffff }, + { 0x0a1, 0x00, 0, 0xffff }, + { 0x0a2, 0x00, 0, 0xffff }, + { 0x0ae, 0xa4, 0, 0xffff }, + { 0x0af, 0xa4, 0, 0xffff }, + { 0x0b0, 0xa4, 0, 0xffff }, + { 0x0b1, 0xa4, 0, 0xffff }, + { 0x0b2, 0xa4, 0, 0xffff }, + { 0x0b3, 0xa4, 0, 0xffff }, + { 0x0b6, 0x00, 0, 0xffff }, + { 0x0b7, 0x00, 0, 0xffff }, + { 0x0d1, 0xff, 0, 0xffff }, + { 0x0d6, 0xff, 0, 0xffff }, + { 0x0db, 0xff, 0, 0xffff }, + { 0x0ea, 0x50, 0, 0xffff }, + { 0x0eb, 0x50, 0, 0xffff }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x184, 0xff, 0, 0xffff }, + { 0x186, 0xff, 0, 0xffff }, + { 0x1a1, 0xce, 0, 0xffff }, + { 0x1a2, 0x0c, 0, 0xffff }, + { 0x1a3, 0x0c, 0, 0xffff }, + { 0x1a6, 0x00, 0, 0xffff }, + { 0x1a7, 0x00, 0, 0xffff }, + { 0x1a8, 0xa4, 0, 0xffff }, + { 0x1a9, 0xa4, 0, 0xffff }, + { 0x1ab, 0x2d, 0, 0xffff }, + { 0x1ac, 0x2d, 0, 0xffff }, + { 0x1b1, 0x00, 0, 0xffff }, + { 0x1bb, 0x00, 0, 0xffff }, + { 0x1bc, 0x00, 0, 0xffff }, + { 0x1bd, 0x00, 0, 0xffff }, + { 0x1be, 0x01, 0, 0xffff }, + { 0x1bf, 0x01, 0, 0xffff }, + { 0x1c0, 0x01, 0, 0xffff }, + { 0x1c1, 0x01, 0, 0xffff }, + { 0x1c2, 0x01, 0, 0xffff }, + { 0x280, 0x00, 0, 0xffff }, + { 0x281, 0x00, 0, 0xffff }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff }, + { 0x040, 0x01, 0, 0xffff }, +}; + +static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x01b, 0x0f, 0, 0xffff }, + { 0x057, 0xff, 0, 0xffff }, + { 0x059, 0xff, 0, 0xffff }, + { 0x05b, 0xff, 0, 0xffff }, + { 0x05d, 0xff, 0, 0xffff }, + { 0x05f, 0xff, 0, 0xffff }, + { 0x061, 0xff, 0, 0xffff }, + { 0x06e, 0x01, 0, 0xffff }, + { 0x06f, 0x03, 0, 0xffff }, + { 0x070, 0x03, 0, 0xffff }, + { 0x071, 0x02, 0, 0xffff }, + { 0x072, 0x02, 0, 0xffff }, + { 0x073, 0x01, 0, 0xffff }, + { 0x074, 0x06, 0, 0xffff }, + { 0x075, 0x07, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x80, 0, 0xffff }, + { 0x082, 0x80, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0xfd, 0, 0xffff }, + { 0x086, 0x60, 0, 0xffff }, + { 0x087, 0x50, 0, 0xffff }, + { 0x088, 0x08, 0, 0xffff }, + { 0x089, 0x00, 0, 0xffff }, + { 0x08a, 0x73, 0, 0xffff }, + { 0x08b, 0x73, 0, 0xffff }, + { 0x08c, 0x73, 0, 0xffff }, + { 0x090, 0x6d, 0, 0xffff }, + { 0x091, 0x7a, 0, 0xffff }, + { 0x092, 0x6b, 0, 0xffff }, + { 0x093, 0xa4, 0, 0xffff }, + { 0x094, 0x78, 0, 0xffff }, + { 0x095, 0xa4, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0xa4, 0, 0xffff }, + { 0x099, 0xa4, 0, 0xffff }, + { 0x09a, 0xa4, 0, 0xffff }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x2e, 0, 0xffff }, + { 0x0a1, 0x00, 0, 0xffff }, + { 0x0a2, 0x00, 0, 0xffff }, + { 0x0ae, 0xa4, 0, 0xffff }, + { 0x0af, 0xa4, 0, 0xffff }, + { 0x0b0, 0xa4, 0, 0xffff }, + { 0x0b1, 0xa4, 0, 0xffff }, + { 0x0b2, 0xa4, 0, 0xffff }, + { 0x0b3, 0xa4, 0, 0xffff }, + { 0x0b6, 0x00, 0, 0xffff }, + { 0x0b7, 0x00, 0, 0xffff }, + { 0x0d1, 0xff, 0, 0xffff }, + { 0x0d6, 0xff, 0, 0xffff }, + { 0x0db, 0xff, 0, 0xffff }, + { 0x0ea, 0x64, 0, 0xffff }, + { 0x0eb, 0x64, 0, 0xffff }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x184, 0xff, 0, 0xffff }, + { 0x186, 0xff, 0, 0xffff }, + { 0x1a1, 0xce, 0, 0xffff }, + { 0x1a2, 0x0c, 0, 0xffff }, + { 0x1a3, 0x0c, 0, 0xffff }, + { 0x1a6, 0x00, 0, 0xffff }, + { 0x1a7, 0x00, 0, 0xffff }, + { 0x1a8, 0xa4, 0, 0xffff }, + { 0x1a9, 0xa4, 0, 0xffff }, + { 0x1ab, 0x2d, 0, 0xffff }, + { 0x1ac, 0x2d, 0, 0xffff }, + { 0x1b1, 0x00, 0, 0xffff }, + { 0x1bb, 0x00, 0, 0xffff }, + { 0x1bc, 0x00, 0, 0xffff }, + { 0x1bd, 0x00, 0, 0xffff }, + { 0x1be, 0x01, 0, 0xffff }, + { 0x1bf, 0x01, 0, 0xffff }, + { 0x1c0, 0x01, 0, 0xffff }, + { 0x1c1, 0x01, 0, 0xffff }, + { 0x1c2, 0x01, 0, 0xffff }, + { 0x280, 0x00, 0, 0xffff }, + { 0x281, 0x00, 0, 0xffff }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff }, + { 0x040, 0x01, 0, 0xffff }, +}; + +static const struct hwm_tab_entry HWM_TAB_SFF[] = { + { 0x019, 0x2f, 0, 0xffff }, + { 0x040, 0x01, 0, 0xffff }, + { 0x072, 0x03, 0, 0xffff }, + { 0x075, 0x06, 0, 0xffff }, + { 0x07c, 0x00, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x00, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0x59, 0, 0xffff }, + { 0x086, 0x6a, 0, 0xffff }, + { 0x087, 0xc0, 0, 0xffff }, + { 0x08a, 0x33, 0, 0xffff }, + { 0x090, 0x77, 0, 0xffff }, + { 0x091, 0x66, 0, 0xffff }, + { 0x092, 0x94, 0, 0xffff }, + { 0x093, 0x90, 0, 0xffff }, + { 0x094, 0x68, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0xa4, 0, 0xffff }, + { 0x099, 0xa4, 0, 0xffff }, + { 0x09a, 0xa4, 0, 0xffff }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x3e, 0, 0xffff }, + { 0x0ae, 0x86, 0, 0xffff }, + { 0x0af, 0x86, 0, 0xffff }, + { 0x0b0, 0xa4, 0, 0xffff }, + { 0x0b1, 0xa4, 0, 0xffff }, + { 0x0b2, 0x90, 0, 0xffff }, + { 0x0b6, 0x48, 0, 0xffff }, + { 0x0b7, 0x48, 0, 0xffff }, + { 0x0ea, 0x64, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x1b1, 0x48, 0, 0xffff }, + { 0x1b8, 0x00, 0, 0xffff }, + { 0x1be, 0x95, 0, 0xffff }, + { 0x1c1, 0x90, 0, 0xffff }, + { 0x1c6, 0x00, 0, 0xffff }, + { 0x1c9, 0x00, 0, 0xffff }, + { 0x280, 0x68, 0, 0xffff }, + { 0x281, 0x10, 0, 0xffff }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff} +}; + +static const struct hwm_tab_entry HWM_TAB_MT[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x00, 0, 0xffff }, + { 0x082, 0x80, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0xb9, 0, 0x0010 }, + { 0x086, 0xac, 0, 0x0010 }, + { 0x087, 0x87, 0, 0x0010 }, + { 0x08a, 0x51, 0, 0x0010 }, + { 0x08b, 0x39, 0, 0x0010 }, + { 0x090, 0x78, 0, 0xffff }, + { 0x091, 0x6a, 0, 0xffff }, + { 0x092, 0x8f, 0, 0xffff }, + { 0x094, 0x68, 0, 0xffff }, + { 0x095, 0x5b, 0, 0xffff }, + { 0x096, 0x92, 0, 0xffff }, + { 0x097, 0x86, 0, 0xffff }, + { 0x098, 0xa4, 0, 0xffff }, + { 0x09a, 0x8b, 0, 0xffff }, + { 0x0a0, 0x0a, 0, 0xffff }, + { 0x0a1, 0x26, 0, 0xffff }, + { 0x0a2, 0xd1, 0, 0xffff }, + { 0x0ae, 0x7c, 0, 0xffff }, + { 0x0af, 0x7c, 0, 0xffff }, + { 0x0b0, 0x9a, 0, 0xffff }, + { 0x0b3, 0x7c, 0, 0xffff }, + { 0x0b6, 0x08, 0, 0xffff }, + { 0x0b7, 0x00, 0, 0xffff }, + { 0x0ea, 0x64, 0, 0xffff }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x0fd, 0x01, 0, 0xffff }, + { 0x1a1, 0x99, 0, 0xffff }, + { 0x1a2, 0x00, 0, 0xffff }, + { 0x1a4, 0x00, 0, 0xffff }, + { 0x1b1, 0x00, 0, 0xffff }, + { 0x1be, 0x90, 0, 0xffff }, + { 0x280, 0xc4, 0, 0xffff }, + { 0x281, 0x09, 0, 0xffff }, + { 0x282, 0x0a, 0, 0xffff }, + { 0x283, 0x14, 0, 0xffff }, + { 0x284, 0x01, 0, 0xffff }, + { 0x285, 0x01, 0, 0xffff }, + { 0x288, 0x94, 0, 0xffff }, + { 0x289, 0x11, 0, 0xffff }, + { 0x28a, 0x0a, 0, 0xffff }, + { 0x28b, 0x14, 0, 0xffff }, + { 0x28c, 0x01, 0, 0xffff }, + { 0x28d, 0x01, 0, 0xffff }, + { 0x294, 0x24, 0, 0xffff }, +}; + +static uint8_t get_temp_target(void) +{ + uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; + if (!val) + val = 20; + return 0x95 - val; +} + +static uint16_t get_pkg_power(void) +{ + const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff; + const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf); + if (pkg_power / power_unit > 65) + return 32; + else + return 16; +} + +static uint8_t get_core_cnt(void) +{ + // Intel describes this CPUID field as: + // > Maximum number of addressable IDs for processor cores in the physical package + if (cpuid(0).eax >= 4) + return cpuid_ext(4, 0).eax >> 26; + return 0; +} + +static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size) +{ + uint8_t temp_target = get_temp_target(); + uint16_t pkg_power = get_pkg_power(); + + printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); + printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); + + for (size_t i = 0; i < size; ++i) { + // Skip entry if it doesn't apply for this package power + if (arr[i].pkg_power != pkg_power && + arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) + continue; + + uint8_t val = arr[i].val; + + // Add temp target to value if requested (current tables never do) + if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) + val += temp_target; + + // Perform write + sch5555_mbox_write(1, arr[i].addr, val); + } +} + +static void sch5555_ec_hwm_init(void *arg) +{ + uint8_t form_fac_id, saved_2fc, core_cnt; + + printk(BIOS_DEBUG, "OptiPlex 3050 late HWM init\n"); + + form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1; + printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id); + + saved_2fc = sch5555_mbox_read(1, 0x2fc); + sch5555_mbox_write(1, 0x2fc, 0xa0); + sch5555_mbox_write(1, 0x2fd, 0x32); + + switch (form_fac_id) { + case FORM_FACTOR_MICRO: + // CPU stepping <= 3 + if ((cpuid(1).eax & 0xf) <= 3) + apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING)); + // Tjunction == 80 + else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80) + apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80)); + else + apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE)); + break; + case FORM_FACTOR_SFF: + apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF)); + break; + default: + apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT)); + break; + } + + core_cnt = get_core_cnt(); + printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt); + if (core_cnt > 2) { + sch5555_mbox_write(1, 0x9e, 0x30); + sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); + } + + sch5555_mbox_write(1, 0x2fc, saved_2fc); + sch5555_mbox_read(1, 0xb8); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/optiplex_3050/romstage.c b/src/mainboard/dell/optiplex_3050/romstage.c new file mode 100644 index 0000000..501b254 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/romstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + struct spd_block blk = { .addr_map = { 0x50, 0x52, } }; + get_spd_smbus(&blk); + dump_spd_info(&blk); + + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + mem_cfg->DqPinsInterleaved = true; + mem_cfg->CaVrefConfig = 2; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.c b/src/mainboard/dell/optiplex_3050/sch5555_ec.c new file mode 100644 index 0000000..1df5026 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <superio/smsc/sch555x/sch555x.h> +#include "sch5555_ec.h" + +uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) +{ + // clear ec-to-host mailbox + uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); + outb(tmp, SCH555x_EMI_IOBASE + 1); + + // send address + outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); + outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); + + outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); + outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); + + // send message to ec + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack + for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; + + // read result + outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); + return inb(SCH555x_EMI_IOBASE + 4); +} + +void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) +{ + // clear ec-to-host mailbox + uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); + outb(tmp, SCH555x_EMI_IOBASE + 1); + + // send address and value + outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); + outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); + + outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); + outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); + + // send message to ec + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack + for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; +} diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.h b/src/mainboard/dell/optiplex_3050/sch5555_ec.h new file mode 100644 index 0000000..9d262d5 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/sch5555_ec.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SCH5555_EC_H__ +#define __SCH5555_EC_H__ + +uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); + +void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 20 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routed
by Lean Sheng Tan (Code Review) 07 Nov '24

07 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82253?usp=email ) Change subject: soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routed ...................................................................... soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routed acpigen_write_PRT_pre_routed writes _PRT covering all direct subordinate child devices based on interrupt line/pin info from their PCI configuration spaces. It is required that IRQ routing and PCI configuration space update to be done ahead of time. TEST=Build and boot on intel/archercity CRB Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82253 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 2 files changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Lean Sheng Tan: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 33db9e6..8d74240 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -8,6 +8,7 @@ #include <soc/chip_common.h> #include <soc/pci_devs.h> #include <soc/util.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #include <stdint.h> #include <stdio.h> #include <stdlib.h> @@ -193,3 +194,43 @@ acpigen_pop_len(); acpigen_pop_len(); } + +void acpigen_write_PRT_pre_routed(const struct device *br) +{ + int dev_num = 0; + uint32_t routed_dev_bitmap = 0; + char *entry_count; + + if (!is_pci_bridge(br)) + return; + + const char *acpi_scope = acpi_device_path(br); + if (!acpi_scope) + return; + + acpigen_write_scope(acpi_scope); + acpigen_write_name("_PRT"); + entry_count = acpigen_write_package(0); + + struct device *dev = NULL; + while ((dev = dev_bus_each_child(br->downstream, dev))) { + if (!is_pci(dev)) + continue; + dev_num = PCI_SLOT(dev->path.pci.devfn); + if (routed_dev_bitmap & (1 << dev_num)) + continue; + + uint8_t int_line = pci_read_config8(dev, PCI_INTERRUPT_LINE); + uint8_t int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if ((int_pin > PCI_INT_MAX) || (int_pin < PCI_INT_A)) + continue; + + acpigen_write_PRT_GSI_entry(dev_num, int_pin - PCI_INT_A, int_line); + + (*entry_count)++; + routed_dev_bitmap |= (1 << dev_num); + } + + acpigen_pop_len(); + acpigen_pop_len(); +} diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index fd693c8..0618147 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -39,5 +39,6 @@ const bool is_cxl_domain, const uint32_t granted_cxl_features); void acpigen_write_pci_root_port(const struct device *rp); +void acpigen_write_PRT_pre_routed(const struct device *br); #endif /* _SOC_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c Gerrit-Change-Number: 82253 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2024