coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Angel Pons (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Lean Sheng Tan, Paul Menzel, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 29: Code-Review+1 (14 comments) Patchset: PS19: > Any response @th3fanbus@gmail. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/83318/comment/1ee7e1d9_05b79b4a?us… : PS19, Line 7: Fixup > The verb is spelled with a space: Fix up. Acknowledged https://review.coreboot.org/c/coreboot/+/83318/comment/39dbc51f_56db864d?us… : PS19, Line 12: default > by default Acknowledged https://review.coreboot.org/c/coreboot/+/83318/comment/491560d3_80637428?us… : PS19, Line 13: add > add*s* Acknowledged https://review.coreboot.org/c/coreboot/+/83318/comment/4a46eb2c_b4894b4c?us… : PS19, Line 13: This patch add > Add … Acknowledged Commit Message: https://review.coreboot.org/c/coreboot/+/83318/comment/08a08881_26b9cd13?us… : PS29, Line 9: Intel server process has Intel server processors have File src/soc/intel/common/block/systemagent-server/Kconfig: https://review.coreboot.org/c/coreboot/+/83318/comment/44fa9194_42c0fb70?us… : PS26, Line 26: default 0x100000 > to clean up? Gone File src/soc/intel/common/block/systemagent-server/common.c: https://review.coreboot.org/c/coreboot/+/83318/comment/2ba17a5f_113aa758?us… : PS29, Line 8: pci_moving_config32 I thought this existed in common code, any reason not to use it? File src/soc/intel/common/block/systemagent-server/memmap.c: https://review.coreboot.org/c/coreboot/+/83318/comment/fdfac7e2_d7841e61?us… : PS29, Line 25: die("NO_FSP_TEMP_RAM_EXIT is not supportted currently!"); This could be implemented as a static assertion to cause a build-time error. If I didn't mess up the syntax: ```suggestion _Static_assert(!NO_FSP_TEMP_RAM_EXIT, "NO_FSP_TEMP_RAM_EXIT is not supportted currently!"); ``` File src/soc/intel/common/block/systemagent/Kconfig: https://review.coreboot.org/c/coreboot/+/83318/comment/bbd53e6d_ca67b042?us… : PS19, Line 58: SA_FIXUP_ADDRESS > I do not have a suggestion, but could address be more specified, and maybe also prefix with `INTEL_S […] Acknowledged https://review.coreboot.org/c/coreboot/+/83318/comment/c7f83d8b_bf9b0240?us… : PS19, Line 62: fixup > fix up Acknowledged https://review.coreboot.org/c/coreboot/+/83318/comment/dc3d43ae_0c6e5c3b?us… : PS19, Line 62: Specify if SoC should fixup the address value in registers to meet coreboot : usage requirements. : > It’d be great if you elaborated or referenced the explanation in the header file. Acknowledged File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/83318/comment/4ca13ff3_25ed8863?us… : PS19, Line 137: else { : /* All regions concerned for have 1 MiB alignment. */ : return ALIGN_DOWN(value, 1*MiB); : } > Else branch not needed, and could just return. But no preference. Acknowledged https://review.coreboot.org/c/coreboot/+/83318/comment/eedc13e0_a01a98b7?us… : PS19, Line 157: value > Why introduce the variable? Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 29 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 07 Nov 2024 07:40:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>

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[M] Change in coreboot[main]: mb/asus/p5qc: Add ASUS P5Q-E as a variant
by Paul Menzel (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Name of user not set #1004033, Stefan Ott. Paul Menzel has posted comments on this change by Name of user not set #1004033. ( https://review.coreboot.org/c/coreboot/+/60011?usp=email ) Change subject: mb/asus/p5qc: Add ASUS P5Q-E as a variant ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60011/comment/a8f1fe1f_d5b84c05?us… : PS2, Line 2: yhaenggi It’d be great if you spelled it like on your passport. Maybe (no idea what the official spelling is): $ git config --global user.name "Yhaeng Gi" $ git commit --amend --author="Yhaeng Gi <yhaenggi-git-public(a)darkgamex.ch>" https://review.coreboot.org/c/coreboot/+/60011/comment/65127a1a_2051eac7?us… : PS2, Line 4: yhaenggi Ditto. https://review.coreboot.org/c/coreboot/+/60011/comment/0f408050_c877e2fb?us… : PS2, Line 8: It’d great if you elaborate, what you tested, and what works, and what does not. -- To view, visit https://review.coreboot.org/c/coreboot/+/60011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e8415fe88a421c529308279381aa62e2160e171 Gerrit-Change-Number: 60011 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1004033 Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Name of user not set #1004033 Gerrit-Comment-Date: Thu, 07 Nov 2024 07:39:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add Elan touchscreen
by Paul Menzel (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Paul Menzel has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85015?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... Patch Set 6: Code-Review+1 (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85015/comment/cb4f637d_f8697203?us… : PS6, Line 7: Add Elan touchscreen … to devicetree https://review.coreboot.org/c/coreboot/+/85015/comment/66d1e607_d78eaee0?us… : PS6, Line 7: Elan ELAN https://review.coreboot.org/c/coreboot/+/85015/comment/f551716b_d373d395?us… : PS6, Line 9: Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. Please wrap the line after 72 characters. https://review.coreboot.org/c/coreboot/+/85015/comment/5a7df8bd_a2499049?us… : PS6, Line 13: touchpanel function is normal What commands did you run? xev? Any log line, one could check? File src/mainboard/google/brya/variants/rull/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85015/comment/e3e1d1a3_a33e79ce?us… : PS6, Line 232: register "generic.stop_delay_ms" = "150" Is 150 ms mentioned in the schematics or some datasheet? -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 6 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 07:35:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Angel Pons (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Máté Kukri, Paul Menzel. Angel Pons has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... Patch Set 19: Code-Review+2 (1 comment) File src/mainboard/dell/optiplex_3050/ramstage.c: https://review.coreboot.org/c/coreboot/+/82053/comment/ecb88b70_cefe77b7?us… : PS17, Line 18: // NOTE: one of these is MT, but 2 and 3 both get the same table anyways > Probably DT and MT Wasn't meant to be used verbatim, but no big deal -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 19 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 07:35:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/google/rex/var/kanix: Add inital overridetree settings
by Tyler Wang (Code Review) 07 Nov '24

07 Nov '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85021?usp=email ) Change subject: mb/google/rex/var/kanix: Add inital overridetree settings ...................................................................... mb/google/rex/var/kanix: Add inital overridetree settings Update inital overridetree settings, it basically copied from karis. It include: 1. USB related settings 2. Display Port Configuration 3. DPTF settings 4. PCIE settings for NVME 5. PCIE settings for WLAN card 6. Settings of ELAN9004 7. Settings of ELAN and PIXA touchpad 8. Settings of MIPI camera HI556 BUG=b:368501705 TEST=emerge-rex coreboot pass Change-Id: I468ca388f495b2e527841145f8162b21074058cc --- M src/mainboard/google/rex/variants/kanix/overridetree.cb 1 file changed, 513 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/85021/1 diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 6c284b3..07cf2ce 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -1,6 +1,517 @@ chip soc/intel/meteorlake - device domain 0 on - end + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1 + + # Enable eDP in Port A + register "ddi_port_A_config" = "1" + # Enable HDMI in Port B + register "ddi_port_B_config" = "0" + + # Enable Display Port Configuration + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD, + [DDI_PORT_4] = DDI_ENABLE_HPD, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio and WFC | + #| I2C1 | Touchscreen | + #| I2C3 | Touchpad | + #| I2C4 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | UFC, SAR1, SAR2, HPS | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 400, + .fall_time_ns = 350, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 900, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) unused + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C1 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 50), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 57000, + .max_power = 57000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie_rp10 on + # Enable SSD Card PCIE 10 using clk 8 + register "pcie_rp[PCIE_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "8" + device generic 0 on end + end + end # PCIE10 SSD card + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp2 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + device ref ipu on end + device ref i2c0 on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM0"" + register "cio2_prt[0]" = "4" + device generic 0 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C01)" + register "generic.reset_delay_ms" = "150" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C00)" + register "generic.enable_delay_ms" = "6" + register "generic.enable_off_delay_ms" = "30" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B00_IRQ)" + register "wake" = "GPE0_DW0_00" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2305"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B00_IRQ)" + register "generic.wake" = "GPE0_DW0_00" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 68 on end + end + end + device ref i2c4 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""INT3537"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Hi-556 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "437 * MHz" + register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_A11" #EN_UCAM_SENR_PWR + register "gpio_panel.gpio[1].gpio_num" = "GPP_B09" #EN_FCAM_PWR + register "gpio_panel.gpio[2].gpio_num" = "GPP_V23" #UCAM_RST_L + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 20 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""ST M24C64X"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c64"" + + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "1" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_B09" #EN_FCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 50 on end + end + end #I2C5 + device ref pcie_rp5 on + # Enable WLAN Card PCIE 5 using clk 5 + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_09" + register "add_acpi_dma_property" = "true" + use usb2_port10 as bluetooth_companion + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E22)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F08)" + register "srcclk_pin" = "5" + device generic 0 on end + end + end #PCIE5 WLAN card + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)" + register "wake" = "GPE0_DW1_10" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "enable_delay_ms" = "3" + device spi 0 on end + end # FPMCU + end + device ref soc_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468ca388f495b2e527841145f8162b21074058cc Gerrit-Change-Number: 85021 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/intel/coffeelake_rvp/cml_u: Correct number of jacks in hda_verb.c
by Paul Menzel (Code Review) 07 Nov '24

07 Nov '24

Paul Menzel has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/84487?usp=email ) Change subject: mb/intel/coffeelake_rvp/cml_u: Correct number of jacks in hda_verb.c ...................................................................... Patch Set 5: (2 comments) Patchset: PS5: The value was updated from 35 to 161. Commit Message: https://review.coreboot.org/c/coreboot/+/84487/comment/cd52b7a5_fac2bfc6?us… : PS1, Line 10: > I have added both explanations. Therefore, I will be marking this comment as resolved. […] Sorry, thank you, and feel always free to mark my comments as resolved. -- To view, visit https://review.coreboot.org/c/coreboot/+/84487?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8df44e056bc841bfb344749ba214e6fb71a1955b Gerrit-Change-Number: 84487 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 07:12:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add Elan touchscreen
by Eric Lai (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Eric Lai has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85015?usp=email ) Change subject: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 6 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 05:48:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add Elan touchscreen
by Rui Zhou (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Rui Zhou has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85015?usp=email ) Change subject: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/variants/rull/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85015/comment/c0abd989_af439f0a?us… : PS3, Line 232: 280 > please check this value can be shorten or not. I referred to all the coreboot commits. Regarding the elan touchscreen of "hid=9004", the ```stop_delay_ms``` is set to 280 or 150. Here I changed it to 150ms. If it affects the function or suspend/resume, I will readjust it later. -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 6 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 05:45:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add Elan touchscreen
by Rui Zhou (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85015?usp=email to look at the new patch set (#6). Change subject: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... mb/google/nissa/var/rull: Add Elan touchscreen Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. BUG=b:374629673 BRANCH=None TEST=Local build successfully and touchpanel function is normal Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85015/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 6 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen
by Rui Zhou (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85015?usp=email to look at the new patch set (#5). Change subject: UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. BUG=b:374629673 BRANCH=None TEST=Local build successfully and touchpanel function is normal Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85015/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 5 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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coreboot-gerrit November 2024