coreboot-gerrit November 2024

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[S] Change in coreboot[main]: soc/mediatek/common: Use write32p and read32p for tracker
by Yu-Ping Wu (Code Review) 07 Nov '24

07 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84959?usp=email ) Change subject: soc/mediatek/common: Use write32p and read32p for tracker ...................................................................... soc/mediatek/common: Use write32p and read32p for tracker TEST=emerge-geralt coreboot Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84959 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v2.c 2 files changed, 10 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 1341d5a..be83999 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -21,7 +21,7 @@ for (j = 0; j < TRACKER_NUM; j++) { tra = &tracker_data[j]; - if (!(read32((void *)(tra->base_addr)) & tra->timeout)) + if (!(read32p(tra->base_addr) & tra->timeout)) continue; printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); @@ -29,7 +29,7 @@ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offsets[k] + i * 4; - printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); + printk(BIOS_INFO, "%#lx:%#x,", reg, read32p(reg)); if (i % 4 == 3 || i == size - 1) printk(BIOS_INFO, "\n"); diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c index 0127916..0b41605 100644 --- a/src/soc/mediatek/common/tracker_v2.c +++ b/src/soc/mediatek/common/tracker_v2.c @@ -61,16 +61,16 @@ * peri tracker clock: 78MHz */ val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0, val); + write32p(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1, val); val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0, val); + write32p(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1, val); /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1, 1 << BUS_TRACE_EN); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2, 1 << BUS_TRACE_EN); /* * Enable infra/peri tracker. @@ -81,6 +81,6 @@ * bit[14] - BUS_OT_WEN_CTRL */ val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1, val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2, val); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Gerrit-Change-Number: 84959 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Refactor `struct tracker`
by Yu-Ping Wu (Code Review) 07 Nov '24

07 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84958?usp=email ) Change subject: soc/mediatek/common: Refactor `struct tracker` ...................................................................... soc/mediatek/common: Refactor `struct tracker` Rather than using a static array size for the `offset` variable, use a pointer named `offsets` that points to a dynamically allocated array. A separate variable called `offset_size` stores the size of this array. TEST=emerge-corsola coreboot && emerge-geralt coreboot Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84958 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/tracker_common.h M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v1.c M src/soc/mediatek/common/tracker_v2.c 4 files changed, 20 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/tracker_common.h b/src/soc/mediatek/common/include/soc/tracker_common.h index 0269457..f1cdb63 100644 --- a/src/soc/mediatek/common/include/soc/tracker_common.h +++ b/src/soc/mediatek/common/include/soc/tracker_common.h @@ -16,7 +16,8 @@ uintptr_t base_addr; u32 timeout; u32 entry; - u32 offset[2]; + const u32 *offsets; + u32 offsets_size; const char *str; }; diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 3485449..1341d5a 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -25,10 +25,10 @@ continue; printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); - for (k = 0; k < 2; k++) { + for (k = 0; k < tra->offsets_size; k++) { size = 2 * tra->entry; for (i = 0; i < size; i++) { - reg = tra->base_addr + tra->offset[k] + i * 4; + reg = tra->base_addr + tra->offsets[k] + i * 4; printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); if (i % 4 == 3 || i == size - 1) diff --git a/src/soc/mediatek/common/tracker_v1.c b/src/soc/mediatek/common/tracker_v1.c index 746951b..00e5bc8 100644 --- a/src/soc/mediatek/common/tracker_v1.c +++ b/src/soc/mediatek/common/tracker_v1.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <soc/addressmap.h> #include <soc/tracker.h> #include <soc/tracker_common.h> @@ -9,13 +10,16 @@ * offset[0] dump from offset 0x100 ~ 0x13C. * offset[1] dump from offset 0x200 ~ 0x23C. */ + +static const u32 offsets[] = { AR_TRACK_OFFSET, AW_TRACK_OFFSET }; + struct tracker tracker_data[TRACKER_NUM] = { [TRACKER_SYSTRACKER] = { .base_addr = DBG_TRACKER_BASE, .timeout = BUS_DBG_CON_TIMEOUT, .entry = SYS_TRACK_ENTRY, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "systracker", }, }; diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c index fecde16..0127916 100644 --- a/src/soc/mediatek/common/tracker_v2.c +++ b/src/soc/mediatek/common/tracker_v2.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/tracker.h> @@ -18,29 +19,32 @@ * offset[0] dump from offset 0x100 ~ 0x2F8 * offset[1] dump from offset 0x300 ~ 0x4FC */ + +static const u32 offsets[] = { AR_TRACK_OFFSET, AW_TRACK_OFFSET }; + struct tracker tracker_data[TRACKER_NUM] = { [TRACKER_SYSTRACKER] = { .base_addr = DBG_TRACKER_BASE, .timeout = BUS_DBG_CON_TIMEOUT, .entry = SYS_TRACK_ENTRY, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "systracker", }, [TRACKER_INFRATRACKER] = { .base_addr = INFRA_TRACKER_BASE, .timeout = BUSTRACKER_TIMEOUT, .entry = INFRA_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "infra_tracker", }, [TRACKER_PERISYSTRACKER] = { .base_addr = PERI_TRACKER_BASE, .timeout = BUSTRACKER_TIMEOUT, .entry = PERI_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "peri_tracker", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/84958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Gerrit-Change-Number: 84958 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add ELAN touchscreen to devicetree
by Rui Zhou (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Rui Zhou has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85015?usp=email ) Change subject: mb/google/nissa/var/rull: Add ELAN touchscreen to devicetree ...................................................................... Patch Set 7: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85015/comment/0ea6daa5_2c394c60?us… : PS6, Line 7: Elan > ELAN Done https://review.coreboot.org/c/coreboot/+/85015/comment/4c6f386c_6cf60816?us… : PS6, Line 7: Add Elan touchscreen > … to devicetree Done https://review.coreboot.org/c/coreboot/+/85015/comment/f89817f9_bcfed1f3?us… : PS6, Line 9: Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. > Please wrap the line after 72 characters. Done https://review.coreboot.org/c/coreboot/+/85015/comment/eba010af_5038a87b?us… : PS6, Line 13: touchpanel function is normal > What commands did you run? xev? Any log line, one could check? Done File src/mainboard/google/brya/variants/rull/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85015/comment/e80cdf18_747ee9c3?us… : PS6, Line 232: register "generic.stop_delay_ms" = "150" > Is 150 ms mentioned in the schematics or some datasheet? Refer to the parameters submitted by the same touch IC, I asked the vendor and they also gave similar reference values. -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 7 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 09:01:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add ELAN touchscreen to devicetree
by Rui Zhou (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85015?usp=email to look at the new patch set (#7). Change subject: mb/google/nissa/var/rull: Add ELAN touchscreen to devicetree ...................................................................... mb/google/nissa/var/rull: Add ELAN touchscreen to devicetree Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. touchpanel function is normal and 'evtest' command displays the touch point Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85015/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 7 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Máté Kukri (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Paul Menzel. Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... Patch Set 19: (1 comment) File src/mainboard/dell/optiplex_3050/ramstage.c: https://review.coreboot.org/c/coreboot/+/82053/comment/84729cf6_1834962c?us… : PS17, Line 18: // NOTE: one of these is MT, but 2 and 3 both get the same table anyways > Wasn't meant to be used verbatim, but no big deal Woops 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 19 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 08:45:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add support for USB A1 port
by Tyler Wang (Code Review) 07 Nov '24

07 Nov '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85022?usp=email ) Change subject: mb/google/rex/var/kanix: Add support for USB A1 port ...................................................................... mb/google/rex/var/kanix: Add support for USB A1 port BUG=b:366291025 TEST=emerge-rex coreboot pass Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 --- M src/mainboard/google/rex/variants/kanix/overridetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/85022/1 diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index c1d026b..4e3ae1c 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -2,10 +2,12 @@ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port A1 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1 @@ -289,6 +291,13 @@ device ref usb2_port2 on end end chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" @@ -308,6 +317,13 @@ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 Gerrit-Change-Number: 85022 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 49: (2 comments) File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/b9f53e5e_e8c065df?us… : PS28, Line 418: PCI_SLOT(dev->path.pci.devfn) >= PCI_SLOT(PCH_DEVFN_QAT_1_7) && > Can we have a checker, e.g. […] Done File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/ebe3a8d7_11917591?us… : PS15, Line 17: *size = CONFIG_ECAM_MMCONF_LENGTH; > CONFIG_ECAM_MMCONF_LENGTH => should be aligned with the probed value The PCIe MMCFG limit register holds a wrong value, so using the Kconfig value as a workaround. -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 49 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 08:28:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Angel Pons (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Shuo Liu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 49: Code-Review+1 (1 comment) File src/soc/intel/snowridge/acpi/pcie.asl: https://review.coreboot.org/c/coreboot/+/83321/comment/38014830_787ea50a?us… : PS28, Line 5: /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ : Name (IQAA, Package() { : Package() { 0x0000ffff, 0, 0, 16 }, : Package() { 0x0000ffff, 1, 0, 17 }, : Package() { 0x0000ffff, 2, 0, 18 }, : Package() { 0x0000ffff, 3, 0, 19 } }) : Name (IQAP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKA, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKB, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKC, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKD, 0 } }) : : /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ : Name (IQBA, Package() { : Package() { 0x0000ffff, 0, 0, 17 }, : Package() { 0x0000ffff, 1, 0, 18 }, : Package() { 0x0000ffff, 2, 0, 19 }, : Package() { 0x0000ffff, 3, 0, 16 } }) : Name (IQBP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKB, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKC, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKD, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKA, 0 } }) : : /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ : Name (IQCA, Package() { : Package() { 0x0000ffff, 0, 0, 18 }, : Package() { 0x0000ffff, 1, 0, 19 }, : Package() { 0x0000ffff, 2, 0, 16 }, : Package() { 0x0000ffff, 3, 0, 17 } }) : Name (IQCP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKC, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKD, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKA, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKB, 0 } }) : : /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ : Name (IQDA, Package() { : Package() { 0x0000ffff, 0, 0, 19 }, : Package() { 0x0000ffff, 1, 0, 16 }, : Package() { 0x0000ffff, 2, 0, 17 }, : Package() { 0x0000ffff, 3, 0, 18 } }) : Name (IQDP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKD, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKA, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKB, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKC, 0 } }) : : /* Interrupt Map INTA->INTE, INTB->INTF, INTC->INTG, INTD->INTH */ : Name (IQEA, Package() { : Package() { 0x0000ffff, 0, 0, 20 }, : Package() { 0x0000ffff, 1, 0, 21 }, : Package() { 0x0000ffff, 2, 0, 22 }, : Package() { 0x0000ffff, 3, 0, 23 } }) : Name (IQEP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKE, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKF, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKG, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKH, 0 } }) : : /* Interrupt Map INTA->INTF, INTB->INTG, INTC->INTH, INTD->INTE */ : Name (IQFA, Package() { : Package() { 0x0000ffff, 0, 0, 21 }, : Package() { 0x0000ffff, 1, 0, 22 }, : Package() { 0x0000ffff, 2, 0, 23 }, : Package() { 0x0000ffff, 3, 0, 20 } }) : Name (IQFP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKF, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKG, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKH, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKE, 0 } }) : : /* Interrupt Map INTA->INTG, INTB->INTH, INTC->INTE, INTD->INTF */ : Name (IQGA, Package() { : Package() { 0x0000ffff, 0, 0, 22 }, : Package() { 0x0000ffff, 1, 0, 23 }, : Package() { 0x0000ffff, 2, 0, 20 }, : Package() { 0x0000ffff, 3, 0, 21 } }) : Name (IQGP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKG, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKH, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKE, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKF, 0 } }) : : /* Interrupt Map INTA->INTH, INTB->INTE, INTC->INTF, INTD->INTG */ : Name (IQHA, Package() { : Package() { 0x0000ffff, 0, 0, 23 }, : Package() { 0x0000ffff, 1, 0, 20 }, : Package() { 0x0000ffff, 2, 0, 21 }, : Package() { 0x0000ffff, 3, 0, 22 } }) : Name (IQHP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKH, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKE, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKF, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKG, 0 } }) > Why is it sad? Looks fine to me -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 49 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 08:05:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Paul Menzel (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Paul Menzel has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 49: (1 comment) File src/soc/intel/snowridge/acpi/pcie.asl: https://review.coreboot.org/c/coreboot/+/83321/comment/8e69f11a_00de1bfc?us… : PS28, Line 5: /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ : Name (IQAA, Package() { : Package() { 0x0000ffff, 0, 0, 16 }, : Package() { 0x0000ffff, 1, 0, 17 }, : Package() { 0x0000ffff, 2, 0, 18 }, : Package() { 0x0000ffff, 3, 0, 19 } }) : Name (IQAP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKA, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKB, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKC, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKD, 0 } }) : : /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ : Name (IQBA, Package() { : Package() { 0x0000ffff, 0, 0, 17 }, : Package() { 0x0000ffff, 1, 0, 18 }, : Package() { 0x0000ffff, 2, 0, 19 }, : Package() { 0x0000ffff, 3, 0, 16 } }) : Name (IQBP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKB, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKC, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKD, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKA, 0 } }) : : /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ : Name (IQCA, Package() { : Package() { 0x0000ffff, 0, 0, 18 }, : Package() { 0x0000ffff, 1, 0, 19 }, : Package() { 0x0000ffff, 2, 0, 16 }, : Package() { 0x0000ffff, 3, 0, 17 } }) : Name (IQCP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKC, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKD, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKA, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKB, 0 } }) : : /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ : Name (IQDA, Package() { : Package() { 0x0000ffff, 0, 0, 19 }, : Package() { 0x0000ffff, 1, 0, 16 }, : Package() { 0x0000ffff, 2, 0, 17 }, : Package() { 0x0000ffff, 3, 0, 18 } }) : Name (IQDP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKD, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKA, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKB, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKC, 0 } }) : : /* Interrupt Map INTA->INTE, INTB->INTF, INTC->INTG, INTD->INTH */ : Name (IQEA, Package() { : Package() { 0x0000ffff, 0, 0, 20 }, : Package() { 0x0000ffff, 1, 0, 21 }, : Package() { 0x0000ffff, 2, 0, 22 }, : Package() { 0x0000ffff, 3, 0, 23 } }) : Name (IQEP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKE, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKF, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKG, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKH, 0 } }) : : /* Interrupt Map INTA->INTF, INTB->INTG, INTC->INTH, INTD->INTE */ : Name (IQFA, Package() { : Package() { 0x0000ffff, 0, 0, 21 }, : Package() { 0x0000ffff, 1, 0, 22 }, : Package() { 0x0000ffff, 2, 0, 23 }, : Package() { 0x0000ffff, 3, 0, 20 } }) : Name (IQFP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKF, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKG, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKH, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKE, 0 } }) : : /* Interrupt Map INTA->INTG, INTB->INTH, INTC->INTE, INTD->INTF */ : Name (IQGA, Package() { : Package() { 0x0000ffff, 0, 0, 22 }, : Package() { 0x0000ffff, 1, 0, 23 }, : Package() { 0x0000ffff, 2, 0, 20 }, : Package() { 0x0000ffff, 3, 0, 21 } }) : Name (IQGP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKG, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKH, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKE, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKF, 0 } }) : : /* Interrupt Map INTA->INTH, INTB->INTE, INTC->INTF, INTD->INTG */ : Name (IQHA, Package() { : Package() { 0x0000ffff, 0, 0, 23 }, : Package() { 0x0000ffff, 1, 0, 20 }, : Package() { 0x0000ffff, 2, 0, 21 }, : Package() { 0x0000ffff, 3, 0, 22 } }) : Name (IQHP, Package() { : Package() { 0x0000ffff, 0, \_SB.LNKH, 0 }, : Package() { 0x0000ffff, 1, \_SB.LNKE, 0 }, : Package() { 0x0000ffff, 2, \_SB.LNKF, 0 }, : Package() { 0x0000ffff, 3, \_SB.LNKG, 0 } }) > Very sad. Why is it sad? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 49 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 07:44:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add printk log missing carriage return character
by Paul Menzel (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Jérémy Compostella. Paul Menzel has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85020?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/fatcat: Add printk log missing carriage return character ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/85020/comment/30bd84ee_8f42d162?us… : PS1, Line 459: Existing Could you also sent a follow-up to correct this to *Exiting* (no s)? -- To view, visit https://review.coreboot.org/c/coreboot/+/85020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Gerrit-Change-Number: 85020 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 07:42:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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