coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/fatcat: Add printk log missing carriage return character
by Pranava Y N (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Jérémy Compostella. Pranava Y N has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85020?usp=email ) Change subject: mb/google/fatcat: Add printk log missing carriage return character ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Gerrit-Change-Number: 85020 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 04:27:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/asus/p5qc: Add ASUS P5Q-E as a variant
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Name of user not set #1004033, Paul Menzel, Stefan Ott. Felix Singer has posted comments on this change by Name of user not set #1004033. ( https://review.coreboot.org/c/coreboot/+/60011?usp=email ) Change subject: mb/asus/p5qc: Add ASUS P5Q-E as a variant ...................................................................... Patch Set 2: (1 comment) File src/mainboard/asus/p5qc/variants/p5q_e/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60011/comment/10cc2e27_3244b220?us… : PS2, Line 4: device cpu_cluster 0 on # APIC cluster : chip cpu/intel/socket_LGA775 : device lapic 0 on end : end : chip cpu/intel/model_1067x # CPU : device lapic 0xACAC off end : end : end Remove this -- To view, visit https://review.coreboot.org/c/coreboot/+/60011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e8415fe88a421c529308279381aa62e2160e171 Gerrit-Change-Number: 60011 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1004033 Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Name of user not set #1004033 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 04:23:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: Documentation: Update Protectli fw6b documentations
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63016?usp=email ) Change subject: Documentation: Update Protectli fw6b documentations ...................................................................... Documentation: Update Protectli fw6b documentations Update documentations: - ME cleaner has been tested on the fw6b. - More observations on the stock firmware is documented. - Compatible boards are listed along with the original manufacturer. Signed-off-by: Xue Yao <xueyao(a)xyte.ch> Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63016 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/mainboard/protectli/fw6.md 1 file changed, 24 insertions(+), 3 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/Documentation/mainboard/protectli/fw6.md b/Documentation/mainboard/protectli/fw6.md index 6448486..309ca3a 100644 --- a/Documentation/mainboard/protectli/fw6.md +++ b/Documentation/mainboard/protectli/fw6.md @@ -4,6 +4,14 @@ ![](fw6.jpg) +## Stock firmware + +The stock firmware contains only the firmware descriptor, BIOS and +Management Engine. The EC firmware is not present on the SPI chip. + +Using ifdtool, a full layout can be obtained along with the ME and FD +flash regions. + ## Required proprietary blobs To build a minimal working coreboot image some blobs are required (assuming @@ -39,6 +47,9 @@ supporting the chipset is flashrom v1.1. Firmware an be easily flashed with internal programmer (either BIOS region or full image). +The stock firmware can be dumped using [flashrom] or downloaded from +Protectli's official [website]. + ### External programming The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. @@ -59,7 +70,7 @@ - Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs connected). A workaround is to power cycle the board (even a few times) or temporarily disconnect DIMM when platform is powered off. -- When using libgfxinit and SeaBIOS bootsplash, the red color is dim +- When using libgfxinit and SeaBIOS bootsplash, the red color is dim. ## Untested @@ -67,7 +78,6 @@ the cables or not being populated on the board case. - Internal USB 2.0 headers -- Boot with cleaned ME ## Working @@ -83,7 +93,9 @@ - SeaBIOS payload (version rel-1.12.1) - Mini PCIe debug card connected to mSATA (mSATA slot has LPC signals routed) - Reset switch -- Booting Debian, Ubuntu, FreeBSD +- Booting Debian, Ubuntu, FreeBSD, Proxmox +- PCIe passthrough for NICs and iGPU +- Boot with cleaned ME ## Technology @@ -132,6 +144,15 @@ +------------------+--------------------------------------------------+ ``` +## Other compatible boards + +As Protectli licenses and uses [Yanling] appliances with no modifications +to the actual hardware, any compatible [Yanling] appliances would work. +Specifically, look for hardware with the same CPU and NIC and coreboot +should be able to compile and boot with no modifications required. + [Protectli FW6]: https://protectli.com/vault-6-port/ +[website]: https://protectli.com/kb/coreboot-on-the-vault/ [MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,… [flashrom]: https://flashrom.org/Flashrom +[Yanling]: http://www.ylgkdn.cn/ -- To view, visit https://review.coreboot.org/c/coreboot/+/63016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Gerrit-Change-Number: 63016 Gerrit-PatchSet: 7 Gerrit-Owner: Xue Yao <xueyao(a)xyte.ch> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: Documentation: Update Protectli fw6b documentations
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Martin L Roth, Paul Menzel, Xue Yao. Felix Singer has posted comments on this change by Xue Yao. ( https://review.coreboot.org/c/coreboot/+/63016?usp=email ) Change subject: Documentation: Update Protectli fw6b documentations ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Gerrit-Change-Number: 63016 Gerrit-PatchSet: 6 Gerrit-Owner: Xue Yao <xueyao(a)xyte.ch> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Xue Yao <xueyao(a)xyte.ch> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 04:21:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add Elan touchscreen
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85015?usp=email ) Change subject: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 04:15:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Add Fn key scancode
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85014?usp=email ) Change subject: mb/google/nissa/var/rull: Add Fn key scancode ...................................................................... mb/google/nissa/var/rull: Add Fn key scancode The Fn key on rull emits a scancode of 94 (0x5e). BUG=b:372211281 TEST=Flash rull, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85014 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Lei Cao: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index fadb977..08cb3dbe 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only config ACPI_FNKEY_GEN_SCANCODE - default 94 if (BOARD_GOOGLE_XOL || BOARD_GOOGLE_RIVEN) + default 94 if (BOARD_GOOGLE_XOL || BOARD_GOOGLE_RIVEN || BOARD_GOOGLE_RULL) config BOARD_GOOGLE_BRYA_COMMON def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/85014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Gerrit-Change-Number: 85014 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Change padbased_override to rtd3 of wifi
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85000?usp=email ) Change subject: mb/google/nissa/var/rull: Change padbased_override to rtd3 of wifi ...................................................................... mb/google/nissa/var/rull: Change padbased_override to rtd3 of wifi The previous method made cnvi wifi6 configuration cumbersome and unusable. And delete unused pins. We abandoned the fw_config judgment method and changed to the better rtd3. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. wifi7&wifi6 function is normal Change-Id: Ia95dc9f6b707db63840de9b15b38bdaea48ea192 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85000 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/brya/variants/rull/gpio.c M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 3 files changed, 16 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Jayvik Desai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c index c78ad40..81bd280 100644 --- a/src/mainboard/google/brya/variants/rull/gpio.c +++ b/src/mainboard/google/brya/variants/rull/gpio.c @@ -28,7 +28,7 @@ /* B6 : I2C2_SCL ==> NA */ PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B11 : NC ==> EN_PP3300_WLAN_X*/ - PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_GPO(GPP_B11, 1, DEEP), /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ PAD_CFG_GPO(GPP_D11, 1, DEEP), @@ -58,6 +58,8 @@ /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), + /* F11 : WWAN_PWR_ON ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : WWAN_RST_L ==> NA */ PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : SOC_PEN_DETECT_R_ODL ==> NA */ @@ -80,6 +82,8 @@ PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), /* H23 : WWAN_SAR_DETECT_ODL ==> NA */ PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), @@ -123,11 +127,6 @@ /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), - /* F11 : NC ==> WWAN_PWR_ON */ - PAD_CFG_GPO(GPP_F11, 1, DEEP), - /* F12 : GSXDOUT ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), - /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 0b4042e..b59a0de 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -274,6 +274,13 @@ register "add_acpi_dma_property" = "true" device pci 00.0 on end end + chip soc/intel/common/block/pcie/rtd3 + # # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end probe WIFI WIFI_PCIE_WIFI7 probe unprovisioned end diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index a2fffb4..8bb7fac 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -16,29 +16,12 @@ return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); } -static const struct pad_config wifi_pcie_enable_pad[] = { - /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), - /* B11 : NC ==> EN_PP3300_WLAN_X*/ - PAD_CFG_GPO(GPP_B11, 1, DEEP), -}; - void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_is_provisioned()) { - printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); - config->cnvi_bt_core = false; - printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n"); - config->cnvi_bt_audio_offload = false; - } -} - -void fw_config_gpio_padbased_override(struct pad_config *padbased_table) -{ - if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || !fw_config_is_provisioned()) { - printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n"); - gpio_padbased_override(padbased_table, wifi_pcie_enable_pad, - ARRAY_SIZE(wifi_pcie_enable_pad)); + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E))) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + config->cnvi_bt_audio_offload = true; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia95dc9f6b707db63840de9b15b38bdaea48ea192 Gerrit-Change-Number: 85000 Gerrit-PatchSet: 13 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXART
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84999?usp=email ) Change subject: mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXART ...................................................................... mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXART Add Synaptics&PIXART init cpnfig, enable touchpad function BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. touchpad function normal Change-Id: Iacf09cd46d4a97fb79f91043c84452f76689462f Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84999 Reviewed-by: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 21 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Lei Cao: Looks good to me, but someone else must approve Jayvik Desai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 1896d94..0b4042e 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -231,7 +231,27 @@ device i2c 1a on end end end - device ref i2c5 off end # Touchpad + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""PIXART Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 68 on end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- To view, visit https://review.coreboot.org/c/coreboot/+/84999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacf09cd46d4a97fb79f91043c84452f76689462f Gerrit-Change-Number: 84999 Gerrit-PatchSet: 9 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of ...
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84997?usp=email ) ( 20 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3 ...................................................................... mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3 The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/rull/gpio.c M src/mainboard/google/brya/variants/rull/overridetree.cb 2 files changed, 17 insertions(+), 9 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c index 13d6469..c78ad40 100644 --- a/src/mainboard/google/brya/variants/rull/gpio.c +++ b/src/mainboard/google/brya/variants/rull/gpio.c @@ -23,8 +23,6 @@ /* A22 : GPP_A22 ==> NC */ PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), - /* B4 : I2C2_SDA ==> SSD1_RST_L */ - PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : I2C2_SDA ==> NA */ PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : I2C2_SCL ==> NA */ @@ -32,14 +30,18 @@ /* B11 : NC ==> EN_PP3300_WLAN_X*/ PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* D3 : ISH_GP3 ==> NA */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D6 : WWAN_PWR_ENABLE ==> PCIE_REFCLK_SSD1_REQ_N */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), - /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D13 : EN_PP1800_WCAM_X ==> NA */ PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D15 : EN_PP2800_WCAM_X ==> NA */ @@ -105,6 +107,11 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* B4 : I2C2_SDA ==> SSD1_RST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d91a7aa..1896d94 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -405,13 +405,14 @@ }" chip soc/intel/common/block/pcie/rtd3 # enable_gpio is EN_PP3300_SSD - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D11)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" register "srcclk_pin" = "1" - device generic 0 on end + device generic 0 on + probe STORAGE STORAGE_NVME + probe unprovisioned + end end - probe STORAGE STORAGE_NVME - probe unprovisioned end device ref emmc on probe STORAGE STORAGE_EMMC -- To view, visit https://review.coreboot.org/c/coreboot/+/84997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Gerrit-Change-Number: 84997 Gerrit-PatchSet: 22 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add printk log missing carriage return character
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Jérémy Compostella, Pranava Y N. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85020?usp=email ) Change subject: mb/google/fatcat: Add printk log missing carriage return character ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Gerrit-Change-Number: 85020 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 04:14:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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