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Change subject: commonlib/fsp_relocate.c: Use enum cb_err instead of int
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Change subject: commonlib/device_tree: Use enum cb_err instead of int
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Change subject: mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84957/comment/78d0a999_1ae0dca6?us… :
PS5, Line 9: This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as NC to enable S0ix low power entry.
> please use line break at < 72 char
Acknowledged
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Hello Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO
......................................................................
mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO
This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as
NC to enable S0ix low power entry.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/84957/6
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO
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Patch Set 5: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84957/comment/7c153363_9f6bb3ad?us… :
PS5, Line 9: This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as NC to enable S0ix low power entry.
please use line break at < 72 char
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Hello Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84957?usp=email
to look at the new patch set (#5).
Change subject: mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO
......................................................................
mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO
This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as NC to enable S0ix low power entry.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/84957/5
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