coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix uninitialized usb_cfg pointer
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84939?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Fix uninitialized usb_cfg pointer ...................................................................... soc/intel/alderlake: Fix uninitialized usb_cfg pointer This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/alderlake/fsp_params.c:936:48: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84939 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Jayvik Desai: Looks good to me, but someone else must approve build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 839d161..d4cbf0f 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -897,7 +897,7 @@ const struct soc_intel_alderlake_config *config) { struct device *port = NULL; - struct drivers_usb_acpi_config *usb_cfg; + struct drivers_usb_acpi_config *usb_cfg = NULL; bool usb_audio_offload = false; /* Search through the devicetree for matching USB devices */ @@ -931,7 +931,7 @@ if (s_cfg->CnviBtAudioOffload && !usb_audio_offload) { printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver.\n"); } - if (!s_cfg->CnviBtAudioOffload && usb_audio_offload) { + if (!s_cfg->CnviBtAudioOffload && usb_cfg && usb_audio_offload) { printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n"); usb_cfg->cnvi_bt_audio_offload = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/84939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Gerrit-Change-Number: 84939 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/brox: Hint romstage init about upcoming reset
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84937?usp=email ) Change subject: mb/google/brox: Hint romstage init about upcoming reset ...................................................................... mb/google/brox: Hint romstage init about upcoming reset Add support for the mainboard to check for any potential firmware component update and hence the assosicated reset. This indication can be used to avoid any redundant resets during the boot flow. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are provided correctly and 2 redundant resets are filtered out. Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84937 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk A src/mainboard/google/brox/variants/baseboard/brox/romstage.c M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brox/variants/brox/Makefile.mk M src/mainboard/google/brox/variants/brox/variant.c M src/mainboard/google/brox/variants/jubilant/Makefile.mk M src/mainboard/google/brox/variants/jubilant/variant.c M src/mainboard/google/brox/variants/lotso/Makefile.mk M src/mainboard/google/brox/variants/lotso/variant.c 9 files changed, 93 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk index 3a66958..b3149ba 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk +++ b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += memory.c romstage-y += gpio.c +romstage-y += romstage.c romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c new file mode 100644 index 0000000..66ed99b --- /dev/null +++ b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <cbfs.h> +#include <ec/google/chromeec/ec.h> +#include <security/vboot/vboot_common.h> +#include <security/vboot/misc.h> +#include <soc/romstage.h> + +#define FWVER_SIZE 3 +#define FWVER_TO_INT(MAJOR, MINOR, PATCH) \ + ((uint32_t)(((MAJOR) & 0xFF) << 16 | ((MINOR) & 0xFF) << 8 | ((PATCH) & 0xFF))) + +static bool check_auxfw_ver_mismatch(void) +{ + uint8_t *new_ver; + size_t new_ver_size; + struct ec_response_pd_chip_info pd_chip_r = {0}; + const char *fwver_fname = variant_get_auxfw_version_file(); + uint8_t cur_major_ver; + bool mismatch = false, is_productionfw; + int ret; + + ret = google_chromeec_get_pd_chip_info(0, 0, &pd_chip_r); + if (ret < 0) { + printk(BIOS_INFO, "%s: Cannot get PD port info\n", __func__); + return mismatch; + } + cur_major_ver = (pd_chip_r.fw_version_number >> 16) & 0xFF; + is_productionfw = !!(cur_major_ver & 0xF0); + + /* find bundled fw hash */ + new_ver = cbfs_map(fwver_fname, &new_ver_size); + if (new_ver == NULL || new_ver_size != FWVER_SIZE) + return mismatch; + + /* + * Firmware version mismatches and satisfies anti-rollback conditions. + * Anti-rollback conditions are one of the following: + * 1) Not a production firmware. + * 2) New major version is greater than current major version. + */ + if ((pd_chip_r.fw_version_number != + FWVER_TO_INT(new_ver[0], new_ver[1], new_ver[2])) && + (!is_productionfw || new_ver[0] >= cur_major_ver)) { + printk(BIOS_INFO, "%s: Expecting Aux FW update and hence a reset\n", __func__); + mismatch = true; + } + + cbfs_unmap(new_ver); + return mismatch; +} + +bool mainboard_expects_another_reset(void) +{ + if (vboot_recovery_mode_enabled()) + return false; + + if (!CONFIG(VBOOT) || + (vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC) && + vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_AUXFW_SOFTWARE_SYNC))) + return false; + + return check_auxfw_ver_mismatch(); +} diff --git a/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h index a1fbe01..070b2f8 100644 --- a/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h @@ -60,4 +60,5 @@ void variant_init(void); void variant_finalize(void); +const char *variant_get_auxfw_version_file(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/brox/variants/brox/Makefile.mk b/src/mainboard/google/brox/variants/brox/Makefile.mk index 4a7ff71..19eb924 100644 --- a/src/mainboard/google/brox/variants/brox/Makefile.mk +++ b/src/mainboard/google/brox/variants/brox/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/brox/variant.c b/src/mainboard/google/brox/variants/brox/variant.c index 332d152..f09c60e 100644 --- a/src/mainboard/google/brox/variants/brox/variant.c +++ b/src/mainboard/google/brox/variants/brox/variant.c @@ -25,3 +25,12 @@ { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); } + +const char *variant_get_auxfw_version_file(void) +{ + if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_BYPASS))) + return "rts5453_retimer_bypass.hash"; + else if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_JHL8040))) + return "rts5453_retimer_jhl8040.hash"; + return NULL; +} diff --git a/src/mainboard/google/brox/variants/jubilant/Makefile.mk b/src/mainboard/google/brox/variants/jubilant/Makefile.mk index 503ef8f..bb7543b 100644 --- a/src/mainboard/google/brox/variants/jubilant/Makefile.mk +++ b/src/mainboard/google/brox/variants/jubilant/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += gpio.c romstage-y += memory.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brox/variants/jubilant/variant.c b/src/mainboard/google/brox/variants/jubilant/variant.c index 5b75380..ff84374 100644 --- a/src/mainboard/google/brox/variants/jubilant/variant.c +++ b/src/mainboard/google/brox/variants/jubilant/variant.c @@ -31,6 +31,11 @@ return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); } +const char *variant_get_auxfw_version_file(void) +{ + return "rts5453_retimer_bypass.hash"; +} + static void wwan_out_of_reset(void *unused) { if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) { diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk index a1059a5..dde5215 100644 --- a/src/mainboard/google/brox/variants/lotso/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += ramstage.c smm-y += smihandler.c diff --git a/src/mainboard/google/brox/variants/lotso/variant.c b/src/mainboard/google/brox/variants/lotso/variant.c index 066acb2..6121450 100644 --- a/src/mainboard/google/brox/variants/lotso/variant.c +++ b/src/mainboard/google/brox/variants/lotso/variant.c @@ -19,3 +19,12 @@ { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); } + +const char *variant_get_auxfw_version_file(void) +{ + if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_BYPASS))) + return "rts5453_retimer_bypass.hash"; + else if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_JHL8040))) + return "rts5453_retimer_jhl8040.hash"; + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Gerrit-Change-Number: 84937 Gerrit-PatchSet: 7 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85005?usp=email ) Change subject: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info ...................................................................... ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info An unintended suffix got added in google_chromeec_get_pd_chip_info. Fix the typo by removing that suffix. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85005 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Caveh Jalali: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 38f7e87..af5c235 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1170,7 +1170,7 @@ return 0; } -int google_chromeec_get_pd_chip_infoi(int port, int renew, +int google_chromeec_get_pd_chip_info(int port, int renew, struct ec_response_pd_chip_info *r) { const struct ec_params_pd_chip_info p = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 5a65f2d..31c7671 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -346,7 +346,7 @@ * * @return 0 if ok, -1 on error */ -int google_chromeec_get_pd_chip_infoi(int port, int renew, +int google_chromeec_get_pd_chip_info(int port, int renew, struct ec_response_pd_chip_info *r); /* Structure representing the capabilities of a USB-PD port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Gerrit-Change-Number: 85005 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Eric Lai, Robert Chen. Karthik Ramasubramanian has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email ) Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Please rebase this change on top of coreboot tree for Jenkin to verify this CL. We landed another CL recently that should resolve the build error. -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 22:40:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Eric Lai, Robert Chen. Karthik Ramasubramanian has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email ) Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 22:39:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/glinda/pcie_gpp.c: Add PCI routing table
by Maximilian Brune (Code Review) 06 Nov '24

06 Nov '24

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[M] Change in coreboot[main]: soc/amd/glinda/pcie_gpp.c: Add PCI routing table
by Maximilian Brune (Code Review) 06 Nov '24

06 Nov '24

Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/85019?usp=email ) Change subject: soc/amd/glinda/pcie_gpp.c: Add PCI routing table ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: Makefile logic is still missing until I clear up on a few things. Commit Message: https://review.coreboot.org/c/coreboot/+/85019/comment/a372e77d_150f7f78?us… : PS1, Line 9: This patch adds the PCI interrupt routing table. I think (not sure) we are only interested in putting the PCI routing info into coreboot if we want to use something like OpenSIL. In the FSP case the information should be provided to us by FSP. https://review.coreboot.org/c/coreboot/+/85019/comment/3f878a03_db491672?us… : PS1, Line 16: boot Linux with pci=nomsi kernel parameter and check /proc/interrupts Interestingly enough when I do the same test, but instead get the pci routing information from FSP (-> src/soc/amd/common/fsp/pci/pci_routing_info.c) my mainboard doesn't successfully boot into Linux anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/85019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c11205ecc1554451a5e9d8f05102fd0d4d25ad Gerrit-Change-Number: 85019 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 22:10:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd/glinda/pcie_gpp.c: Add PCI routing table
by Maximilian Brune (Code Review) 06 Nov '24

06 Nov '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85019?usp=email ) Change subject: soc/amd/glinda/pcie_gpp.c: Add PCI routing table ...................................................................... soc/amd/glinda/pcie_gpp.c: Add PCI routing table This patch adds the PCI interrupt routing table. It also adds the missing PCI devices in the header files accordingly. source: PPR 57254 Rev 1.59 Table "Recommended interrupt Routing and Swizzling" tested: boot Linux with pci=nomsi kernel parameter and check /proc/interrupts Change-Id: I44c11205ecc1554451a5e9d8f05102fd0d4d25ad Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/include/soc/pci_devs.h A src/soc/amd/glinda/pcie_gpp.c 2 files changed, 88 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85019/1 diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index e85a6e3..01907e8 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -20,36 +20,75 @@ #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) -/* PCIe GFX/GPP Bridge device 1 with no ports */ +/* PCIe USB4 Bridge device 1 with 3 ports */ #define PCIE_GPP_BRIDGE_1_DEV 0x1 +#define PCIE_GPP_1_1_FUNC 1 +#define PCIE_GPP_1_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) +#define SOC_GPP_1_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) + +#define PCIE_GPP_1_2_FUNC 2 +#define PCIE_GPP_1_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) +#define SOC_GPP_1_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) + +#define PCIE_GPP_1_3_FUNC 3 +#define PCIE_GPP_1_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_3_FUNC) +#define SOC_GPP_1_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_3_FUNC) + /* PCIe GPP Bridge device 2 with up to 6 ports */ #define PCIE_GPP_BRIDGE_2_DEV 0x2 -#define PCIE_GPP_2_0_FUNC 1 -#define PCIE_GPP_2_0_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) -#define SOC_GPP_2_0_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) - -#define PCIE_GPP_2_1_FUNC 2 +#define PCIE_GPP_2_1_FUNC 1 #define PCIE_GPP_2_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) #define SOC_GPP_2_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) -#define PCIE_GPP_2_2_FUNC 3 +#define PCIE_GPP_2_2_FUNC 2 #define PCIE_GPP_2_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) #define SOC_GPP_2_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) -#define PCIE_GPP_2_3_FUNC 4 +#define PCIE_GPP_2_3_FUNC 3 #define PCIE_GPP_2_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) #define SOC_GPP_2_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) -#define PCIE_GPP_2_4_FUNC 5 +#define PCIE_GPP_2_4_FUNC 4 #define PCIE_GPP_2_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) #define SOC_GPP_2_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) -#define PCIE_GPP_2_5_FUNC 6 +#define PCIE_GPP_2_5_FUNC 5 #define PCIE_GPP_2_5_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) #define SOC_GPP_2_5_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) +#define PCIE_GPP_2_6_FUNC 6 +#define PCIE_GPP_2_6_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) +#define SOC_GPP_2_6_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) + +/* PCIe GPP Bridge device 3 with up to 6 ports */ +#define PCIE_GPP_BRIDGE_3_DEV 0x3 + +#define PCIE_GPP_3_1_FUNC 1 +#define PCIE_GPP_3_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_1_FUNC) +#define SOC_GPP_3_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_1_FUNC) + +#define PCIE_GPP_3_2_FUNC 2 +#define PCIE_GPP_3_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_2_FUNC) +#define SOC_GPP_3_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_2_FUNC) + +#define PCIE_GPP_3_3_FUNC 3 +#define PCIE_GPP_3_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_3_FUNC) +#define SOC_GPP_3_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_3_FUNC) + +#define PCIE_GPP_3_4_FUNC 4 +#define PCIE_GPP_3_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_4_FUNC) +#define SOC_GPP_3_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_4_FUNC) + +#define PCIE_GPP_3_5_FUNC 5 +#define PCIE_GPP_3_5_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_5_FUNC) +#define SOC_GPP_3_5_DEV _SOC_DEV(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_5_FUNC) + +#define PCIE_GPP_3_6_FUNC 6 +#define PCIE_GPP_3_6_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_6_FUNC) +#define SOC_GPP_3_6_DEV _SOC_DEV(PCIE_GPP_BRIDGE_3_DEV, PCIE_GPP_3_6_FUNC) + /* PCIe Bridges to Bus A, Bus B and Bus C devices */ #define PCIE_ABC_BRIDGE_DEV 0x8 diff --git a/src/soc/amd/glinda/pcie_gpp.c b/src/soc/amd/glinda/pcie_gpp.c new file mode 100644 index 0000000..5ebf4f6 --- /dev/null +++ b/src/soc/amd/glinda/pcie_gpp.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/amd_pci_util.h> +#include <commonlib/bsd/helpers.h> +#include <soc/pci_devs.h> +#include <stddef.h> + +/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ + +const struct pci_routing_info pci_routing_table[] = { + {PCIE_GPP_1_1_DEVFN, 0, PCI_SWIZZLE_ABCD, 0}, + {PCIE_GPP_1_2_DEVFN, 1, PCI_SWIZZLE_ABCD, 0}, + {PCIE_GPP_1_3_DEVFN, 2, PCI_SWIZZLE_ABCD, 0}, + + {PCIE_GPP_2_1_DEVFN, 3, PCI_SWIZZLE_ABCD, 1}, + {PCIE_GPP_2_2_DEVFN, 4, PCI_SWIZZLE_ABCD, 1}, + {PCIE_GPP_2_3_DEVFN, 5, PCI_SWIZZLE_ABCD, 1}, + {PCIE_GPP_2_4_DEVFN, 5, PCI_SWIZZLE_CDAB, 1}, + {PCIE_GPP_2_5_DEVFN, 4, PCI_SWIZZLE_CDAB, 1}, + {PCIE_GPP_2_6_DEVFN, 3, PCI_SWIZZLE_CDAB, 1}, + + {PCIE_GPP_3_1_DEVFN, 2, PCI_SWIZZLE_CDAB, 2}, + {PCIE_GPP_3_2_DEVFN, 1, PCI_SWIZZLE_CDAB, 2}, + {PCIE_GPP_3_3_DEVFN, 0, PCI_SWIZZLE_CDAB, 2}, + {PCIE_GPP_3_4_DEVFN, 0, PCI_SWIZZLE_DABC, 2}, + {PCIE_GPP_3_5_DEVFN, 1, PCI_SWIZZLE_BCDA, 2}, + {PCIE_GPP_3_6_DEVFN, 2, PCI_SWIZZLE_DABC, 2}, + + {PCIE_ABC_A_DEVFN, 3, PCI_SWIZZLE_DABC, 3}, + {PCIE_GPP_B_DEVFN, 4, PCI_SWIZZLE_DABC, 3}, + {PCIE_ABC_C_DEVFN, 5, PCI_SWIZZLE_DABC, 3}, +}; + +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + *entries = ARRAY_SIZE(pci_routing_table); + return pci_routing_table; + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c11205ecc1554451a5e9d8f05102fd0d4d25ad Gerrit-Change-Number: 85019 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Matt DeVillier (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84786?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Nov 2024 21:27:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters
by Matt DeVillier (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/85008?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Gerrit-Change-Number: 85008 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Nov 2024 21:27:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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