coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: drivers/wifi: Remove unnecessary data structure copy
by Jérémy Compostella (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Zhixing Ma, dinesh.sharma(a)intel.com. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84940?usp=email ) Change subject: drivers/wifi: Remove unnecessary data structure copy ...................................................................... Patch Set 1: (1 comment) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/84940/comment/05484bdf_302a79cb?us… : PS1, Line 672: /* > add sar_limits null check? This is a static (private) function and we only call it with sar_limits != NULL -- To view, visit https://review.coreboot.org/c/coreboot/+/84940?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e207 Gerrit-Change-Number: 84940 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: dinesh.sharma(a)intel.com Gerrit-Comment-Date: Fri, 01 Nov 2024 18:10:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com>

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[M] Change in coreboot[main]: drivers/wifi: Remove unnecessary data structure copy
by Bora Guvendik (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Anil Kumar K, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Zhixing Ma, dinesh.sharma(a)intel.com. Bora Guvendik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84940?usp=email ) Change subject: drivers/wifi: Remove unnecessary data structure copy ...................................................................... Patch Set 1: (1 comment) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/84940/comment/9838b381_d466e38e?us… : PS1, Line 672: /* add sar_limits null check? -- To view, visit https://review.coreboot.org/c/coreboot/+/84940?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e207 Gerrit-Change-Number: 84940 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: dinesh.sharma(a)intel.com Gerrit-Comment-Date: Fri, 01 Nov 2024 18:05:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: ec/google/chromeec: Add is_battery_present()
by Karthik Ramasubramanian (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Kapil Porwal, Keith Short, Nick Vaccaro, Rishika Raj, Shelly Chang, Sowmya Aralguppe, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83735?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: ec/google/chromeec: Add is_battery_present() ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83735/comment/ed54a920_4f5afd91?us… : PS7, Line 15: Is there an EC dependency. If so, can you please mark so using `Cq-Depend: chromium:xxxx` -- To view, visit https://review.coreboot.org/c/coreboot/+/83735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie49ed8f6d8b0fa59ec0e7b06efea9cac4d253957 Gerrit-Change-Number: 83735 Gerrit-PatchSet: 7 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 18:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/fizz: Fix USB port defintions
by Matt DeVillier (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Felix Singer. Hello Felix Singer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84955?usp=email to look at the new patch set (#2). Change subject: mb/google/fizz: Fix USB port defintions ...................................................................... mb/google/fizz: Fix USB port defintions commit 6c83a71b0a80 ("skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope") not only moved the USB port definitions under the XHCI device reference, but also combined multiple register definitions. In doing so, it broke the inheritance from the baseboard, since the variant overridetree registers now replaced the entire usb2_ports/usb3_ports structs, rather than replacing individual array elements therein. This resulted in any USB ports inherited from the baseboard and not overridden by the variant being non-functional as they were not included in the resulting combined devicetree. To fix this, return to overriding individual array elements in the usb2/3_ports structs. TEST=build/boot google/fizz/var/karma. Verify all USB ports present and functional. Verify mainboard/static.c in built shows all ports. Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb 3 files changed, 34 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/84955/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80 Gerrit-Change-Number: 84955 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: mb/google/fizz: Fix USB port defintions
by Matt DeVillier (Code Review) 01 Nov '24

01 Nov '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84955?usp=email ) Change subject: mb/google/fizz: Fix USB port defintions ...................................................................... mb/google/fizz: Fix USB port defintions commit 6c83a71b0a80 ("skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope") not only moved the USB port definitions under the XHCI device reference, but also combined multiple register definitions. In doing so, it broke the inheritance from the baseboard, since the variant overridetree registers now replaced the entire usb2_ports/usb3_ports structs, rather than replacing individual array elements therein. This resulted in any USB ports inherited from the baseboard and not overridden by the variant being non-function as they were not included in the resulting combined devicetree. To fix this, return to overriding individual array elements in the usb2/3_ports structs. TEST=build/boot google/fizz/var/karma. Verify all USB ports present and functional. Verify mainboard/static.c in built shows all ports. Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb 3 files changed, 34 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/84955/1 diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 2976deb..25114f0 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -204,25 +204,22 @@ device ref igpu on end device ref sa_thermal on end device ref south_xhci on - register "usb2_ports" = "{ - [0] = USB2_PORT_LONG(OC0), // Type-C - [1] = USB2_PORT_MID(OC3), // Type-A Rear - [2] = USB2_PORT_MID(OC2), // Type-A Front - [3] = USB2_PORT_MID(OC2), // Type-A Front - [4] = USB2_PORT_MID(OC1), // Type-A Rear - [5] = USB2_PORT_MID(OC1), // Type-A Rear - [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth - [7] = USB2_PORT_MID(OC_SKIP), // Type-A 2.0 / Debug - }" + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC0), // Type-C - [1] = USB3_PORT_DEFAULT(OC3), // Type-A Rear - [2] = USB3_PORT_DEFAULT(OC2), // Type-A Front - [3] = USB3_PORT_DEFAULT(OC2), // Type-A Front - [4] = USB3_PORT_DEFAULT(OC1), // Type-A Rear - [5] = USB3_PORT_DEFAULT(OC1), // Type-A Rear - }" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear + chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 649b5c1..f359bf3 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -22,23 +22,20 @@ device domain 0 on device ref south_xhci on - register "usb2_ports" = "{ - [0] = USB2_PORT_LONG(OC_SKIP), // Type-C - [1] = USB2_PORT_MID(OC_SKIP), // HDMI - [2] = USB2_PORT_MID(OC2), // Type-A Rear - [3] = USB2_PORT_MID(OC2), // Type-A Rear - [4] = USB2_PORT_MID(OC3), // Type-A Rear - [5] = USB2_PORT_MID(OC_SKIP), // HDMI Audio - [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth - }" + register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Rear + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C - [1] = USB3_PORT_DEFAULT(OC_SKIP), // HDMI - [2] = USB3_PORT_DEFAULT(OC2), // Type-A Rear - [3] = USB3_PORT_DEFAULT(OC2), // Type-A Rear - [4] = USB3_PORT_DEFAULT(OC3), // Type-A Rear - }" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear + chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index 25b39f4..53fef3c 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -15,17 +15,13 @@ #| Camera | 8 | | #| Touchsreen | 10 | | #+----------------+-------+-----------------------------------+ - register "usb2_ports" = "{ - [2] = USB2_PORT_MID(OC2), // Type-A Side - [3] = USB2_PORT_MID(OC_SKIP), // Card reader - [7] = USB2_PORT_MID(OC_SKIP), // Camera - [9] = USB2_PORT_MID(OC_SKIP), // Touchscreen - }" + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Side + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen - register "usb3_ports" = "{ - [2] = USB3_PORT_DEFAULT(OC2), // Type-A Side - [3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader - }" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/84955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80 Gerrit-Change-Number: 84955 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix uninitialized usb_cfg pointer
by Karthik Ramasubramanian (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84939?usp=email ) Change subject: soc/intel/alderlake: Fix uninitialized usb_cfg pointer ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84939/comment/8cc25392_9501a47a?us… : PS2, Line 908: : usb_cfg = port->chip_info; > can we add a NULL check here ? The next line confirms that usb_cfg is not NULL. From the static analyzer's standpoint, we may not even enter the while loop or everything in the loop is skipped based on if block in line 906. So usb_cfg will be NULL and hence needs to be checked specifically in line 934. -- To view, visit https://review.coreboot.org/c/coreboot/+/84939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Gerrit-Change-Number: 84939 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Nov 2024 15:46:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Enable ChromeOS EC
by Yidi Lin (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84931?usp=email ) Change subject: mb/google/rauru: Enable ChromeOS EC ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rauru/bootblock.c: https://review.coreboot.org/c/coreboot/+/84931/comment/e53ab4c0_0cb2447a?us… : PS2, Line 20: mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); > I’d be great if you mentioned the datasheet in the commit message, where it’s specified, that it ope […] This function call simply indicates that the AP's SPI speed is set to 3MHz on the SPI bus that connects to the ChromeOS EC. -- To view, visit https://review.coreboot.org/c/coreboot/+/84931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059 Gerrit-Change-Number: 84931 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 14:17:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Fix devicetree_update
by Robert Chen (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Robert Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84953?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/dedede/var/drawcia: Fix devicetree_update ...................................................................... mb/google/dedede/var/drawcia: Fix devicetree_update ext_vr_update should be run after board version 0xbw, but skipped by return. BUG=b:376828839 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/drawcia/ramstage.c 1 file changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/84953/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Gerrit-Change-Number: 84953 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Fix devicetree_update
by Robert Chen (Code Review) 01 Nov '24

01 Nov '24

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84953?usp=email ) Change subject: mb/google/dedede/var/drawcia: Fix devicetree_update ...................................................................... mb/google/dedede/var/drawcia: Fix devicetree_update ext_vr_update should be run after board version 0xbw, but skipped by return. BUG=b:376828839 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/drawcia/ramstage.c 1 file changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/84953/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c index aed160e..f7c07c9 100644 --- a/src/mainboard/google/dedede/variants/drawcia/ramstage.c +++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c @@ -10,25 +10,32 @@ static void ext_vr_update(void) { struct soc_intel_jasperlake_config *cfg = config_of_soc(); + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_ABSENT))) cfg->disable_external_bypass_vr = 1; } -void variant_devtree_update(void) +static void update_lte_device_drawper(void) { - uint32_t board_version = board_id(); struct device *lte_usb2 = DEV_PTR(lte_usb2); struct drivers_usb_acpi_config *config; struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0); - /* board version 9 is drawper EVT */ - if (board_version > 9) - return; - if (lte_usb2 == NULL) return; config = config_of(lte_usb2); config->reset_gpio = lte_reset_gpio; - ext_vr_update(); +} + +void variant_devtree_update(void) +{ + uint32_t board_version = board_id(); + + if(board_version > 0xb) + ext_vr_update(); + /* Remove power IC after board version 0xc */ + if (board_version <= 0x9) + update_lte_device_drawper(); + /* board version 9 is drawper EVT */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/84953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Gerrit-Change-Number: 84953 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism
by Paul Menzel (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Lawrence Chang, Nick Vaccaro, Simon Yang. Paul Menzel has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email ) Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Gerrit-Change-Number: 84866 Gerrit-PatchSet: 4 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: David Ruth <druth(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: David Ruth <druth(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 10:28:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit November 2024