coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

[XS] Change in coreboot[main]: soc/intel/skylake: Enable 4E/4F PNP I/O ports in bootblock
by Máté Kukri (Code Review) 22 Nov '24

22 Nov '24

Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/85273?usp=email ) Change subject: soc/intel/skylake: Enable 4E/4F PNP I/O ports in bootblock ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173 Gerrit-Change-Number: 85273 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Comment-Date: Fri, 22 Nov 2024 21:30:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/telith: Add 6W and 15W power limit parameters
by 9elements QA (Code Review) 22 Nov '24

22 Nov '24

9elements QA has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85209?usp=email ) Change subject: mb/google/nissa/var/telith: Add 6W and 15W power limit parameters ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/225362 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/225360 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/225359 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/225358 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/225357 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/225356 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/225355 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/225354 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/225353 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/225352 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/225351 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/225350 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/85209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I069869fa01dc157cf2544e72468f43ce1bb64035 Gerrit-Change-Number: 85209 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 22 Nov 2024 18:43:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update Touch Controller UPD params
by Cliff Huang (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85199?usp=email ) Change subject: soc/intel/pantherlake: Update Touch Controller UPD params ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85199/comment/2aa419a3_ec17bf7d?us… : PS3, Line 563: if (is_devfn_enabled(PCI_DEVFN_THC0)) { : s_cfg->ThcAssignment[0] = THC_0; : s_cfg->ThcMode[0] = config->thc_mode[0]; : s_cfg->ThcWakeOnTouch[0] = config->thc_wake_on_touch[0]; : } else { : s_cfg->ThcAssignment[0] = THC_NONE; : } : if (is_devfn_enabled(PCI_DEVFN_THC1)) { : s_cfg->ThcAssignment[1] = THC_1; : s_cfg->ThcMode[1] = config->thc_mode[1]; : s_cfg->ThcWakeOnTouch[1] = config->thc_wake_on_touch[1]; : } else { : s_cfg->ThcAssignment[1] = THC_NONE; : } : } > ``` […] Bubrata, THC0/1 are used independent to each other. ex in fatcat/ptlrvp: THC0 is for touchscreen and THC1 is for touchpad. Although, when THC1 is enabled, THC0 needs to be enabled as well, which is taken care in devicetree with probe via fw_config. This is due to THC0 is PCI function 0 device. -- To view, visit https://review.coreboot.org/c/coreboot/+/85199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Gerrit-Change-Number: 85199 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 18:41:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: arch/riscv: Allow adding OpenSBI as external blob
by ron minnich (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Arthur Heymans, Felix Held, Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83284?usp=email ) Change subject: arch/riscv: Allow adding OpenSBI as external blob ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6592ad90a254ca4ac9a6cee89404ad49274f0dea Gerrit-Change-Number: 83284 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Nov 2024 18:28:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: commonlib/bsd/cbmem_id.h: Add region for SIL_CONTEXT
by Nick Kochlowski (Code Review) 22 Nov '24

22 Nov '24

Nick Kochlowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84804?usp=email ) Change subject: commonlib/bsd/cbmem_id.h: Add region for SIL_CONTEXT ...................................................................... Abandoned Instead of a dedicated cbmem region for this, we may just create a static sil_context and access it through a helper function when it is needed for any call into OpenSIL. This is fine since currently the three OpenSIL TP calls happen in ramstage, and anyway the helper function can recreate/populate the context if needed as the info doesn't change between stages. -- To view, visit https://review.coreboot.org/c/coreboot/+/84804?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie142c51324cabeaedab51a5ee42f0384b6bb67d9 Gerrit-Change-Number: 84804 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls
by Nick Kochlowski (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, Matt DeVillier, Paul Menzel. Nick Kochlowski has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/84915?usp=email ) Change subject: soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls ...................................................................... Patch Set 7: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84915/comment/ebabc531_6ab98845?us… : PS6, Line 9: Call OpenSIL timepoint 2 right after resource allocation, : and timepoint 3 right before entering payload. > What is OpenSIL timepoint 2 and 3? Please elaborate. Done File src/soc/amd/phoenix/chip.c: PS6: > yes, i agree with that there's nothing in that file that would be needed to be changed or updated fo […] Before we commit to the decision, I wonder if it would be of more instructional value (being a POC implementation) for the three TPs to be called from within this file. It's true for FSP the later calls are done from the driver code instead of here, but they're not called from vendorcode either. What do you think? https://review.coreboot.org/c/coreboot/+/84915/comment/2a26ce62_04eb4ac3?us… : PS6, Line 30: !CONFIG(PLATFORM_USES_FSP2_0) > Do we not have a config for PLATFORM_USES_OPENSIL? That seems like a better choice for this. […] Just added it to the Kconfig since we didn't have that particular config. https://review.coreboot.org/c/coreboot/+/84915/comment/5d1fd232_5e80395f?us… : PS6, Line 41: default: : break; > This seems a little unnecessary. […] Out of good practice, I left the default case and added an error log although we shouldn't expect to see it used. I can remove it altogether if it really isn't needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38 Gerrit-Change-Number: 84915 Gerrit-PatchSet: 7 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Nov 2024 18:09:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Nick Kochlowski <nickkochlowski(a)gmail.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls
by Nick Kochlowski (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier, Nick Kochlowski. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84915?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls ...................................................................... soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls Call OpenSIL timepoint 2 for further initialization of AMD SoC after coreboot has performed PCIe enumeration, and timepoint 3 for late SoC IPs programming and register locking closer to payload load prior to OS handoff. Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/chip.c 2 files changed, 42 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84915/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38 Gerrit-Change-Number: 84915 Gerrit-PatchSet: 7 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral

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[XS] Change in coreboot[main]: commonlib/bsd/cbmem_id.h: Add region for SIL_CONTEXT
by Paul Menzel (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Felix Held, Nick Kochlowski. Paul Menzel has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/84804?usp=email ) Change subject: commonlib/bsd/cbmem_id.h: Add region for SIL_CONTEXT ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84804/comment/2ccfc20e_4861ce65?us… : PS3, Line 10: global SIL_CONTEXT structure used in openSIL API : calls Please elaborate. Can you already point to some specification document? https://review.coreboot.org/c/coreboot/+/84804/comment/da4ad712_3c56a9cb?us… : PS3, Line 9: Add an ID to identify and reserve a region in CBMEM for : the global SIL_CONTEXT structure used in openSIL API : calls. Please re-flow for 72 characters per line. (One line less is going to be used.) https://review.coreboot.org/c/coreboot/+/84804/comment/bc95d03e_f2cb6016?us… : PS3, Line 12: Were you able to test it already? Please add a TEST= line. -- To view, visit https://review.coreboot.org/c/coreboot/+/84804?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie142c51324cabeaedab51a5ee42f0384b6bb67d9 Gerrit-Change-Number: 84804 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Nov 2024 17:25:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
by Paul Menzel (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, V Sowmya, Vidya Gopalakrishnan, Vinay Kumar. Paul Menzel has posted comments on this change by Vidya Gopalakrishnan. ( https://review.coreboot.org/c/coreboot/+/85184?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85184/comment/08cbbf8b_6b8c93cc?us… : PS5, Line 9: The RAPL PL1 limit and MMIO PL1 max values should be set as per : silicon TDP (6W for N150/N250, 15W for N355). According to whom? -- To view, visit https://review.coreboot.org/c/coreboot/+/85184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a Gerrit-Change-Number: 85184 Gerrit-PatchSet: 5 Gerrit-Owner: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 16:42:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
by Paul Menzel (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85124?usp=email ) Change subject: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING ...................................................................... Patch Set 14: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85124/comment/23a4e4ae_369d43bf?us… : PS14, Line 11: we need : to reserve a dedicated buffer for HW TX tracking feature Please elaborate. How big is the buffer? Will the buffer be released after word? https://review.coreboot.org/c/coreboot/+/85124/comment/e3c9fb8f_adcb0d26?us… : PS14, Line 15: TEST=Reserve memory ok Please elaborate, how this can be checked exactly. File src/soc/mediatek/mt8196/soc.c: https://review.coreboot.org/c/coreboot/+/85124/comment/9103b5de_5172c608?us… : PS14, Line 16: uint8_t i; No need to limit the length. Just `size_t` or `unsigned int`. https://review.coreboot.org/c/coreboot/+/85124/comment/e1c4ebaa_2598b282?us… : PS14, Line 23: reserved_size What unit is it? Bytes? https://review.coreboot.org/c/coreboot/+/85124/comment/017ddbe5_eb16d5e9?us… : PS14, Line 23: 0x10000 64 KiB? -- To view, visit https://review.coreboot.org/c/coreboot/+/85124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc Gerrit-Change-Number: 85124 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 16:40:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit November 2024