coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Reserve memory for OP-TEE
by Jarried Lin (Code Review) 22 Nov '24

22 Nov '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85249?usp=email ) Change subject: soc/mediatek/mt8196: Reserve memory for OP-TEE ...................................................................... soc/mediatek/mt8196: Reserve memory for OP-TEE This patch reserves 70MB memory space for running the OP-TEE image. BUG=b:317009620 TEST=build pass Change-Id: I6f75870bdd76e89866508d351b04a0921f30fe4d Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85249/1 diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h index 5e1c705..065c300 100644 --- a/src/soc/mediatek/common/include/soc/symbols.h +++ b/src/soc/mediatek/common/include/soc/symbols.h @@ -6,5 +6,6 @@ #include <symbols.h> DECLARE_REGION(dram_dma) +DECLARE_REGION(resv_mem_optee) #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index f5710f4..f038e23 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -2,6 +2,9 @@ #include <soc/memlayout.h> +#define OPTEE_BUF(addr, size) \ + REGION(resv_mem_optee, addr, size, 4K) + SECTIONS { /* MT8196 has 256KB SRAM. */ @@ -54,6 +57,7 @@ DRAM_DMA(0x80000000, 1M) POSTRAM_CBFS_CACHE(0x80100000, 2M) RAMSTAGE(0x80300000, 2M) + OPTEE_BUF(0x80500000, 70M) BL31(0x94600000, 0x200000) } diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index eb72fca..fee9192 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -5,8 +5,16 @@ #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/pcie.h> +#include <soc/symbols.h> #include <symbols.h> +void bootmem_platform_add_ranges(void) +{ + if (CONFIG(ARM64_BL31_OPTEE_WITH_SMC)) + bootmem_add_range((uint64_t)_resv_mem_optee, + (uint64_t)REGION_SIZE(resv_mem_optee), BM_MEM_RESERVED); +} + static void soc_read_resources(struct device *dev) { ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); -- To view, visit https://review.coreboot.org/c/coreboot/+/85249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f75870bdd76e89866508d351b04a0921f30fe4d Gerrit-Change-Number: 85249 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Krishna P Bhat D, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski. Subrata Banik has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82898?usp=email ) Change subject: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Gerrit-Change-Number: 82898 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 11:35:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
by Jarried Lin (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Crystal Guo, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85124?usp=email to look at the new patch set (#14). Change subject: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING ...................................................................... soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING HW TX tracking works by writing a pattern to the designated DRAM buffer and then reading it back automatically to calculate the appropriate TX time delay. To avoid writing the pattern to system-used memory, we need to reserve a dedicated buffer for HW TX tracking feature. BUG=b:317009620 TEST=Reserve memory ok Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/soc.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/85124/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/85124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc Gerrit-Change-Number: 85124 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
by Jarried Lin (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Crystal Guo, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85124?usp=email to look at the new patch set (#13). Change subject: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING ...................................................................... soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING HW TX tracking works by writing a pattern to the designated DRAM buffer and then reading it back automatically to calculate the appropriate TX time delay. To avoid writing the pattern to system-used memory, we need to reserve a dedicated buffer for HW TX tracking feature. BUG=b:317009620 TEST=Reserve memory ok Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/soc.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/85124/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc Gerrit-Change-Number: 85124 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
by Michał Kopeć (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Krishna P Bhat D, Krystian Hebel, Maciej Pijanowski, Michał Żygowski, Subrata Banik. Michał Kopeć has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82898?usp=email ) Change subject: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Rebased to get rid of conflict -- To view, visit https://review.coreboot.org/c/coreboot/+/82898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Gerrit-Change-Number: 82898 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 11:11:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
by Michał Kopeć (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Krishna P Bhat D, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Subrata Banik. Hello Krishna P Bhat D, Krystian Hebel, Maciej Pijanowski, Michał Żygowski, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82898?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Krystian Hebel, Code-Review+2 by Krishna P Bhat D, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU ...................................................................... soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented in non-Lite CSE SKUs. Original CL [1] adding this feature also says that, but at that point the feature was validated for CSE Lite only. Move cse_get_boot_performance_data() to shared blk/cse/telemetry.c to have it compile for mainboards without CSE Lite. TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`: 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 34,000 945:CSE started to handle ICC configuration 172,000 (138,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000) 991:Die Management Unit (DMU) load completed 360,000 (46,000) 0:1st timestamp 385,844 (25,844) 11:start of bootblock 398,796 (12,952) 12:end of bootblock 402,099 (3,302) [...] [1]: https://review.coreboot.org/c/coreboot/+/59507 Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/cse/telemetry.c 3 files changed, 31 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/82898/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Gerrit-Change-Number: 82898 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
by Jarried Lin (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Crystal Guo, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85124?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING ...................................................................... soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING HW TX tracking works by writing a pattern to the designated DRAM buffer and then reading it back automatically to calculate the appropriate TX time delay. To avoid writing the pattern to system-used memory, we need to reserve a dedicated buffer for HW TX tracking feature. BUG=b:317009620 TEST=Reserve memory ok Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/soc.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/85124/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc Gerrit-Change-Number: 85124 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Update GPIO settings
by Tyler Wang (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Tyler Wang has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85248?usp=email ) Change subject: mb/google/rex/var/kanix: Update GPIO settings ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a9de4098739cbcdc09f2ec685c374bee3c236a7 Gerrit-Change-Number: 85248 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 09:57:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/common: Save dram_reserved_buffer info to sram
by Yu-Ping Wu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85123?usp=email ) Change subject: soc/mediatek/common: Save dram_reserved_buffer info to sram ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/85123/comment/3cbb1922_8503bb1a?us… : PS8, Line 359: reserved_buffer_ptr->dram_rank_num = curr_ddr_info->support_ranks; > mt8196/emi.c has been removed in CL*85098... […] Yup, create a new file mt8196/emi.c (or other name you prefer). -- To view, visit https://review.coreboot.org/c/coreboot/+/85123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc74103c3826a4de525e183e764aa1fd9ac2c131 Gerrit-Change-Number: 85123 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 09:51:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Update GPIO settings
by Tyler Wang (Code Review) 22 Nov '24

22 Nov '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85248?usp=email ) Change subject: mb/google/rex/var/kanix: Update GPIO settings ...................................................................... mb/google/rex/var/kanix: Update GPIO settings BUG=b:366291025 TEST=none Change-Id: I8a9de4098739cbcdc09f2ec685c374bee3c236a7 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/kanix/gpio.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85248/1 diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c index 202dae6..a319429 100644 --- a/src/mainboard/google/rex/variants/kanix/gpio.c +++ b/src/mainboard/google/rex/variants/kanix/gpio.c @@ -56,8 +56,8 @@ PAD_NC(GPP_B03, NONE), /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ PAD_NC(GPP_B04, NONE), - /* GPP_B05 : [] ==> SPKR_INT_L_R */ - PAD_CFG_GPI(GPP_B05, NONE, DEEP), + /* GPP_B05 : [] ==> SPKR_INT_L_R, test point */ + PAD_NC(GPP_B05, NONE), /* GPP_B06 : [] ==> HP_INT_L_R */ PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), /* GPP_B07 : [] ==> CAM_DET_L */ @@ -174,8 +174,8 @@ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), - /* GPP_D18 : net NC is not present in the given design */ - PAD_NC(GPP_D18, NONE), + /* GPP_D18 : [] ==> LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* GPP_D19 : [] ==> EC_SOC_REC_SWITCH_ODL */ PAD_CFG_GPI_LOCK(GPP_D19, NONE, LOCK_CONFIG), /* GPP_D20 : [] ==> SSD_CLKREQ_ODL */ @@ -195,8 +195,8 @@ PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* GPP_E04 : [] ==> SOC_PEN_DETECT */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E04, NONE, PLTRST), + /* GPP_E04 : [] ==> SOC_PEN_DETECT, test point */ + PAD_NC(GPP_E04, NONE), /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */ PAD_CFG_GPO(GPP_E05, 1, DEEP), /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ @@ -320,9 +320,9 @@ PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), /* GPP_S01 : [] ==> SDW_HP_DATA_WLAN_PCM_SYNC */ PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), - /* GPP_S02 : [] ==> DMIC_SOC_CLK0_WLAN_PCM_OUT */ + /* GPP_S02 : [] ==> DMIC_CLK1_R */ PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3), - /* GPP_S03 : [] ==> DMIC_SOC_DATA0_WLAN_PCM_IN */ + /* GPP_S03 : [] ==> DMIC_DATA1_R */ PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3), /* GPP_S04 : Not connected. */ PAD_NC(GPP_S04, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/85248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a9de4098739cbcdc09f2ec685c374bee3c236a7 Gerrit-Change-Number: 85248 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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