coreboot-gerrit November 2024

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v2.0
by Kenji Yu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Jarried Lin. Kenji Yu has posted comments on this change by Kenji Yu. ( https://review.coreboot.org/c/blobs/+/85247?usp=email ) Change subject: soc/mediatek/mt8196: Update SSPM firmware to v2.0 ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/blobs/+/85247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Gerrit-Change-Number: 85247 Gerrit-PatchSet: 8 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 05:42:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v2.0
by Kenji Yu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Jarried Lin, Kenji Yu. Hello Jarried Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/85247?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Kenji Yu Change subject: soc/mediatek/mt8196: Update SSPM firmware to v2.0 ...................................................................... soc/mediatek/mt8196: Update SSPM firmware to v2.0 Update sspm.bin to fix suspend issue. BUG=b:317009620 TEST=test of suspend and resume pass. Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Signed-off-by: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> --- M mainboard/google/guybrush/dewatt_psp_verstage.signed.bin M mainboard/google/guybrush/guybrush_psp_verstage.signed.bin M mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin M soc/mediatek/mt8196/sspm.bin M soc/mediatek/mt8196/sspm.bin.md5 M soc/mediatek/mt8196/sspm_release_notes.txt 6 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/47/85247/6 -- To view, visit https://review.coreboot.org/c/blobs/+/85247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Gerrit-Change-Number: 85247 Gerrit-PatchSet: 6 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v2.0
by Kenji Yu (Code Review) 22 Nov '24

22 Nov '24

Kenji Yu has posted comments on this change by Kenji Yu. ( https://review.coreboot.org/c/blobs/+/85247?usp=email ) Change subject: soc/mediatek/mt8196: Update SSPM firmware to v2.0 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/blobs/+/85247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Gerrit-Change-Number: 85247 Gerrit-PatchSet: 4 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 05:31:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v2.0
by Kenji Yu (Code Review) 22 Nov '24

22 Nov '24

Kenji Yu has posted comments on this change by Kenji Yu. ( https://review.coreboot.org/c/blobs/+/85247?usp=email ) Change subject: soc/mediatek/mt8196: Update SSPM firmware to v2.0 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/blobs/+/85247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Gerrit-Change-Number: 85247 Gerrit-PatchSet: 3 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 05:30:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v2.0
by Kenji Yu (Code Review) 22 Nov '24

22 Nov '24

Kenji Yu has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/85247?usp=email ) Change subject: soc/mediatek/mt8196: Update SSPM firmware to v2.0 ...................................................................... soc/mediatek/mt8196: Update SSPM firmware to v2.0 Update sspm.bin to fix suspend issue. BUG=b:317009620 TEST=test of suspend and resume pass. Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Signed-off-by: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> --- M mainboard/google/guybrush/dewatt_psp_verstage.signed.bin M mainboard/google/guybrush/guybrush_psp_verstage.signed.bin M mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin M soc/mediatek/mt8196/sspm.bin M soc/mediatek/mt8196/sspm.bin.md5 M soc/mediatek/mt8196/sspm_release_notes.txt 6 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/47/85247/1 diff --git a/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin b/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin index a2b5bc0..ef2be8f 100644 --- a/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin +++ b/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin b/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin index ccdf85a..8653223 100644 --- a/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin +++ b/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin b/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin index 28468f7..784ed67 100644 --- a/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin +++ b/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin Binary files differ diff --git a/soc/mediatek/mt8196/sspm.bin b/soc/mediatek/mt8196/sspm.bin index 6841081..099712d 100644 --- a/soc/mediatek/mt8196/sspm.bin +++ b/soc/mediatek/mt8196/sspm.bin Binary files differ diff --git a/soc/mediatek/mt8196/sspm.bin.md5 b/soc/mediatek/mt8196/sspm.bin.md5 index c4c3110..bff7731 100644 --- a/soc/mediatek/mt8196/sspm.bin.md5 +++ b/soc/mediatek/mt8196/sspm.bin.md5 @@ -1 +1 @@ -cbfd0cac5f9ee49a20a64291de7ab8b4 *sspm.bin +3cdf43a33dbdb417d8da460c61e0caef *sspm.bin diff --git a/soc/mediatek/mt8196/sspm_release_notes.txt b/soc/mediatek/mt8196/sspm_release_notes.txt index be43022..03d60de 100644 --- a/soc/mediatek/mt8196/sspm_release_notes.txt +++ b/soc/mediatek/mt8196/sspm_release_notes.txt @@ -1,4 +1,4 @@ ** Build from MediaTek Internal ** -# Version 1.0 -1. Add sspm.bin v1.0. +# Version 2.0 +1. Add sspm.bin v2.0. -- To view, visit https://review.coreboot.org/c/blobs/+/85247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I2c5503e31c2d97bc23d39c7ae442a1849a0dec85 Gerrit-Change-Number: 85247 Gerrit-PatchSet: 1 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Move CSE sync at payload
by Kapil Porwal (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Paul Menzel, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85233?usp=email ) Change subject: mb/google/fatcat: Move CSE sync at payload ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f1dd2e153ed0f1e671699002cf34a58d758ce2f Gerrit-Change-Number: 85233 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 04:16:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Held, Felix Singer, Frans Hendriks, Jérémy Compostella, Patrick Rudolph, Paul Menzel, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 60: Code-Review+1 (6 comments) File src/soc/intel/snowridge/acpi.c: https://review.coreboot.org/c/coreboot/+/83321/comment/4eaf1bae_bca5460e?us… : PS60, Line 94: /* PCH PCIe root port needs further swizzle. */ Not sure the root port itself needs such pin swizzle or not (though I agree its child device's intx message needs such transformation). https://review.coreboot.org/c/coreboot/+/83321/comment/dbe62fd7_31918f30?us… : PS60, Line 115: intel_write_pci_PRT(scope, pin_irq_map, map_count, &pirq_map); The scope could be obtained from domain's device path, e.g. acpi_device_acope() https://review.coreboot.org/c/coreboot/+/83321/comment/e1b2d794_30eba74d?us… : PS60, Line 127: /* Generating accelerator domains dynamically since they are SKU-dependent. */ Maybe add a comment that pch domain (domain0) is in dsdt https://review.coreboot.org/c/coreboot/+/83321/comment/dd299d59_3d3ded73?us… : PS60, Line 280: if (dev == DEV_PTR(dlb_sa)) { If using devicetree ptr in soc codes, there should be a soc layer devicetree.cb to be consistent. https://review.coreboot.org/c/coreboot/+/83321/comment/7a6e963b_52aad638?us… : PS60, Line 333: struct device *dev = PCH_DEV_XHCI; Not sure if this could be represented as a devicetree ptr, thus to reduce the types of dev reference overall. File src/soc/intel/snowridge/lpc.c: https://review.coreboot.org/c/coreboot/+/83321/comment/c75c76a3_23349e8b?us… : PS60, Line 47: swizzle_pin = get_pci_irq_pins(dev, &bridge); Can this code working with multiple pcie bridge layers? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 60 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 22 Nov 2024 04:13:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya/var/redrix: Add ACPI fan definitions
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85175?usp=email ) Change subject: mb/google/brya/var/redrix: Add ACPI fan definitions ...................................................................... mb/google/brya/var/redrix: Add ACPI fan definitions Add entries in overridetree.cb required for exposing fan control via ACPI, which is used then by acpi-fan driver in Linux kernel. This includes: 1. Fan duty-cycle/rpm table. The RPM numbers were adjusted to the values reported by ACPI on different duty cycle levels. 2. Dummy Active DPTF policy. This is required to mark the TFNx devices as active and therefore let the acpi-fan driver probe. BUG=b:358089775 TEST=Build and flash on redrix and check /sys/class/thermal for TFN1 Change-Id: Iaeffe8bc48cd8cd800efa7be29ec81447ecf2935 Signed-off-by: Stanislaw Kardach <skardach(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85175 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 56 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 1843670..7acb3ff 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -162,6 +162,41 @@ register "options.tsr[2].desc" = ""Charger"" register "options.tsr[3].desc" = ""5V regulator"" + ## Active Policy + # NOTE: Copy from EC. Only to enable acpi-fan. + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(100, 85), + TEMP_PCT( 58, 78), + TEMP_PCT( 57, 71), + TEMP_PCT( 56, 68), + TEMP_PCT( 55, 66), + TEMP_PCT( 54, 53), + } + }, + [1] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(100, 85), + TEMP_PCT( 58, 78), + TEMP_PCT( 57, 71), + TEMP_PCT( 56, 68), + TEMP_PCT( 55, 66), + TEMP_PCT( 54, 53), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(100, 100), + TEMP_PCT( 58, 63), + TEMP_PCT( 57, 61), + } + } + }" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ @@ -194,6 +229,27 @@ [2] = { 16, 1000 }, [3] = { 8, 500 } }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + # NOTE: Noise and Power numbers are placeholders. + register "controls.fan_perf" = "{ + [ 0] = { 100, 9500, 200, 2000, }, + [ 1] = { 90, 8700, 180, 1800, }, + [ 2] = { 80, 8000, 160, 1600, }, + [ 3] = { 70, 7200, 140, 1400, }, + [ 4] = { 60, 6300, 120, 1200, }, + [ 5] = { 50, 5400, 100, 1000, }, + [ 6] = { 40, 4400, 80, 800, }, + [ 7] = { 30, 3300, 60, 600, }, + [ 8] = { 20, 2100, 40, 400, }, + [ 9] = { 10, 800, 20, 200, }, + [10] = { 0, 0, 0, 0, }, + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + device generic 0 alias dptf_policy on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaeffe8bc48cd8cd800efa7be29ec81447ecf2935 Gerrit-Change-Number: 85175 Gerrit-PatchSet: 3 Gerrit-Owner: Stanisław Kardach <skardach(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Turn off camera during S0ix
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85133?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/pujjoga: Turn off camera during S0ix ...................................................................... mb/google/nissa/var/pujjoga: Turn off camera during S0ix Add a variant specific S0ix hook to fill the SSDT table to disable and enable camera during suspend and resume respectively. For safety concern, our client LENOVO want us to follow the Boten project to create the function. BUG=b:378525209 TEST=Build Pujjoga BIOS image. Ensure that camera is disabled during suspend and enabled during resume. Do the powerd_dbus_suspend and measure the camera power 3.3V which is disable. And resume will recover. Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993 Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85133 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjoga/variant.c 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjoga/variant.c b/src/mainboard/google/brya/variants/pujjoga/variant.c index c4a6fac..2264264c 100644 --- a/src/mainboard/google/brya/variants/pujjoga/variant.c +++ b/src/mainboard/google/brya/variants/pujjoga/variant.c @@ -2,8 +2,23 @@ #include <fw_config.h> #include <sar.h> +#include <acpi/acpigen.h> +#include <gpio.h> +#include <acpi/acpi.h> +#include <baseboard/variants.h> + const char *get_wifi_sar_cbfs_filename(void) { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); } + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + /* GPP_C3 control the 3.3V of user facing camera, + pull down when do suspend and pull high when resume. */ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(GPP_C3); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(GPP_C3); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993 Gerrit-Change-Number: 85133 Gerrit-PatchSet: 12 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nikki Huang <nikki.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/fatcat/var/francka: Add memory DQ map
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85205?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat/var/francka: Add memory DQ map ...................................................................... mb/google/fatcat/var/francka: Add memory DQ map Follow latest schematics MB_SCH_1102A to add the DQ map. BUG=b:372395010 TEST=emerge-fatcat coreboot Change-Id: I2ea0c5a07d83df108e41fc838e702b793c878096 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85205 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/memory.c 2 files changed, 94 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/Makefile.mk index bb28536..f4b5d45 100644 --- a/src/mainboard/google/fatcat/variants/francka/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/francka/Makefile.mk @@ -3,6 +3,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c diff --git a/src/mainboard/google/fatcat/variants/francka/memory.c b/src/mainboard/google/fatcat/variants/francka/memory.c new file mode 100644 index 0000000..74d74cd --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/memory.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 14, 12, 15, 11, 10, 8, 9 }, + .dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 }, + }, + .ddr1 = { + .dq0 = { 1, 3, 0, 2, 7, 4, 6, 5 }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, + }, + .ddr2 = { + .dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 14, 13, 15, 12, 8, 11, 10, 9 }, + }, + .ddr3 = { + .dq0 = { 6, 5, 7, 4, 2, 3, 1, 0 }, + .dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 }, + }, + .ddr4 = { + .dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 }, + .dq1 = { 15, 14, 12, 13, 9, 11, 10, 8 }, + }, + .ddr5 = { + .dq0 = { 6, 5, 7, 4, 3, 1, 0, 2 }, + .dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 }, + }, + .ddr6 = { + .dq0 = { 9, 10, 11, 8, 14, 12, 13, 15 }, + .dq1 = { 0, 1, 2, 3, 5, 7, 4, 6 }, + }, + .ddr7 = { + .dq0 = { 0, 1, 2, 3, 7, 5, 6, 4 }, + .dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .lp_ddr_dq_dqs_re_training = 1, + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_D08 + * GPIO_MEM_CONFIG_1 GPP_D07 + * GPIO_MEM_CONFIG_2 NC + * GPIO_MEM_CONFIG_3 NC + */ + gpio_t spd_gpios[] = { + GPP_D08, + GPP_D07, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ea0c5a07d83df108e41fc838e702b793c878096 Gerrit-Change-Number: 85205 Gerrit-PatchSet: 6 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com>

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coreboot-gerrit November 2024