coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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2521 discussions

[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84932?usp=email ) Change subject: mb/google/rauru: Configure TPM ...................................................................... Patch Set 13: (3 comments) Patchset: PS11: > `aarch64-elf-ld. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/84932/comment/18d51987_4de10211?us… : PS11, Line 12: IRQ_TYPE_LEVEL_LOW for now > IRQ_TYPE_EDGE_RISING Done https://review.coreboot.org/c/coreboot/+/84932/comment/639e2ed5_2ce6e52b?us… : PS11, Line 14: there is no CR50 TPM timeout log > Please paste the log message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 11:44:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KB
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85043?usp=email ) Change subject: soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KB ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85043/comment/5cc1e7a3_7f09009b?us… : PS1, Line 7: Increase bootblock size > … from 70 kB to 75 kB Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Gerrit-Change-Number: 85043 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 11:43:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84932?usp=email to look at the new patch set (#13). Change subject: mb/google/rauru: Configure TPM ...................................................................... mb/google/rauru: Configure TPM 1. Add TPM support 2. Configure I2C speed to I2C_SPEED_FAST_PLUS 3. Pass GPIO_GSC_AP_INT_ODL to the payload 4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now TEST=build pass, boot ok and there is no CR50 TPM timeout log Pass log: [INFO ] Probing TPM I2C: done! DID_VID 0x504a6666 [DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a) BUG=b:317009620 Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/bootblock.c M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 4 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84932/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KB
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85043?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KB ...................................................................... soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KB Increase the bootblock size to support TPM. TEST=Build pass BUG=b:317009620 Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85043/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Gerrit-Change-Number: 85043 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Increase bootblock size
by Paul Menzel (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85043?usp=email ) Change subject: soc/mediatek/mt8196: Increase bootblock size ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85043/comment/8720a966_c1f1df3a?us… : PS1, Line 7: Increase bootblock size … from 70 kB to 75 kB -- To view, visit https://review.coreboot.org/c/coreboot/+/85043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Gerrit-Change-Number: 85043 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 11:38:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Increase bootblock size
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85043?usp=email ) Change subject: soc/mediatek/mt8196: Increase bootblock size ...................................................................... soc/mediatek/mt8196: Increase bootblock size Increase the bootblock size to support TPM. TEST=Build pass BUG=b:317009620 Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85043/1 diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index 9bddf10..f5710f4 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -43,7 +43,7 @@ DRAM_INIT_CODE(0x02000000, 600K) #else /* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */ - BOOTBLOCK(0x02001000, 70K) + BOOTBLOCK(0x02001000, 75K) #endif OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) PRERAM_CBFS_CACHE(0x020DA000, 48K) -- To view, visit https://review.coreboot.org/c/coreboot/+/85043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Gerrit-Change-Number: 85043 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Guangjie Song, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84497?usp=email to look at the new patch set (#30). The following approvals got outdated and were removed: Code-Review+1 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... soc/mediatek/mt8196: Add mtcmos init support Add mtcmos init code and APIs for controlling power domain. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h A src/soc/mediatek/mt8196/mtcmos.c 5 files changed, 941 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84497/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 30 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Enable IRQ routing
by Paul Menzel (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Shuo Liu. Paul Menzel has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84328?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Enable IRQ routing ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84328/comment/aeef2787_0e4f344f?us… : PS6, Line 13: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> Please try to follow the convention and sort it, so that no comma is needed. https://review.coreboot.org/c/coreboot/+/84328/comment/687377e5_2033c3a5?us… : PS6, Line 13: Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> Should Pen-Chun have been the author? -- To view, visit https://review.coreboot.org/c/coreboot/+/84328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Gerrit-Change-Number: 84328 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 11:18:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Paul Menzel (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Jarried Lin. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 2: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/85034/comment/8cf03dd0_6d46fd17?us… : PS2, Line 15: MEM_CHIP_DDR5 = 0x50, : MEM_CHIP_LPDDR5 = 0x58, : MEM_CHIP_LPDDR5X = 0x59 > It just follows the numbering rule here. […] Good find. That was two years ago. I can’t even remember most of the things I did last week (or yesterday). ;-) Maybe mention, to start the numbering with 0x5… is it’s DDR5. -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 11:16:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Yidi Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/85034/comment/5d65b7a7_e10da3c7?us… : PS2, Line 15: MEM_CHIP_DDR5 = 0x50, : MEM_CHIP_LPDDR5 = 0x58, : MEM_CHIP_LPDDR5X = 0x59 > Where are the numbers from? It just follows the numbering rule here. https://review.coreboot.org/c/coreboot/+/59193/comment/8b45355f_2bb583ab/ You also joined the review. Don't you ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 11:10:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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