coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Paul Menzel (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Jarried Lin. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 2: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/85034/comment/5d1cc2ef_5d972f6b?us… : PS2, Line 15: MEM_CHIP_DDR5 = 0x50, : MEM_CHIP_LPDDR5 = 0x58, : MEM_CHIP_LPDDR5X = 0x59 Where are the numbers from? -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 10:54:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Paul Menzel (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Jarried Lin. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85034/comment/dff19e95_74feada2?us… : PS2, Line 9: Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. Also mention `MEM_CHIP_UNDEFINED`? -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 10:54:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85034/comment/97ae7979_4af0f737?us… : PS1, Line 7: LPDDR5 > `DDR5/LPDDR5` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 10:52:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Jarried Lin. Hello Crystal Guo, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85034?usp=email to look at the new patch set (#2). Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. BUG=b:357743097 TEST=build pass Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85034/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Lean Sheng Tan (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 30: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 30 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 10:32:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: southbridge/intel/common: Imrpove ACPI _PRT method generation
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85013?usp=email ) Change subject: southbridge/intel/common: Imrpove ACPI _PRT method generation ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Gerrit-Change-Number: 85013 Gerrit-PatchSet: 5 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Fri, 08 Nov 2024 10:32:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/topton/adl: Add initial support for X2F N100 FW appliance
by Alicja Michalska (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/84175?usp=email ) Change subject: mb/topton/adl: Add initial support for X2F N100 FW appliance ...................................................................... Patch Set 9: (3 comments) File src/mainboard/topton/adl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84175/comment/cfed738a_b348461f?us… : PS2, Line 43: # TODO: SATA doesn't work. EDK2 returns "Unsupported", not sure how to fix (yet). > Okay, then I would leave the SATA ports enabled in the devicetree since that's correct. […] That's a good question, AFAIK this SoC has 8 lanes: - NVME: x2 - ETH0: x1 - ETH1: x1 - ETH2: X1 - ETH3: X1 - WiFi: X1 This leaves us with one more lane assigned... somewhere? File src/mainboard/topton/adl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84175/comment/cf4f20d0_c0c6493d?us… : PS9, Line 99: chip superio/ite/it8625e > Does fan control work? This device is fanless (using chassis as a heatsink), so no :D File src/mainboard/topton/adl/mainboard.c: https://review.coreboot.org/c/coreboot/+/84175/comment/1efbdcea_c28b7d4c?us… : PS9, Line 17: params->PchLegacyIoLowLatency = 1; > Okay, fair enough. […] ack -- To view, visit https://review.coreboot.org/c/coreboot/+/84175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65 Gerrit-Change-Number: 84175 Gerrit-PatchSet: 9 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:49:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/gpmr/Kconfig: PS1: > Ah, "GPMR registers" refers to the registers in GPMR used for extended BIOS region. […] Seems no. In existing code, GPMR refers to the GPMR register for extended BIOS region in some code, however it also refers to all the private configuration registers under `PID_DMI`. I will find a more clearer name for this set of registers. -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:38:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email ) Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/itss/itss.c: https://review.coreboot.org/c/coreboot/+/85012/comment/9340fffc_a52ebd6c?us… : PS5, Line 140: uint16_t pir = pcr_read16(PID_ITSS, itss_soc_get_pir(dev)); Will itss_soc_get_pir use offsets other than PCR_ITSS_PIR? -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 5 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Fri, 08 Nov 2024 09:37:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Felix Singer, Jérémy Compostella, Paul Menzel, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... Patch Set 34: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 34 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:32:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit November 2024