coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2521 discussions

[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Felix Singer, Jérémy Compostella, Paul Menzel, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... Patch Set 34: (1 comment) File src/soc/intel/common/block/imc/imc.c: https://review.coreboot.org/c/coreboot/+/83320/comment/e8b1ede0_cfcbbd2e?us… : PS21, Line 4: IO based access will not work. > It's by design. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 34 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:27:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Angel Pons (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/gpmr/Kconfig: PS1: > Okay, I'm a bit confused. […] Ah, "GPMR registers" refers to the registers in GPMR used for extended BIOS region. Do they have a more specific name? -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Fri, 08 Nov 2024 09:25:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Angel Pons (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/gpmr/Kconfig: PS1: Okay, I'm a bit confused. How does one have GPMR support without GPMR registers? -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Fri, 08 Nov 2024 09:21:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Lean Sheng Tan, Paul Menzel, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 30: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 30 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:21:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Angel Pons (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Lean Sheng Tan, Paul Menzel, Shuo Liu, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 30: Code-Review+2 (1 comment) File src/soc/intel/common/block/systemagent-server/common.c: https://review.coreboot.org/c/coreboot/+/83318/comment/a4f45969_a0a124d8?us… : PS29, Line 8: pci_moving_config32 > Maybe a separate patch. Okay, let's keep it like this for now, but it would be nice to update common code to provide these "moving config" functions with SIMPLE_DEVICE. -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 30 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:19:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 50: (2 comments) File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/289980d4_a31a722a?us… : PS50, Line 417: if (is_dev_on_domain0(dev) && is_pch_slot(PCI_DEV2DEVFN(PCI_BDF(dev))) && > yes, most of them are assigned with `default_pci_ops_dev`. Acknowledged File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/ea48cfbb_6d587c5c?us… : PS50, Line 31: /* The PCIe MMCFG limit in registers is not correct thus using the configuration value here. */ > @shuo.liu@intel.com, I've added comment for it in the latest patch. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 50 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:19:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: mb/topton/adl: Add initial support for X2F N100 FW appliance
by Angel Pons (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Alicja Michalska. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/84175?usp=email ) Change subject: mb/topton/adl: Add initial support for X2F N100 FW appliance ...................................................................... Patch Set 9: (3 comments) File src/mainboard/topton/adl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84175/comment/cc7b6253_5d81c9be?us… : PS2, Line 43: # TODO: SATA doesn't work. EDK2 returns "Unsupported", not sure how to fix (yet). > I believe ADL-N has two SATA ports, but when I tried adding what you just mentioned - drive wasn't r […] Okay, then I would leave the SATA ports enabled in the devicetree since that's correct. Regarding GPIOs: I think there's some GPIOs that control SATA/PCIe muxing. Could it be that some lanes are shared between SATA and PCIe (e.g. NVMe)? File src/mainboard/topton/adl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84175/comment/7fd2eca4_827eddb9?us… : PS9, Line 99: chip superio/ite/it8625e Does fan control work? File src/mainboard/topton/adl/mainboard.c: https://review.coreboot.org/c/coreboot/+/84175/comment/bccfc564_2cb88f59?us… : PS9, Line 17: params->PchLegacyIoLowLatency = 1; > It disables some DMI-related power saving features, I probably could remove it if I do a bit more te […] Okay, fair enough. I would either add a short comment (`Disable DMI/PCIe ASPM to work around NVMe instability`) or remove it if it's not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65 Gerrit-Change-Number: 84175 Gerrit-PatchSet: 9 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:17:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 50: (4 comments) File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/acfedc07_381ffe91?us… : PS50, Line 417: if (is_dev_on_domain0(dev) && is_pch_slot(PCI_DEV2DEVFN(PCI_BDF(dev))) && > Seems that these static PCH devices will be assigned with an ops later by the PCI probing process, r […] yes, most of them are assigned with `default_pci_ops_dev`. https://review.coreboot.org/c/coreboot/+/83321/comment/a12188ec_7228b19a?us… : PS50, Line 418: (dev->ops == NULL || dev->ops->enable == NULL)) { > What is the benefit of (dev->ops == NULL || dev->ops->enable == NULL)?, just to double confirm it is […] Actually at the time when this function is called, the device is not assigned with a device operation, I think it could be removed to avoid confusing. File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/7a49a27f_858fee12?us… : PS15, Line 17: *size = CONFIG_ECAM_MMCONF_LENGTH; > Maybe to add a comment here as a note? Done File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/b9888390_dfe29996?us… : PS50, Line 31: /* The PCIe MMCFG limit in registers is not correct thus using the configuration value here. */ @shuo.liu@intel.com, I've added comment for it in the latest patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 50 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:16:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I think the key would be the relationships between HAVE_GPMR_REGISTERS and USE_SOC_GPMR_DEFS, should we allow any combination of them? -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:13:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Angel Pons, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Raise the open In previous patch https://review.coreboot.org/c/coreboot/+/83317, I added `USE_SOC_GPMR_DEFS` to allow SoC to use its specific GPMR register definitions. For SNR, it didn't have GPMR and I was using a Kconfig item CONFIG_UNDEFINED_REGISTER for them originally, but this made the code hard to maintain, so I add this patch to disable the related code. -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 09:05:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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coreboot-gerrit November 2024