coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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2521 discussions

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KB
by Yidi Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85043?usp=email ) Change subject: soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KB ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Gerrit-Change-Number: 85043 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 13:24:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/telith: Add Fn key scancode
by Kun Liu (Code Review) 08 Nov '24

08 Nov '24

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85045?usp=email ) Change subject: mb/google/nissa/var/telith: Add Fn key scancode ...................................................................... mb/google/nissa/var/telith: Add Fn key scancode The Fn key on telith emits a scancode of 94 (0x5e). BUG=b:372506691 TEST=Flash telith, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Ib69af9a8448312b275de46f9c835f8a9d592312a Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85045/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 08cb3dbe..f2eefec 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only config ACPI_FNKEY_GEN_SCANCODE - default 94 if (BOARD_GOOGLE_XOL || BOARD_GOOGLE_RIVEN || BOARD_GOOGLE_RULL) + default 94 if (BOARD_GOOGLE_XOL || BOARD_GOOGLE_RIVEN || BOARD_GOOGLE_RULL || BOARD_GOOGLE_TELITH) config BOARD_GOOGLE_BRYA_COMMON def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/85045?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib69af9a8448312b275de46f9c835f8a9d592312a Gerrit-Change-Number: 85045 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT
by Rui Zhou (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Rui Zhou has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85044?usp=email ) Change subject: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/rull/variant.c: https://review.coreboot.org/c/coreboot/+/85044/comment/53c1b26c_bb1eac34?us… : PS3, Line 27: config->cnvi_bt_core > i guess config->cnvi_bt_core is default false unless overridden No, I made this mistake on the 15217 branch. if it isn't set to false here, it will trigger an assert error (fw15217:coreboot/src/soc/intel/alderlake/fsp_params.c ```assert(s_cfg->CnviMode || !s_cfg->CnviBtCore);```), thus affecting the coreboot operation and system boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/85044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Gerrit-Change-Number: 85044 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Nov 2024 13:17:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Enable IRQ routing
by Shuo Liu (Code Review) 08 Nov '24

08 Nov '24

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84328?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Enable IRQ routing ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84328/comment/e1fab908_1a826427?us… : PS6, Line 13: Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> > Should Pen-Chun have been the author? Oops, yes, this is a mistake made in patch porting. Will pay attention the next time. https://review.coreboot.org/c/coreboot/+/84328/comment/d94b8613_b58a2942?us… : PS6, Line 13: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> > Please try to follow the convention and sort it, so that no comma is needed. Got, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/84328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Gerrit-Change-Number: 84328 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 08 Nov 2024 13:07:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT
by Subrata Banik (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85044?usp=email ) Change subject: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/rull/variant.c: https://review.coreboot.org/c/coreboot/+/85044/comment/5493bf5c_6b897564?us… : PS3, Line 27: config->cnvi_bt_core i guess config->cnvi_bt_core is default false unless overridden -- To view, visit https://review.coreboot.org/c/coreboot/+/85044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Gerrit-Change-Number: 85044 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Nov 2024 13:04:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT
by Rui Zhou (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85044?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT ...................................................................... mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT When we use PCIE wifi7, CNVI BT and BT offload should be turned off. BUG=b:374629673 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/variant.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85044/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Gerrit-Change-Number: 85044 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT
by Rui Zhou (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85044?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT ...................................................................... mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT When we use PCIE wifi7, CNVI BT and BT offload should be turned off. BUG=b:374629673 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/variant.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85044/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Gerrit-Change-Number: 85044 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT
by Rui Zhou (Code Review) 08 Nov '24

08 Nov '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85044?usp=email ) Change subject: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT ...................................................................... mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT When we use PCIE wifi7, CNVI BT and BT offload should be turned off. BUG=b:374629673 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b --- M src/mainboard/google/brya/variants/rull/variant.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85044/1 diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index 8bb7fac..31367e7 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -22,6 +22,10 @@ printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); config->cnvi_bt_core = true; config->cnvi_bt_audio_offload = true; + } else if(fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_WIFI7))) { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + config->cnvi_bt_audio_offload = false; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Gerrit-Change-Number: 85044 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo, Paul Menzel. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85034/comment/470ef470_57f8e06d?us… : PS2, Line 9: Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. > Also mention `MEM_CHIP_UNDEFINED`? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 11:52:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo, Jarried Lin. Hello Crystal Guo, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85034?usp=email to look at the new patch set (#3). Change subject: mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type ...................................................................... mem_chip_info: Add DDR5/LPDDR5 enums to mem_chip_type Add MEM_CHIP_UNDEFINED, MEM_CHIP_DDR5, MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. BUG=b:357743097 TEST=build pass Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85034/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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coreboot-gerrit November 2024