coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2521 discussions

[S] Change in coreboot[main]: mb/google/brox: Do not select HAVE_ACPI_RESUME
by Karthik Ramasubramanian (Code Review) 09 Nov '24

09 Nov '24

Attention is currently required from: Bob Moragues, Edward Hill, Karthik Ramasubramanian, Shyam Sundar Radjacoumar, Subrata Banik. Hello Bob Moragues, Edward Hill, Shyam Sundar Radjacoumar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85038?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Bob Moragues, Code-Review+1 by Shyam Sundar Radjacoumar, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/brox: Do not select HAVE_ACPI_RESUME ...................................................................... mb/google/brox: Do not select HAVE_ACPI_RESUME Brox mainboard does not reliably support S3 entry/exit. Hence do not select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board reset if the system resumes from S3. BUG=b:337274309 TEST=Build Brox BIOS image and boot to OS. Ensure that the _S3 name variable is not advertised in the DSDT. Trigger a S3 entry and ensure that on S3 exit, the board reset is triggered. Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/bootblock.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85038/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Gerrit-Change-Number: 85038 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Edward Hill <ecgh(a)google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

1 0

[S] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data
by Felix Held (Code Review) 09 Nov '24

09 Nov '24

Felix Held has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85059?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data ...................................................................... drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data The basic flash parameter table described in JESB216F can be up to 23 DWORDs (92 bytes) long which is larger than the 47 byte SPI data buffer in the AMD SoCs which also contains the data from the command buffer except the command byte. TEST=Calling 'read_sfdp_data' with a data length of 256 bytes which is larger than the buffer of the AMD SPI host controller now works and returns the SFDP data expected from the W74M12JW SPI flash: 0x00: 53 46 44 50 06 01 02 ff 00 06 01 10 80 00 00 ff SFDP............ 0x10: 84 00 01 02 d0 00 00 ff 03 00 01 02 f0 00 00 ff ................ 0x20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ ... 0x80: e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb . ......D..k.;B. 0x90: fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 ..........@.. .R 0xa0: 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 ....6........cv3 0xb0: 7a 75 7a 75 f7 bd d5 5c 19 f7 4d ff e9 30 f8 80 zuzu...\..M..0.. 0xc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xd0: 00 00 f0 ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xf0: 38 9b 96 f0 a5 ad a5 ff ff ff ff ff ff ff ff ff 8............... Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/spi/spi_flash_sfdp.c 1 file changed, 21 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85059/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Gerrit-Change-Number: 85059 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data
by Felix Held (Code Review) 09 Nov '24

09 Nov '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85059?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data ...................................................................... drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data The basic flash parameter table described in JESB216F can be up to 23 DWORDs (92 bytes) long which is larger than the 47 byte SPI data buffer in the AMD SoCs which also contains the data from the command buffer except the command byte. TEST=Calling 'read_sfdp_data' with a data length of 256 bytes which is larger than the buffer of the AMD SPI host controller now works and returns the SFDP data expected from the W74M12JW SPI flash: 0x00: 53 46 44 50 06 01 02 ff 00 06 01 10 80 00 00 ff SFDP............ 0x10: 84 00 01 02 d0 00 00 ff 03 00 01 02 f0 00 00 ff ................ 0x20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ ... 0x80: e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb . ......D..k.;B. 0x90: fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 ..........@.. .R 0xa0: 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 ....6........cv3 0xb0: 7a 75 7a 75 f7 bd d5 5c 19 f7 4d ff e9 30 f8 80 zuzu...\..M..0.. 0xc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xd0: 00 00 f0 ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xf0: 38 9b 96 f0 a5 ad a5 ff ff ff ff ff ff ff ff ff 8............... Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/spi/spi_flash_sfdp.c 1 file changed, 21 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85059/1 diff --git a/src/drivers/spi/spi_flash_sfdp.c b/src/drivers/spi/spi_flash_sfdp.c index 46117bc..6f0b0aa 100644 --- a/src/drivers/spi/spi_flash_sfdp.c +++ b/src/drivers/spi/spi_flash_sfdp.c @@ -10,8 +10,6 @@ /* * Assumptions (not) made in the code: * - code is supposed to be endian-safe - * - requested SFDP data blocks are small enough to fit into the SPI controller buffer, so no - * spi_crop_chunk calls are needed * * Limitations: * - only legacy access protocol supported: @@ -24,20 +22,35 @@ #define CMD_READ_SFDP 0x5a +static void read_sfdp_data_update_buffer_offset(uint8_t *buf_cmd, uint32_t offset) +{ + buf_cmd[1] = offset >> 16 & 0xff; + buf_cmd[2] = offset >> 8 & 0xff; + buf_cmd[3] = offset >> 0 & 0xff; +} + static enum cb_err read_sfdp_data(const struct spi_flash *flash, uint32_t offset, size_t len, uint8_t *buf) { uint8_t buf_cmd[5]; buf_cmd[0] = CMD_READ_SFDP; - buf_cmd[1] = offset >> 16 & 0xff; - buf_cmd[2] = offset >> 8 & 0xff; - buf_cmd[3] = offset >> 0 & 0xff; + /* the read offset in buf_cmd[1..3] gets written in + read_sfdp_data_update_buffer_offset */ buf_cmd[4] = 0; /* dummy byte */ - /* TODO: use spi_crop_chunk to break up larger transfers */ - if (spi_flash_cmd_multi(&flash->spi, buf_cmd, sizeof(buf_cmd), buf, len)) - return CB_ERR; + uint8_t *data = buf; + + /* split data transfers into chunks that each fit into the SPI controller's buffer */ + while(len) { + uint32_t xfer_len = spi_crop_chunk(&flash->spi, sizeof(buf_cmd), len); + read_sfdp_data_update_buffer_offset(buf_cmd, offset); + if (spi_flash_cmd_multi(&flash->spi, buf_cmd, sizeof(buf_cmd), data, xfer_len)) + return CB_ERR; + offset += xfer_len; + data += xfer_len; + len -= xfer_len; + } return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Gerrit-Change-Number: 85059 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: mb/google/brox: Do not select HAVE_ACPI_RESUME
by Bob Moragues (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Edward Hill, Karthik Ramasubramanian. Bob Moragues has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85038?usp=email ) Change subject: mb/google/brox: Do not select HAVE_ACPI_RESUME ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Gerrit-Change-Number: 85038 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward Hill <ecgh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 21:54:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters
by Felix Held (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Martin Roth, Matt DeVillier. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/85008?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters ...................................................................... Patch Set 4: (2 comments) File src/drivers/spi/spi_flash_sfdp.c: https://review.coreboot.org/c/coreboot/+/85008/comment/fc9ed8f5_a8c7b09b?us… : PS3, Line 202: #define > Why not put this in a header file? Sure, it may only be used here, but it clutters the C code IMO. i wanted to keep that parameter id close to the corresponding parameter table field defines and i found that moving all of that into a header file makes it more difficult to read, since you have to switch back and forth between the c and the h file https://review.coreboot.org/c/coreboot/+/85008/comment/67718582_468375f1?us… : PS3, Line 250: multiplicator > Multiplier? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Gerrit-Change-Number: 85008 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 19:52:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Felix Held (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Martin Roth, Matt DeVillier. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84786?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... Patch Set 11: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84786/comment/6e7d0325_a5b8a97f?us… : PS10, Line 10: a : specific > Nit: Maybe you only tested on one chip, but this should work with any chip that supports this mechan […] Done File src/drivers/spi/spi_flash_sfdp.c: https://review.coreboot.org/c/coreboot/+/84786/comment/9f1615d5_ade311b8?us… : PS10, Line 46: 0x50444653 > Nit: Use the ascii characters instead, or at least include them as a comment? the cbmem ids also use hex numbers instead of char arrays; the byte order is also in reverse. i'll add a comment https://review.coreboot.org/c/coreboot/+/84786/comment/2bd17df1_f39c0438?us… : PS10, Line 158: %#x > %p? it's an uint32_t, not an actual c pointer, so %#x is correct here https://review.coreboot.org/c/coreboot/+/84786/comment/32a3c4ea_bb00e59f?us… : PS10, Line 176: if (get_sfdp_header(flash, &sfdp_rev, &param_header_count, &access_protocol) != CB_SUCCESS) > Does this line need to be wrapped? makes the code look a bit worse, but yes -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 19:52:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters
by Felix Held (Code Review) 08 Nov '24

08 Nov '24

1 0

[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Felix Held (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Felix Held, Martin Roth, Matt DeVillier. Hello Martin Roth, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84786?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Code-Review+2 by Martin Roth, Verified+1 by build bot (Jenkins) Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... drivers/spi/spi_flash_sfdp: add basic SFDP support Add basic support for the Serial Flash Discoverable Parameters (SFDP) standard which can be used to discover the parameters to interact with any SPI flash chip that supports this mechanism. This commit adds functionality to find specific SFDP parameter headers and print all SFDP parameter headers, but not to parse any SFDP parameter table. This is a preparation for a follow-up patch that adds support to parse the RPMC SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in the next patch, it's marked as static inline in this commit so that the code still build; the 'inline' keyword will be removed again in that follow-up patch. For now, only the legacy access protocol using single bit SPI transfers is supported, but this should cover most of the SPI NOR flash chips. In any other case, the code will error out. It's also assumed that the SFDP data blocks read from the SPI flash chip are small enough to fit into the SPI host controller buffer and don't need to be broken up into multiple transfers. This limitation will be addressed in a follow-up patch. JESD216F.02 was used as a reference. TEST=On a board with a W74M12JW SPI flash chip, calling 'spi_flash_print_sfdp_headers' prints this on the console output: Manufacturer: ef SF: Detected ef 6018 with sector size 0x1000, total 0x1000000 SF: Exiting 4-byte addressing mode SFDP header found in SPI flash. major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3 SFPD header with index 0: table ID 0xff00, major rev 0x1, minor rev 0x6 table pointer 0x80, table length DWORDS 0x10 SFPD header with index 1: table ID 0xff84, major rev 0x1, minor rev 0x0 table pointer 0xd0, table length DWORDS 0x2 SFPD header with index 2: table ID 0xff03, major rev 0x1, minor rev 0x0 table pointer 0xf0, table length DWORDS 0x2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.mk A src/drivers/spi/spi_flash_sfdp.c M src/include/spi_flash.h 4 files changed, 212 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/84786/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: util/crosfirmware: Add support for parsing from manifest.json
by Matt DeVillier (Code Review) 08 Nov '24

08 Nov '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85024?usp=email ) Change subject: util/crosfirmware: Add support for parsing from manifest.json ...................................................................... util/crosfirmware: Add support for parsing from manifest.json Some ChromeOS recovery images, such as for GRUNT, support multiple boards / multiple bios/ec images, but do not break them out in a 'models' subdirectory like modern recovery images do. Instead, they use a manifest.json to map the board name to the correct bios/ec images. Add support for parsing out the info from here. TEST=run `util/chromeos/crosfirmware.sh kasumi` and verify that the correct shellball firmware is extracted from the recovery image. Change-Id: I64153ba16cb8328d65a0f088d05f04a969f6810f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85024 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M util/chromeos/crosfirmware.sh 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index e72ff7d..ee87329 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -107,6 +107,9 @@ fi _bios_image=$(grep "IMAGE_MAIN" $_unpacked/models/$_board/setvars.sh | cut -f2 -d\") + elif [ -f "$_unpacked/manifest.json" ]; then + _version=$(grep -m1 -A1 "$BOARD" "$_unpacked/manifest.json" | grep "host" | cut -f12 -d'"') + _bios_image=$(grep -m1 -A3 "$BOARD" "$_unpacked/manifest.json" | grep "image" | cut -f4 -d'"') else _version=$(cat $_unpacked/VERSION | grep BIOS\ version: | cut -f2 -d: | tr -d \ ) -- To view, visit https://review.coreboot.org/c/coreboot/+/85024?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64153ba16cb8328d65a0f088d05f04a969f6810f Gerrit-Change-Number: 85024 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Update power limits config
by Subrata Banik (Code Review) 08 Nov '24

08 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85006?usp=email ) Change subject: soc/intel/pantherlake: Update power limits config ...................................................................... soc/intel/pantherlake: Update power limits config This updates power_limits_config for Panther Lake U and H. Source: Intel PTL PDG 813278 Intel PTL FSP Power limit profiles table BUG=b:357011633 TEST=Build fatcat and boot with Panther Lake SoC and RVP. Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb 2 files changed, 9 insertions(+), 9 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 59aad4f..b59ce5e 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -65,9 +65,9 @@ } cpuid_to_ptl[] = { { PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W }, { PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W }, - { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_3_CORE, TDP_45W }, - { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_1_CORE, TDP_25W }, - { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_1_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W }, }; /* Types of display ports */ diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb index 4f6c8e04..f4c1b26 100644 --- a/src/soc/intel/pantherlake/chipset.cb +++ b/src/soc/intel/pantherlake/chipset.cb @@ -4,20 +4,20 @@ register "power_limits_config[PTL_U_1_CORE]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 54, - .tdp_pl4 = 142, + .tdp_pl2_override = 55, + .tdp_pl4 = 152, }" register "power_limits_config[PTL_H_1_CORE]" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 64, - .tdp_pl4 = 154, + .tdp_pl2_override = 95, + .tdp_pl4 = 239, }" register "power_limits_config[PTL_H_2_CORE]" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 80, - .tdp_pl4 = 240, + .tdp_pl2_override = 64, + .tdp_pl4 = 154, }" # NOTE: if any variant wants to override this value, use the same format -- To view, visit https://review.coreboot.org/c/coreboot/+/85006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Gerrit-Change-Number: 85006 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2024