coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0
by Subrata Banik (Code Review) 08 Nov '24

08 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84916?usp=email ) Change subject: device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0 ...................................................................... device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0 This patch adds new DID0 PCI device IDs for Intel PTL-H. Additionally, updates the System Agent driver's `systemagent_ids` list and Panther Lake SoC bootblock to support these new IDs. Source: Intel PTL-FAS. Document Number 812562 BUG=b:347669091 TEST=Build fatcat and boot with Panther Lake SoC with newly added MCH ID. With patch, coreboot log: `[DEBUG] MCH: device id b004 (rev 00) is Pantherlake H` `[DEBUG] MCH: device id b00a (rev 00) is Pantherlake H` Change-Id: I56e795696f661d88828d7549f856eee19c46c942 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84916 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/pantherlake/bootblock/report_platform.c M src/soc/intel/pantherlake/chip.h 4 files changed, 8 insertions(+), 0 deletions(-) Approvals: Wonkyu Kim: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4730f3f..6386891 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4456,6 +4456,8 @@ #define PCI_DID_INTEL_PTL_U_ID_1 0xb000 #define PCI_DID_INTEL_PTL_H_ID_1 0xb001 #define PCI_DID_INTEL_PTL_H_ID_2 0xb002 +#define PCI_DID_INTEL_PTL_H_ID_3 0xb004 +#define PCI_DID_INTEL_PTL_H_ID_4 0xb00a #define PCI_DID_INTEL_SNR_ID 0x09a2 /* Intel SMBUS device Ids */ diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 3b71633..b358202 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -427,6 +427,8 @@ PCI_DID_INTEL_PTL_U_ID_1, PCI_DID_INTEL_PTL_H_ID_1, PCI_DID_INTEL_PTL_H_ID_2, + PCI_DID_INTEL_PTL_H_ID_3, + PCI_DID_INTEL_PTL_H_ID_4, PCI_DID_INTEL_LNL_M_ID, PCI_DID_INTEL_LNL_M_ID_1, PCI_DID_INTEL_MTL_M_ID, diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c index 22cda26..55afc49 100644 --- a/src/soc/intel/pantherlake/bootblock/report_platform.c +++ b/src/soc/intel/pantherlake/bootblock/report_platform.c @@ -31,6 +31,8 @@ { PCI_DID_INTEL_PTL_U_ID_1, "Pantherlake U" }, { PCI_DID_INTEL_PTL_H_ID_1, "Pantherlake H" }, { PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" }, + { PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" }, + { PCI_DID_INTEL_PTL_H_ID_4, "Pantherlake H" }, }; static struct { diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index d902865..59aad4f 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -66,6 +66,8 @@ { PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W }, { PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W }, { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_3_CORE, TDP_45W }, + { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_1_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_1_CORE, TDP_25W }, }; /* Types of display ports */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56e795696f661d88828d7549f856eee19c46c942 Gerrit-Change-Number: 84916 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/var/riven: Optimize the stop delay for touchsreen
by Subrata Banik (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85039?usp=email ) Change subject: mb/google/var/riven: Optimize the stop delay for touchsreen ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85039/comment/91fe8929_8cb7d617?us… : PS2, Line 12: > can you please add the spec dependency from the bug for transparency Could you please elaborate on why we think 180ms is a good delay and why we don't need a higher delay? -- To view, visit https://review.coreboot.org/c/coreboot/+/85039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7dcbc393bfae9bb62b5700bb9042a543152e968 Gerrit-Change-Number: 85039 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Nov 2024 19:08:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Paul Menzel (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84932?usp=email ) Change subject: mb/google/rauru: Configure TPM ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84932/comment/5f45cf41_3a33e1f9?us… : PS11, Line 14: TEST=build pass, boot ok and there is no CR50 TPM timeout log > Of course. The factory also measured the signal in order the meet SI requirement. Maybe add the measurements results to the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 18:32:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brox: Do not select HAVE_ACPI_RESUME
by Shyam Sundar Radjacoumar (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Edward Hill, Karthik Ramasubramanian. Shyam Sundar Radjacoumar has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85038?usp=email ) Change subject: mb/google/brox: Do not select HAVE_ACPI_RESUME ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Gerrit-Change-Number: 85038 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward Hill <ecgh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 18:20:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/spi: add RPMC info to spi_flash struct
by Martin Roth (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/85009?usp=email ) Change subject: drivers/spi: add RPMC info to spi_flash struct ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9 Gerrit-Change-Number: 85009 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 17:41:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters
by Martin Roth (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/85008?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters ...................................................................... Patch Set 3: Code-Review+2 (3 comments) Patchset: PS3: Everything looks good. Some nits, but nothing to stop the merge. Change them or close the comments - Just wanted to bring them to your attention. File src/drivers/spi/spi_flash_sfdp.c: https://review.coreboot.org/c/coreboot/+/85008/comment/5ac3a078_237aca3e?us… : PS3, Line 202: #define Why not put this in a header file? Sure, it may only be used here, but it clutters the C code IMO. https://review.coreboot.org/c/coreboot/+/85008/comment/7074f826_dade23b4?us… : PS3, Line 250: multiplicator Multiplier? https://www.merriam-webster.com/dictionary/multiplicator -- To view, visit https://review.coreboot.org/c/coreboot/+/85008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Gerrit-Change-Number: 85008 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 17:39:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Martin Roth (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84786?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... Patch Set 10: Code-Review+2 (5 comments) Patchset: PS10: Just nits. Fix them here, in a follow-on, or don't fix them. Up to you. Commit Message: https://review.coreboot.org/c/coreboot/+/84786/comment/ddac3923_a24f19c4?us… : PS10, Line 10: a : specific Nit: Maybe you only tested on one chip, but this should work with any chip that supports this mechanism (and meets the requirements), right? Maybe "any"? Add the requirements listed in spi_flash_sfdp.c to the commit message? File src/drivers/spi/spi_flash_sfdp.c: https://review.coreboot.org/c/coreboot/+/84786/comment/868e51f9_5ce5ccc4?us… : PS10, Line 46: 0x50444653 Nit: Use the ascii characters instead, or at least include them as a comment? https://review.coreboot.org/c/coreboot/+/84786/comment/2a14015f_675c1183?us… : PS10, Line 158: %#x %p? https://review.coreboot.org/c/coreboot/+/84786/comment/93814d5e_847ebb83?us… : PS10, Line 176: if (get_sfdp_header(flash, &sfdp_rev, &param_header_count, &access_protocol) != CB_SUCCESS) Does this line need to be wrapped? -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Nov 2024 17:30:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update power limits config
by Wonkyu Kim (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N. Wonkyu Kim has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/85006?usp=email ) Change subject: soc/intel/pantherlake: Update power limits config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Gerrit-Change-Number: 85006 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 17:26:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0
by Wonkyu Kim (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N. Wonkyu Kim has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/84916?usp=email ) Change subject: device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56e795696f661d88828d7549f856eee19c46c942 Gerrit-Change-Number: 84916 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 17:25:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat: support ISH
by Bora Guvendik (Code Review) 08 Nov '24

08 Nov '24

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84739?usp=email ) Change subject: mb/google/fatcat: support ISH ...................................................................... Abandoned will use CL84998 instead -- To view, visit https://review.coreboot.org/c/coreboot/+/84739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b6eb39fe7b07fcabc255d66df4aa0aa2865df79 Gerrit-Change-Number: 84739 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com>

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coreboot-gerrit November 2024