coreboot-gerrit November 2024

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[S] Change in coreboot[main]: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER
by Lean Sheng Tan (Code Review) 09 Nov '24

09 Nov '24

Attention is currently required from: Wonkyu Kim, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/84200?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: This has to be manually rebased -- To view, visit https://review.coreboot.org/c/coreboot/+/84200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af Gerrit-Change-Number: 84200 Gerrit-PatchSet: 5 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Sat, 09 Nov 2024 10:22:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: arch/x86: Define macros for hard-coded HPET registers
by Lean Sheng Tan (Code Review) 09 Nov '24

09 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84252?usp=email ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/x86: Define macros for hard-coded HPET registers ...................................................................... arch/x86: Define macros for hard-coded HPET registers HPET General Capabilities and ID Register at offset 0x0 and Timer 0 Configuration and Capability Register at offset 0x100 are used to determine the generation of HPET ACPI tables. This patch adds macro definitions for these registers and fields. Definitions are from IA-PC HPET (High Precision Event Timers) Specification Revision 1.0a. Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84252 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/include/arch/hpet.h M src/soc/intel/xeon_sp/uncore_acpi.c 2 files changed, 15 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/arch/x86/include/arch/hpet.h b/src/arch/x86/include/arch/hpet.h index 224279e..7c2e44f 100644 --- a/src/arch/x86/include/arch/hpet.h +++ b/src/arch/x86/include/arch/hpet.h @@ -5,4 +5,15 @@ #define HPET_BASE_ADDRESS 0xfed00000 +/** + * Definitions are from IA-PC HPET (High Precision Event Timers) Specification, + * Revision 1.0a + */ +#define HPET_GEN_CAP_ID 0x0 +#define HPET_NUM_TIM_CAP_MASK 0x1f +#define HPET_NUM_TIM_CAP_SHIFT 8 + +#define HPET_TMR0_CNF_CAP 0x100 +#define HPET_TIMER_FSB_EN_CNF_MASK (1 << 15) + #endif /* ARCH_X86_HPET_H */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 949c88b..9823d94 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -324,13 +324,14 @@ // Add HPET if (is_dev_on_domain0(iommu)) { - uint16_t hpet_capid = read16p(HPET_BASE_ADDRESS); - uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + uint16_t hpet_capid = read16p(HPET_BASE_ADDRESS + HPET_GEN_CAP_ID); + // Bits [8:12] has hpet count + uint16_t num_hpets = (hpet_capid >> HPET_NUM_TIM_CAP_SHIFT) & HPET_NUM_TIM_CAP_MASK; printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", __func__, hpet_capid, num_hpets); //BIT 15 if (num_hpets && (num_hpets != 0x1f) && - (read32p(HPET_BASE_ADDRESS + 0x100) & (0x00008000))) { + (read32p(HPET_BASE_ADDRESS + HPET_TMR0_CNF_CAP) & (HPET_TIMER_FSB_EN_CNF_MASK))) { union p2sb_bdf hpet_bdf = soc_get_hpet_bdf(); printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/84252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa Gerrit-Change-Number: 84252 Gerrit-PatchSet: 17 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Lean Sheng Tan (Code Review) 09 Nov '24

09 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... soc/intel/common/block/imc: Add Integrated Memory Controller driver Intel common IMC contains an embedded SMBus controller for SPD data access. This patch implements IMC based SPD access supports through MMIO. Register definitons are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Tested-by: Yuchi Chen <yuchi.chen(a)intel.com> Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83320 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- A src/soc/intel/common/block/imc/Kconfig A src/soc/intel/common/block/imc/Makefile.mk A src/soc/intel/common/block/imc/imc.c A src/soc/intel/common/block/imc/imclib.h A src/soc/intel/common/block/imc/spd_access.c M src/soc/intel/common/block/include/intelblocks/imc.h M src/soc/intel/common/block/smbus/Makefile.mk M src/soc/intel/common/block/smbus/smbuslib.c 8 files changed, 292 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/common/block/imc/Kconfig b/src/soc/intel/common/block/imc/Kconfig new file mode 100644 index 0000000..f731954 --- /dev/null +++ b/src/soc/intel/common/block/imc/Kconfig @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_BLOCK_IMC + bool + depends on ECAM_MMCONF_SUPPORT + default n + help + Select this to access SPD data through Integrated Memory Controller. diff --git a/src/soc/intel/common/block/imc/Makefile.mk b/src/soc/intel/common/block/imc/Makefile.mk new file mode 100644 index 0000000..0c074a3 --- /dev/null +++ b/src/soc/intel/common/block/imc/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_IMC),y) +romstage-y += imc.c +romstage-y += spd_access.c +endif diff --git a/src/soc/intel/common/block/imc/imc.c b/src/soc/intel/common/block/imc/imc.c new file mode 100644 index 0000000..ccc3d5c --- /dev/null +++ b/src/soc/intel/common/block/imc/imc.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/bsd/cb_err.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <intelblocks/imc.h> +#include <soc/pci_devs.h> +#include <stdbool.h> +#include <timer.h> + +#include "imclib.h" + +#define IMC_SMBUS_TIMEOUT_MS 100 + +#define SMB_CMD_CFG 0x80 +#define SMB_CKOVRD BIT(29) +#define SMB_DIS_WRT BIT(28) +#define SMB_SOFT_RST BIT(24) +#define SMB_TSOD_POLL_EN BIT(20) +#define SMB_CMD_TRIGGER BIT(19) +#define SMB_WORD_ACCESS BIT(17) +#define SMB_WRT_READ (0 << 15) +#define SMB_WRT_WRITE BIT(15) +#define SMB_DTI_MASK (7 << 11) +#define SMB_CMD_SA_SHIFT 8 +#define SMB_CMD_BA_SHIFT 0 +#define SMB_CMD_DTI_SHIFT 11 +#define SMB_STATUS_CFG 0x84 +#define SMB_SBE BIT(1) +#define SMB_BUSY BIT(0) +#define SMB_DATA_CFG 0x88 +#define SMB_PERIOD_CFG 0x90 +#define SMB_CLOCK_PERIOD_400K 250 /* Clock period for 400K. */ +#define SMB_CLOCK_OFFSET_400K 35 /* Clock offset for 400K. */ + +static void imc_spd_smbus_reset(pci_devfn_t dev) +{ + uint32_t cmd; + + cmd = pci_read_config32(dev, SMB_CMD_CFG); + cmd &= ~SMB_CKOVRD; + cmd |= SMB_SOFT_RST; + pci_write_config32(dev, SMB_CMD_CFG, cmd); + + mdelay(35); /* See description of `SMB_CKOVRD` field. */ + + cmd = pci_read_config32(dev, SMB_CMD_CFG); + cmd |= SMB_CKOVRD; + cmd &= ~SMB_SOFT_RST; + pci_write_config32(dev, SMB_CMD_CFG, cmd); +} + +void imc_spd_smbus_init(pci_devfn_t dev) +{ + uint32_t status, cmd; + if (pci_read_config16(dev, 0) == 0xffff) { + printk(BIOS_ERR, + "IMC SMBUS controller PCI: %02x:%02x:%02x.%01x isn't present!\n", + PCI_DEV2SEG(dev), PCI_DEV2BUS(dev), PCI_SLOT(PCI_DEV2DEVFN(dev)), + PCI_FUNC(PCI_DEV2DEVFN(dev))); + return; + } + + /* Set SMB CLOCK to 400K to detect DIMM SPDs. */ + pci_write_config32(dev, SMB_PERIOD_CFG, + (SMB_CLOCK_OFFSET_400K << 16) | SMB_CLOCK_PERIOD_400K); + + /* Reset the bus if the first access is busy. */ + status = pci_read_config32(dev, SMB_STATUS_CFG); + if (status & SMB_BUSY) + imc_spd_smbus_reset(dev); + + /* Disable TSOD polling. */ + cmd = pci_read_config32(dev, SMB_CMD_CFG); + cmd &= ~SMB_TSOD_POLL_EN; + pci_write_config32(dev, SMB_CMD_CFG, cmd); +} + +static bool poll_ready(pci_devfn_t dev, uint32_t *status) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, IMC_SMBUS_TIMEOUT_MS); + + do { + *status = pci_read_config32(dev, SMB_STATUS_CFG); + if ((*status & SMB_BUSY) == 0) + return true; + } while (!stopwatch_expired(&sw)); + + return false; +} + +static bool claim_controller(pci_devfn_t dev) +{ + uint32_t cmd, status; + + cmd = pci_read_config32(dev, SMB_CMD_CFG); + cmd &= ~SMB_TSOD_POLL_EN; + cmd &= ~SMB_DIS_WRT; + pci_write_config32(dev, SMB_CMD_CFG, cmd); + + return poll_ready(dev, &status); +} + +static bool release_controller(pci_devfn_t dev) +{ + uint32_t cmd, status; + + cmd = pci_read_config32(dev, SMB_CMD_CFG); + cmd |= SMB_TSOD_POLL_EN; + pci_write_config32(dev, SMB_CMD_CFG, cmd); + + return poll_ready(dev, &status); +} + +int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, + enum device_type_id dti, enum access_width width, + enum memory_controller_id mcid, enum smbus_command cmd, void *data) +{ + int ret = CB_ERR; + uint32_t cmdbits, stat, databits, data_mask; + uint16_t wdata = 0, rdata = 0; + + /* Slaves addresses are 3 bits length, and bus address is 8 bits length. */ + if (slave_addr > (1 << 7) - 1) { + printk(BIOS_ERR, "Invalid SMBus slave 0x%02x\n", slave_addr); + return CB_ERR; + } + + if (!claim_controller(dev)) { + printk(BIOS_ERR, "Claim controller failed!\n"); + return CB_ERR; + } + + cmdbits = slave_addr << SMB_CMD_SA_SHIFT; + cmdbits |= bus_addr << SMB_CMD_BA_SHIFT; + + if (cmd == IMC_WRITE) { + databits = pci_read_config32(dev, SMB_DATA_CFG); + wdata = (width == IMC_DATA_BYTE ? read8(data) : cpu_to_be16(read16(data))); + databits |= (wdata << 16); + pci_write_config32(dev, SMB_DATA_CFG, databits); + + cmdbits |= SMB_WRT_WRITE; + cmdbits &= ~SMB_DIS_WRT; + } else { + cmdbits |= SMB_WRT_READ; + } + + if (width == IMC_DATA_WORD) { + cmdbits |= SMB_WORD_ACCESS; + data_mask = 0xffff; + } else { + data_mask = 0xff; + } + + cmdbits &= ~SMB_DTI_MASK; + cmdbits |= dti << SMB_CMD_DTI_SHIFT; + cmdbits |= SMB_CKOVRD; + + /* Pull the trigger */ + cmdbits |= SMB_CMD_TRIGGER; + pci_write_config32(dev, SMB_CMD_CFG, cmdbits); + + if (!poll_ready(dev, &stat)) { + printk(BIOS_ERR, "IMC transfer didn't finished for slave 0x%02x\n", slave_addr); + ret = CB_ERR; + goto cleanup; + } + + if (stat & SMB_SBE) { + printk(BIOS_ERR, "IMC SMBUS SBE for slave 0x%02x\n", slave_addr); + ret = CB_ERR; + goto cleanup; + } + + if (cmd == IMC_READ) { + databits = pci_read_config32(dev, SMB_DATA_CFG); + rdata = databits & data_mask; + if (width == IMC_DATA_WORD) + write16(data, be16_to_cpu(rdata)); + else + write8(data, rdata); + } + + ret = CB_SUCCESS; + +cleanup: + if (!release_controller(dev)) { + printk(BIOS_ERR, "Release controller failed!\n"); + return CB_ERR; + } + + return ret; +} diff --git a/src/soc/intel/common/block/imc/imclib.h b/src/soc/intel/common/block/imc/imclib.h new file mode 100644 index 0000000..2b0989e --- /dev/null +++ b/src/soc/intel/common/block/imc/imclib.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_IMC_IMCLIB_H +#define SOC_INTEL_COMMON_BLOCK_IMC_IMCLIB_H + +#include <device/pci_type.h> + +enum smbus_command { IMC_READ, IMC_WRITE }; + +enum access_width { IMC_DATA_BYTE, IMC_DATA_WORD }; + +enum memory_controller_id { IMC_CONTROLLER_ID0, IMC_CONTROLLER_ID1 }; + +enum device_type_id { + IMC_DEVICE_TSOD = 0x3, + IMC_DEVICE_WP_EEPROM = 0x6, + IMC_DEVICE_EEPROM = 0xa +}; + +/* Initiate SMBus/I2C transaction to DIMM EEPROM */ +int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, + enum device_type_id dti, enum access_width width, + enum memory_controller_id mcid, enum smbus_command cmd, void *data); + +#endif diff --git a/src/soc/intel/common/block/imc/spd_access.c b/src/soc/intel/common/block/imc/spd_access.c new file mode 100644 index 0000000..31cc484 --- /dev/null +++ b/src/soc/intel/common/block/imc/spd_access.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/bsd/cb_err.h> +#include <intelblocks/imc.h> +#include <soc/pci_devs.h> +#include <spd_bin.h> + +#include "imclib.h" + +int spd_read_byte(u8 slave_addr, u8 bus_addr) +{ + uint8_t value; + + if (imc_smbus_spd_xfer(IMC_SPD_DEV, slave_addr, bus_addr, IMC_DEVICE_EEPROM, IMC_DATA_BYTE, + IMC_CONTROLLER_ID0, IMC_READ, &value) == CB_SUCCESS) { + return value; + } + + return -1; +} + +int spd_read_word(u8 slave_addr, u8 bus_addr) +{ + uint16_t value = 0; + + if (imc_smbus_spd_xfer(IMC_SPD_DEV, slave_addr, bus_addr, IMC_DEVICE_EEPROM, IMC_DATA_WORD, + IMC_CONTROLLER_ID0, IMC_READ, &value) == CB_SUCCESS) { + return value; + } + + return -1; +} + +void spd_write_byte(u8 slave_addr, u8 bus_addr, u8 value) +{ + imc_smbus_spd_xfer(IMC_SPD_DEV, slave_addr, bus_addr, IMC_DEVICE_WP_EEPROM, + IMC_DATA_BYTE, IMC_CONTROLLER_ID0, IMC_WRITE, &value); +} diff --git a/src/soc/intel/common/block/include/intelblocks/imc.h b/src/soc/intel/common/block/include/intelblocks/imc.h index 1607794..50ae6df 100644 --- a/src/soc/intel/common/block/include/intelblocks/imc.h +++ b/src/soc/intel/common/block/include/intelblocks/imc.h @@ -1,25 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci.h> -#include <stdint.h> +#include <device/pci_type.h> #ifndef SOC_INTEL_COMMON_BLOCK_IMC_H #define SOC_INTEL_COMMON_BLOCK_IMC_H -enum smbus_command { IMC_READ, IMC_WRITE }; +void imc_spd_smbus_init(pci_devfn_t dev); -enum access_width { IMC_DATA_BYTE, IMC_DATA_WORD }; - -enum memory_controller_id { IMC_CONTROLLER_ID0 = 0, IMC_CONTROLLER_ID1 }; - -enum device_type_id { - IMC_DEVICE_TSOD = 0x3, - IMC_DEVICE_WP_EEPROM = 0x6, - IMC_DEVICE_EEPROM = 0xa -}; - -/* Initiate SMBus/I2C transaction to DIMM EEPROM */ -int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, - enum device_type_id dti, enum access_width width, - enum memory_controller_id mcid, enum smbus_command cmd, void *data); #endif diff --git a/src/soc/intel/common/block/smbus/Makefile.mk b/src/soc/intel/common/block/smbus/Makefile.mk index dd56814..2ef3a5b 100644 --- a/src/soc/intel/common/block/smbus/Makefile.mk +++ b/src/soc/intel/common/block/smbus/Makefile.mk @@ -1,10 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c @@ -15,3 +13,8 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c + +ifneq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_IMC),y) +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c +endif diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index deb09b3..cf60e64 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -52,7 +52,9 @@ return -1; } - if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { + /* IMC doesn't support i2c eeprom read. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || + i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); spd_read(spd, addr); } @@ -62,7 +64,9 @@ /* Switch to page 1 */ spd_write_byte(SPD_PAGE_1, 0, 0); - if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + /* IMC doesn't support i2c eeprom read. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || + i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); spd_read(spd + SPD_PAGE_LEN, addr); } @@ -78,7 +82,10 @@ { u8 i; for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { - if (blk->addr_map[i] == 0) { + /** + * Slave address 0 is also available for IMC based SPD SMBus. + */ + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) && blk->addr_map[i] == 0) { blk->spd_array[i] = NULL; continue; } -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 35 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add SPI driver support
by 9elements QA (Code Review) 09 Nov '24

09 Nov '24

9elements QA has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84930?usp=email ) Change subject: soc/mediatek/mt8196: Add SPI driver support ...................................................................... Patch Set 11: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/224088 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/224086 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/224085 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/224084 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/224083 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/224082 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/224081 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/224080 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/224079 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/224078 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/224077 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/224076 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/84930?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Gerrit-Change-Number: 84930 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 09 Nov 2024 10:20:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: include/spd_bin.h: Add SPD IO layer
by Lean Sheng Tan (Code Review) 09 Nov '24

09 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84201?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: include/spd_bin.h: Add SPD IO layer ...................................................................... include/spd_bin.h: Add SPD IO layer By default, PCH SMBus codes will be called to retrieve SPD data. This patch adds a SPD IO layer so that SoC could implement its specific SPD IO layer functions such as using Integrated Memory Controller to get SPD data. Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84201 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/Makefile.mk M src/soc/intel/common/block/smbus/smbuslib.c A src/soc/intel/common/block/smbus/spd_access.c 4 files changed, 40 insertions(+), 15 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c51e449..434d674 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -49,6 +49,10 @@ void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +int spd_read_byte(u8 slave_addr, u8 bus_addr); +int spd_read_word(u8 slave_addr, u8 bus_addr); +void spd_write_byte(u8 slave_addr, u8 bus_addr, u8 value); + /* * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4. * return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present. diff --git a/src/soc/intel/common/block/smbus/Makefile.mk b/src/soc/intel/common/block/smbus/Makefile.mk index 777d92a..dd56814 100644 --- a/src/soc/intel/common/block/smbus/Makefile.mk +++ b/src/soc/intel/common/block/smbus/Makefile.mk @@ -1,8 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += spd_access.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index aff6fb0..deb09b3 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -20,7 +20,7 @@ blk->len = SPD_PAGE_LEN; } -static void smbus_read_spd(u8 *spd, u8 addr) +static void spd_read(u8 *spd, u8 addr) { u16 i; u8 step = 1; @@ -31,9 +31,9 @@ for (i = 0; i < SPD_PAGE_LEN; i += step) { if (CONFIG(SPD_READ_BY_WORD)) ((u16*)spd)[i / sizeof(uint16_t)] = - smbus_read_word(addr, i); + spd_read_word(addr, i); else - spd[i] = smbus_read_byte(addr, i); + spd[i] = spd_read_byte(addr, i); } } @@ -42,11 +42,11 @@ { if (CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Restore to page 0 before reading */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } /* If address is not 0, it will return CB_ERR(-1) if no dimm */ - if (smbus_read_byte(addr, 0) < 0) { + if (spd_read_byte(addr, 0) < 0) { printk(BIOS_INFO, "No memory dimm at address %02X\n", addr << 1); return -1; @@ -54,20 +54,20 @@ if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd, addr); + spd_read(spd, addr); } /* Check if module is DDR4, DDR4 spd is 512 byte. */ if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); + spd_write_byte(SPD_PAGE_1, 0, 0); if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd + SPD_PAGE_LEN, addr); + spd_read(spd + SPD_PAGE_LEN, addr); } /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } return 0; } @@ -109,11 +109,11 @@ if (CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Restore to page 0 before reading */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } /* If dimm is not present, set sn to 0xff. */ - smbus_ret = smbus_read_byte(addr, SPD_DRAM_TYPE); + smbus_ret = spd_read_byte(addr, SPD_DRAM_TYPE); if (smbus_ret < 0) { printk(BIOS_INFO, "No memory dimm at address %02X\n", addr << 1); *sn = 0xffffffff; @@ -125,17 +125,17 @@ /* Check if module is DDR4, DDR4 spd is 512 byte. */ if (dram_type == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); + spd_write_byte(SPD_PAGE_1, 0, 0); for (i = 0; i < SPD_SN_LEN; i++) - *((u8 *)sn + i) = smbus_read_byte(addr, + *((u8 *)sn + i) = spd_read_byte(addr, i + DDR4_SPD_SN_OFF); /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + spd_write_byte(SPD_PAGE_0, 0, 0); } else if (dram_type == SPD_DRAM_DDR3) { for (i = 0; i < SPD_SN_LEN; i++) - *((u8 *)sn + i) = smbus_read_byte(addr, + *((u8 *)sn + i) = spd_read_byte(addr, i + DDR3_SPD_SN_OFF); } else { printk(BIOS_ERR, "Unsupported dram_type\n"); diff --git a/src/soc/intel/common/block/smbus/spd_access.c b/src/soc/intel/common/block/smbus/spd_access.c new file mode 100644 index 0000000..f37e313 --- /dev/null +++ b/src/soc/intel/common/block/smbus/spd_access.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/smbus_host.h> +#include <spd_bin.h> + +int spd_read_byte(u8 slave_addr, u8 bus_addr) +{ + return smbus_read_byte(slave_addr, bus_addr); +} + +int spd_read_word(u8 slave_addr, u8 bus_addr) +{ + return smbus_read_word(slave_addr, bus_addr); +} + +void spd_write_byte(u8 slave_addr, u8 bus_addr, u8 value) +{ + smbus_write_byte(slave_addr, bus_addr, value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Gerrit-Change-Number: 84201 Gerrit-PatchSet: 17 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: include/device/pci_def.h: Add PCIe SRIOV definitions
by Lean Sheng Tan (Code Review) 09 Nov '24

09 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83319?usp=email ) ( 19 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: include/device/pci_def.h: Add PCIe SRIOV definitions ...................................................................... include/device/pci_def.h: Add PCIe SRIOV definitions Add SRIOV related definitions from section 9.3 of PCI Express Base Specification Revision 6.2. Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83319 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/include/device/pci_def.h 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 6d61e6d..6748b35 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -478,6 +478,7 @@ #define PCIE_EXT_CAP_LTR_ID 0x0018 #define PCIE_EXT_CAP_RESIZABLE_BAR 0x0015 #define PCIE_EXT_CAP_RCECEA_ID 0x0007 +#define PCIE_EXT_CAP_SRIOV_ID 0x0010 /* Secondary PCI Express Extended Capability Structure */ #define PCI_EXP_SEC_CAP_ID 0x19 @@ -580,6 +581,16 @@ #define PCI_RCECEA_BUSNUM 8 /* + * Single Root IO Virtualization + * Section 9.3 of PCI Express Base Specification Revision 6.2. + */ +#define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0x0e +#define PCIE_EXT_CAP_SRIOV_SUPPORTED_PAGE_SIZE 0x1c +#define PCIE_EXT_CAP_SRIOV_SYSTEM_PAGE_SIZE 0x20 +#define PCIE_EXT_CAP_SRIOV_VF_BAR0 0x24 +#define PCIE_EXT_CAP_SRIOV_VF_BAR5 0x38 + +/* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded * in a single byte as follows: -- To view, visit https://review.coreboot.org/c/coreboot/+/83319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013 Gerrit-Change-Number: 83319 Gerrit-PatchSet: 31 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com>

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[S] Change in coreboot[main]: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER
by Lean Sheng Tan (Code Review) 09 Nov '24

09 Nov '24

Attention is currently required from: Wonkyu Kim, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/84200?usp=email ) Change subject: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af Gerrit-Change-Number: 84200 Gerrit-PatchSet: 5 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Sat, 09 Nov 2024 10:19:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Lean Sheng Tan (Code Review) 09 Nov '24

09 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... soc/intel/common/systemagent_server: Add server platform system agent Intel server processors have a different system agent design, it has some differences with client platform such as (1) no BDSM and BGSM registers; (2) different alignment size and bit fields in TOLUD, TOUUD and TSEG registers. Thus this patch adds a new common block for server platform system agent. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83318 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/intel/common/block/include/intelblocks/systemagent_server.h A src/soc/intel/common/block/systemagent-server/Kconfig A src/soc/intel/common/block/systemagent-server/Makefile.mk A src/soc/intel/common/block/systemagent-server/common.c A src/soc/intel/common/block/systemagent-server/memmap.c A src/soc/intel/common/block/systemagent-server/systemagent.c A src/soc/intel/common/block/systemagent-server/systemagent_early.c 7 files changed, 417 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent_server.h b/src/soc/intel/common/block/include/intelblocks/systemagent_server.h new file mode 100644 index 0000000..7623282 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/systemagent_server.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_SA_SERVER_H +#define SOC_INTEL_COMMON_BLOCK_SA_SERVER_H + +#include <device/device.h> +#include <device/pci_type.h> +#include <stdbool.h> +#include <stdint.h> + +enum sa_server_reg { + MMCFG_BASE_REG, + MMCFG_LIMIT_REG, + TSEG_BASE_REG, + TSEG_LIMIT_REG, + TOCM_REG, + TOUUD_REG, + TOLUD_REG, + MMIO_L_REG, + VT_BAR_REG, + DPR_REG, + NUM_MAP_ENTRIES, /* Must be last. */ +}; + +/** + * SoC implementation to convert register index to SoC-specific register PCIe configuration + * space offset. + */ +uint32_t sa_server_soc_reg_to_pci_offset(enum sa_server_reg reg); + +struct sa_server_mem_map_descriptor { + uint32_t reg_offset; /* PCI configuration space offset. */ + bool is_64_bit; /* If register is 64 bit. */ + bool is_limit; /* If lower bits should be treated as 1s or 0s but always read as 0s. */ + uint32_t alignment; /* Alignment of the address in register. Probing as PCI BAR if 0. */ +}; + +uint64_t sa_server_read_map_entry(pci_devfn_t dev, + const struct sa_server_mem_map_descriptor *entry); + +struct sa_server_mmio_descriptor { + uint64_t base; + uint64_t size; + bool (*get_resource)(struct device *dev, uint64_t *base, uint64_t *size); + const char *description; /* Name of the register. */ +}; + +uintptr_t sa_server_get_tseg_base(void); + +size_t sa_server_get_tseg_size(void); + +uint64_t sa_server_get_touud(void); + +uintptr_t sa_server_get_tolud(void); + +/* + * API to determine whether system agent is on PCH domain or accelerators domains. + */ +bool sa_server_is_on_pch_domain(const struct device *dev); + +/* + * API to add MMIO resources based on `struct sa_mmio_descriptor` provided by SoC. + */ +void sa_server_add_mmio_resources( + struct device *dev, int *resource_cnt, + const struct sa_server_mmio_descriptor *sa_server_fixed_resources, size_t count); + +/** + * SoC call to provide all known fixed memory ranges for system agent. + * + * SoC function should provide fixed resource ranges in form of + * `struct sa_server_mmio_descriptor` along with resource count. + */ +void sa_server_soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); + +#endif // SOC_INTEL_COMMON_BLOCK_SA_SERVER_H diff --git a/src/soc/intel/common/block/systemagent-server/Kconfig b/src/soc/intel/common/block/systemagent-server/Kconfig new file mode 100644 index 0000000..2f84b63 --- /dev/null +++ b/src/soc/intel/common/block/systemagent-server/Kconfig @@ -0,0 +1,24 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_BLOCK_SA_SERVER + bool + help + Intel Server Processor common System Agent support + +if SOC_INTEL_COMMON_BLOCK_SA_SERVER + +config TOUUD_LIMIT + bool + default y + help + Specify if the lower bits in top of upper usable DRAM register should be + treated as 1s. + +config TOLUD_LIMIT + bool + default y + help + Specify if the lower bits in top of lower usable DRAM register should be + treated as 1s. + +endif diff --git a/src/soc/intel/common/block/systemagent-server/Makefile.mk b/src/soc/intel/common/block/systemagent-server/Makefile.mk new file mode 100644 index 0000000..497c687 --- /dev/null +++ b/src/soc/intel/common/block/systemagent-server/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += common.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += memmap.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += systemagent_early.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += common.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += memmap.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += systemagent.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += systemagent_early.c diff --git a/src/soc/intel/common/block/systemagent-server/common.c b/src/soc/intel/common/block/systemagent-server/common.c new file mode 100644 index 0000000..a564f3b --- /dev/null +++ b/src/soc/intel/common/block/systemagent-server/common.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <device/pci_ops.h> +#include <intelblocks/systemagent_server.h> + +static uint32_t pci_moving_config32(pci_devfn_t dev, unsigned int reg) +{ + uint32_t value, ones, zeroes; + + value = pci_read_config32(dev, reg); + + pci_write_config32(dev, reg, 0xffffffff); + ones = pci_read_config32(dev, reg); + + pci_write_config32(dev, reg, 0x00000000); + zeroes = pci_read_config32(dev, reg); + + pci_write_config32(dev, reg, value); + + return ones ^ zeroes; +} + +uint64_t sa_server_read_map_entry(pci_devfn_t dev, + const struct sa_server_mem_map_descriptor *entry) +{ + uint64_t value = 0; + uint32_t alignment = entry->alignment; + + if (entry->is_64_bit) { + value = pci_s_read_config32(dev, entry->reg_offset + 4); + value <<= 32; + } + + value |= pci_s_read_config32(dev, entry->reg_offset); + + /** + * Probe the alignment if not provided, promising the lower bits are read only, otherwise + * SoC should give a initial value. + */ + if (!alignment) + alignment = ~pci_moving_config32(dev, entry->reg_offset) + 1; + + /** + * If register stores the limit address, where lower bits are read as 0s but treated as 1s, + * restore the lower bits and align it up. + */ + if (entry->is_limit) + value = ALIGN_UP(value + alignment - 1, alignment); + else + value = ALIGN_DOWN(value, alignment); + + return value; +} diff --git a/src/soc/intel/common/block/systemagent-server/memmap.c b/src/soc/intel/common/block/systemagent-server/memmap.c new file mode 100644 index 0000000..6fc14a0 --- /dev/null +++ b/src/soc/intel/common/block/systemagent-server/memmap.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/romstage.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <intelblocks/systemagent_server.h> + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = sa_server_get_tseg_base(); + *size = sa_server_get_tseg_size(); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + /* + * `postcar_mtrr_setup()` will be skipped if using FSP to tear down CAR. + */ + if (!CONFIG(NO_FSP_TEMP_RAM_EXIT)) + return; + + /* + * Add MTRR for ramstage, TSEG and extended BIOS region if exiting CAR without FSP is supporated. + */ + _Static_assert(!CONFIG(NO_FSP_TEMP_RAM_EXIT), + "NO_FSP_TEMP_RAM_EXIT is not supportted currently!"); +} diff --git a/src/soc/intel/common/block/systemagent-server/systemagent.c b/src/soc/intel/common/block/systemagent-server/systemagent.c new file mode 100644 index 0000000..e0c9d4d --- /dev/null +++ b/src/soc/intel/common/block/systemagent-server/systemagent.c @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/vga.h> +#include <commonlib/bsd/helpers.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_type.h> +#include <fsp/util.h> +#include <intelblocks/acpi.h> +#include <intelblocks/systemagent_server.h> +#include <security/intel/txt/txt_register.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> + +__weak void sa_server_soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt) +{ +} + +__weak unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + return current; +} + +uint64_t sa_server_get_touud(void) +{ + struct sa_server_mem_map_descriptor touud_descriptor = { + .reg_offset = sa_server_soc_reg_to_pci_offset(TOUUD_REG), + .is_64_bit = true, + .is_limit = CONFIG(TOUUD_LIMIT), + }; + + return sa_server_read_map_entry(PCI_BDF(SA_DEV_ROOT), &touud_descriptor); +} + +uintptr_t sa_server_get_tolud(void) +{ + struct sa_server_mem_map_descriptor tolud_descriptor = { + .reg_offset = sa_server_soc_reg_to_pci_offset(TOLUD_REG), + .is_limit = CONFIG(TOLUD_LIMIT), + }; + + return sa_server_read_map_entry(PCI_BDF(SA_DEV_ROOT), &tolud_descriptor); +} + +bool sa_server_is_on_pch_domain(const struct device *dev) +{ + return is_dev_on_domain0(dev); +} + +void sa_server_add_mmio_resources(struct device *dev, int *resource_cnt, + const struct sa_server_mmio_descriptor *mmio_descriptors, + size_t count) +{ + int index = *resource_cnt; + uint64_t base, size; + + for (int i = 0; i < count; i++) { + base = mmio_descriptors[i].base; + size = mmio_descriptors[i].size; + + /** + * Prefer to using `base` and `size` to retrieving them from `get_resource()` since + * some MMIO resources may not stored in any registers and registers may hold an + * incorrect value. + */ + if (!size) + if (!mmio_descriptors[i].get_resource || + !mmio_descriptors[i].get_resource(dev, &base, &size)) + continue; + + printk(BIOS_DEBUG, + "SA MMIO resource: %-8s -> base = 0x%08llx, size = 0x%08llx\n", + mmio_descriptors[i].description, base, size); + + mmio_range(dev, index++, base, size); + } + + *resource_cnt = index; +} + +/* + * Host Memory Map: + * +--------------------------+ + * | MMIOH | + * | (relocatable) | + * +--------------------------+ TOUUD + * | High DRAM | + * +--------------------------+ 4GB (0x1_0000_0000) + * | Firmware | + * +--------------------------+ 0xFF00_0000 + * | Reserved | + * +--------------------------+ 0xFEF0_0000 + * | Local xAPIC | + * +--------------------------+ 0xFEE0_0000 + * | HPET, Intel TXT, TPM | + * +--------------------------+ 0xFED0_0000 + * | I/O xAPIC | + * +--------------------------+ 0xFEC0_0000 + * | Reserved | + * +--------------------------+ MMIOL + * | MMIOL | + * | (relocatable) | + * +--------------------------+ + * | PCIe MMCFG | + * | (relocatable) | + * +--------------------------+ TOLUD + * | MESEG (relocatable) | + * +--------------------------+ + * | TSEG (relocatable) | + * +--------------------------+ + * | DMA Protected Range | + * | (relocatable) | + * +--------------------------+ DPR base, 1M aligned + * | Unused memory (possible) | + * +--------------------------+ cbmem_top + * | FSP Bootloader TOLUM | + * +--------------------------+ + * | FSP Reserved | + * +--------------------------+ top_of_ram + * | Low DRAM | + * | Legacy ISA hole | + * +--------------------------+ 0x10_0000 (1MB) + * | C, D, E, F segments | + * +--------------------------+ 0xC_0000 + * | VGA (TSEG, MESEG) | + * +--------------------------+ 0xA_0000 + * | DOS Range | + * +--------------------------+ 0 + */ +static void sa_server_add_dram_resources(struct device *dev, int *resource_cnt) +{ + int index = *resource_cnt; + + /* 0 - > 0xa0000 */ + ram_from_to(dev, index++, 0, 0xa0000); + + /* 0xa0000 - > 0xc0000 */ + mmio_range(dev, index++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - > 1MB */ + reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); + + /* 1MB -> top_of_ram (FSP reserved base) */ + struct range_entry fsp_mem; + fsp_find_reserved_memory(&fsp_mem); + uint32_t top_of_ram = range_entry_base(&fsp_mem); + ram_from_to(dev, index++, 1 * MiB, top_of_ram); + + /* top_of_ram -> cbmem_top, including FSP reserved and bootloader TOLUM. */ + ram_from_to(dev, index++, top_of_ram, cbmem_top()); + + /* Mark cbmem_top to TOLUD as reserved, SoC should provide more details for this ranges. */ + reserved_ram_from_to(dev, index++, cbmem_top(), sa_server_get_tolud()); + + /* 4GB -> TOUUD */ + upper_ram_end(dev, index++, sa_server_get_touud()); + + *resource_cnt = index; +} + +static void sa_server_read_resources(struct device *dev) +{ + int index = 0; + + pci_dev_read_resources(dev); + + /* + * Only add DRAM resource when calling from PCH domain. + */ + if (sa_server_is_on_pch_domain(dev)) + sa_server_add_dram_resources(dev, &index); + + /* Add all SoC fixed MMIO resources. */ + sa_server_soc_add_fixed_mmio_resources(dev, &index); +} + +struct device_operations systemagent_server_ops = { + .read_resources = sa_server_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = sa_write_acpi_tables, +#endif +}; + +static const unsigned short systemagent_server_ids[] = { + PCI_DID_INTEL_SNR_ID, + 0 +}; + +static const struct pci_driver systemagent_server_driver __pci_driver = { + .ops = &systemagent_server_ops, + .vendor = PCI_VID_INTEL, + .devices = systemagent_server_ids +}; diff --git a/src/soc/intel/common/block/systemagent-server/systemagent_early.c b/src/soc/intel/common/block/systemagent-server/systemagent_early.c new file mode 100644 index 0000000..5cbadfc --- /dev/null +++ b/src/soc/intel/common/block/systemagent-server/systemagent_early.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <commonlib/bsd/helpers.h> +#include <device/pci_ops.h> +#include <intelblocks/systemagent_server.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> + +uintptr_t sa_server_get_tseg_base(void) +{ + struct sa_server_mem_map_descriptor tseg_descriptor = { + .reg_offset = sa_server_soc_reg_to_pci_offset(TSEG_BASE_REG), + }; + + return sa_server_read_map_entry(SA_DEV_ROOT, &tseg_descriptor); +} + +size_t sa_server_get_tseg_size(void) +{ + struct sa_server_mem_map_descriptor tseg_descriptor = { + .reg_offset = sa_server_soc_reg_to_pci_offset(TSEG_LIMIT_REG), + .is_limit = true, + }; + + return sa_server_read_map_entry(SA_DEV_ROOT, &tseg_descriptor) - + sa_server_get_tseg_base(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 31 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com>

1 0

[M] Change in coreboot[main]: [only for test] use errno_t
by Elyes Haouas (Code Review) 09 Nov '24

09 Nov '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85060?usp=email ) Change subject: [only for test] use errno_t ...................................................................... [only for test] use errno_t Change-Id: I97208106f801899f5e0de019d1de8ccf56513f36 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M payloads/libpayload/Makefile M payloads/libpayload/curses/PDCurses/x11/pdcx11.c M payloads/libpayload/curses/curses.priv.h M payloads/libpayload/curses/menu/mf_common.h M payloads/libpayload/libc/string.c M payloads/libpayload/tests/Makefile.mk M src/commonlib/bsd/include/commonlib/bsd/stdlib.h M src/lib/libgcov.c M util/amdfwtool/amdfwtool.c M util/amdfwtool/handle_file.c M util/amdfwtool/signed_psp.c M util/archive/archive.c M util/bucts/bucts.c M util/cbfstool/Makefile.mk M util/cbfstool/cse_fpt.c M util/cbfstool/cse_serger.c M util/cbfstool/flashmap/fmap.c M util/cbfstool/lz4/lib/Makefile M util/cbmem/cbmem.c M util/intelmetool/mmap.c M util/intelmetool/msr.c M util/inteltool/cpu.c M util/inteltool/inteltool.c M util/inteltool/ivy_memory.c M util/intelvbttool/intelvbttool.c M util/kconfig/conf.c M util/kconfig/confdata.c M util/kconfig/expr.c M util/kconfig/mconf.c M util/kconfig/nconf.h M util/marvell/doimage_mv/doimage.c M util/msrtool/darwin.c M util/msrtool/freebsd.c M util/msrtool/linux.c M util/msrtool/msrtool.c M util/nvramtool/common.h M util/pmh7tool/pmh7tool.c M util/post/post.c M util/sconfig/sconfig.h M util/smmstoretool/main.c M util/smmstoretool/utils.c M util/superiotool/Makefile M util/supermicro/smcbiosinfo/smcbiosinfo.c 44 files changed, 26 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85060/1 diff --git a/Makefile.mk b/Makefile.mk index ca79d05..a576049 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -507,7 +507,7 @@ CFLAGS_common += -pipe CFLAGS_common += -g CFLAGS_common += -nostdinc -CFLAGS_common += -std=gnu11 +CFLAGS_common += -std=gnu23 CFLAGS_common += -nostdlib CFLAGS_common += -Wall CFLAGS_common += -Wundef diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index afe38dc..8805a19 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -216,7 +216,7 @@ AR := $(AR_$(ARCH-y)) endif -CFLAGS += -std=gnu11 $(CFLAGS_$(ARCH-y)) +CFLAGS += -std=gnu23 $(CFLAGS_$(ARCH-y)) ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) diff --git a/payloads/libpayload/curses/PDCurses/x11/pdcx11.c b/payloads/libpayload/curses/PDCurses/x11/pdcx11.c index 370cedb..e8b02e1 100644 --- a/payloads/libpayload/curses/PDCurses/x11/pdcx11.c +++ b/payloads/libpayload/curses/PDCurses/x11/pdcx11.c @@ -4,7 +4,6 @@ RCSID("$Id: pdcx11.c,v 1.96 2008/07/14 04:24:52 wmcbrine Exp $") -#include <errno.h> #include <stdlib.h> /*** Functions that are called by both processes ***/ @@ -73,6 +72,7 @@ int XC_read_socket(int sock_num, void *buf, int len) { int start = 0, length = len, rc; + errno_t err = 0; PDC_LOG(("%s:XC_read_socket called: sock_num %d len %d\n", XCLOGMSG, sock_num, len)); @@ -84,9 +84,9 @@ #ifdef MOUSE_DEBUG if (sock_num == xc_key_sock) printf("%s:XC_read_socket(key) rc %d errno %d " - "resized: %d\n", XCLOGMSG, rc, errno, SP->resized); + "resized: %d\n", XCLOGMSG, rc, err, SP->resized); #endif - if (rc < 0 && sock_num == xc_key_sock && errno == EINTR + if (rc < 0 && sock_num == xc_key_sock && err == EINTR && SP->resized != FALSE) { MOUSE_LOG(("%s:continuing\n", XCLOGMSG)); diff --git a/payloads/libpayload/curses/curses.priv.h b/payloads/libpayload/curses/curses.priv.h index 31ec80f..a9afee3 100644 --- a/payloads/libpayload/curses/curses.priv.h +++ b/payloads/libpayload/curses/curses.priv.h @@ -80,12 +80,6 @@ //// #include <assert.h> #include <stdio.h> -#include <errno.h> - -#if DECL_ERRNO -extern int errno; -#endif - //// #include <nc_panel.h> //// //// /* Some systems have a broken 'select()', but workable 'poll()'. Use that */ diff --git a/payloads/libpayload/curses/menu/mf_common.h b/payloads/libpayload/curses/menu/mf_common.h index d40c7b9..bdaed76 100644 --- a/payloads/libpayload/curses/menu/mf_common.h +++ b/payloads/libpayload/curses/menu/mf_common.h @@ -45,11 +45,6 @@ #include <assert.h> #include <string.h> #include <ctype.h> -#include <errno.h> - -#if DECL_ERRNO -extern int errno; -#endif /* in case of debug version we ignore the suppression of assertions */ #ifdef TRACE diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index a1b7d4d..0a94b12 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -33,7 +33,7 @@ #include <ctype.h> #include <inttypes.h> #include <limits.h> -#include <errno.h> +#include <stdlib.h> /** * Compare two strings. diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk index a6cee5f..03125cc 100644 --- a/payloads/libpayload/tests/Makefile.mk +++ b/payloads/libpayload/tests/Makefile.mk @@ -48,7 +48,7 @@ TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type -TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -std=gnu23 -ffunction-sections -fdata-sections -fno-builtin ifneq ($(filter-out 0,$(DEBUG)),) TEST_CFLAGS += -Og -ggdb3 diff --git a/src/commonlib/bsd/include/commonlib/bsd/stdlib.h b/src/commonlib/bsd/include/commonlib/bsd/stdlib.h index c497b5c..38ecf7c 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/stdlib.h +++ b/src/commonlib/bsd/include/commonlib/bsd/stdlib.h @@ -13,6 +13,16 @@ #define printk(level, ...) printf(__VA_ARGS__) #endif +#ifndef __ERRNO_T_DEFINED +#define __ERRNO_T_DEFINED + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L +#include <errno.h> +#else + typedef int errno_t; +#endif +#endif /* __ERRNO_T_DEFINED */ + void __noreturn abort(void); void free(void *ptr); void *malloc(size_t size); diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index 61304ff..74e00da 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -99,7 +99,6 @@ #include <string.h> #if GCOV_LOCKED #include <fcntl.h> -#include <errno.h> #include <sys/stat.h> #endif #else diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 7f17b71..9a10472 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -71,7 +71,6 @@ #include <commonlib/bsd/helpers.h> #include <fcntl.h> -#include <errno.h> #include <limits.h> #include <stdbool.h> #include <stdio.h> diff --git a/util/amdfwtool/handle_file.c b/util/amdfwtool/handle_file.c index c37bb2c..81ac4ce 100644 --- a/util/amdfwtool/handle_file.c +++ b/util/amdfwtool/handle_file.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <fcntl.h> -#include <errno.h> #include <limits.h> #include <stdio.h> #include <sys/stat.h> diff --git a/util/amdfwtool/signed_psp.c b/util/amdfwtool/signed_psp.c index 24f76e8..30b3c74 100644 --- a/util/amdfwtool/signed_psp.c +++ b/util/amdfwtool/signed_psp.c @@ -2,7 +2,6 @@ #include <assert.h> #include <fcntl.h> -#include <errno.h> #include <limits.h> #include <openssl/sha.h> #include <stdio.h> diff --git a/util/archive/archive.c b/util/archive/archive.c index f877632..3939a44 100644 --- a/util/archive/archive.c +++ b/util/archive/archive.c @@ -2,7 +2,6 @@ #include "archive.h" #include <endian.h> -#include <errno.h> #include <libgen.h> #include <stdint.h> #include <stdio.h> diff --git a/util/bucts/bucts.c b/util/bucts/bucts.c index 2bd1c5d..6c9a81f 100644 --- a/util/bucts/bucts.c +++ b/util/bucts/bucts.c @@ -8,7 +8,6 @@ #include <stdlib.h> #include <stdint.h> #include <string.h> -#include <errno.h> #include <unistd.h> #include <sys/mman.h> #if defined(__GLIBC__) diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk index 8577874..b207523 100644 --- a/util/cbfstool/Makefile.mk +++ b/util/cbfstool/Makefile.mk @@ -140,10 +140,10 @@ TOOLCFLAGS += -mno-ms-bitfields endif ifeq ($(shell uname -o 2>/dev/null), Cygwin) -TOOLCFLAGS+=-std=gnu11 +TOOLCFLAGS+=-std=gnu23 TOOLCPPFLAGS+=-D_GNU_SOURCE else -TOOLCFLAGS+=-std=c11 +TOOLCFLAGS+=-std=c2x endif LZ4CFLAGS ?= -Wno-strict-prototypes diff --git a/util/cbfstool/cse_fpt.c b/util/cbfstool/cse_fpt.c index 51fa9d0..525aba2 100644 --- a/util/cbfstool/cse_fpt.c +++ b/util/cbfstool/cse_fpt.c @@ -3,7 +3,6 @@ #include <commonlib/endian.h> #include <getopt.h> -#include <errno.h> #include <stdlib.h> #include <sys/stat.h> #include <sys/types.h> diff --git a/util/cbfstool/cse_serger.c b/util/cbfstool/cse_serger.c index 9d74a12..fe1528f 100644 --- a/util/cbfstool/cse_serger.c +++ b/util/cbfstool/cse_serger.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* CSE Serger - Tool for stitching Intel CSE components */ -#include <errno.h> #include <getopt.h> #include <stdlib.h> #include <sys/stat.h> diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index 46c31bb..052063b 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -9,7 +9,6 @@ #include <sys/types.h> #include <sys/stat.h> #include <sys/mman.h> -#include <errno.h> #include <inttypes.h> #include <limits.h> #include <assert.h> diff --git a/util/cbfstool/lz4/lib/Makefile b/util/cbfstool/lz4/lib/Makefile index ed59577..288c14e 100644 --- a/util/cbfstool/lz4/lib/Makefile +++ b/util/cbfstool/lz4/lib/Makefile @@ -20,7 +20,7 @@ PREFIX ?= /usr/local CPPFLAGS= -DXXH_NAMESPACE=LZ4_ CFLAGS ?= -O3 -CFLAGS += -std=c99 -Wall -Wextra -Wundef -Wshadow -Wcast-align -Wcast-qual -Wstrict-prototypes -pedantic +CFLAGS += -std=c2x -Wall -Wextra -Wundef -Wshadow -Wcast-align -Wcast-qual -Wstrict-prototypes -pedantic FLAGS = $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) LIBDIR?= $(PREFIX)/lib diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 15b6770..ac35f23 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -8,7 +8,6 @@ #include <unistd.h> #include <getopt.h> #include <dirent.h> -#include <errno.h> #include <fcntl.h> #include <ctype.h> #include <arpa/inet.h> diff --git a/util/intelmetool/mmap.c b/util/intelmetool/mmap.c index 988085e..d572edc 100644 --- a/util/intelmetool/mmap.c +++ b/util/intelmetool/mmap.c @@ -2,7 +2,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include "mmap.h" -#include <errno.h> +#include <stdlib.h> #include <string.h> #ifndef __DARWIN__ diff --git a/util/intelmetool/msr.c b/util/intelmetool/msr.c index 1a5ead9..d9648e1 100644 --- a/util/intelmetool/msr.c +++ b/util/intelmetool/msr.c @@ -6,7 +6,6 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> -#include <errno.h> #include "msr.h" diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index ecd3eb4..cc65bd1 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -7,7 +7,6 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> -#include <errno.h> #include <limits.h> #include "inteltool.h" diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index b7dbd62..c4f22d1 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -9,7 +9,6 @@ #include <fcntl.h> #include <sys/mman.h> #include <unistd.h> -#include <errno.h> #include <limits.h> #include "inteltool.h" #include "pcr.h" diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 15d3a10..8be914d 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -4,7 +4,7 @@ #include <stdlib.h> #include <string.h> #include <inttypes.h> -#include <errno.h> + #include "inteltool.h" extern volatile uint8_t *mchbar; diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index a70b33c..910dd16 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -10,7 +10,6 @@ #include <sys/stat.h> #include <fcntl.h> #include <getopt.h> -#include <errno.h> #include <stdarg.h> #include <commonlib/helpers.h> diff --git a/util/kconfig/conf.c b/util/kconfig/conf.c index 8499143..23a87f9 100644 --- a/util/kconfig/conf.c +++ b/util/kconfig/conf.c @@ -12,7 +12,6 @@ #include <unistd.h> #include <getopt.h> #include <sys/time.h> -#include <errno.h> #include "lkc.h" diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 0105917..1aa3b3d 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -7,7 +7,6 @@ #include <sys/stat.h> #include <sys/types.h> #include <ctype.h> -#include <errno.h> #include <fcntl.h> #include <limits.h> #include <stdarg.h> diff --git a/util/kconfig/expr.c b/util/kconfig/expr.c index 22bc337..d3bf040 100644 --- a/util/kconfig/expr.c +++ b/util/kconfig/expr.c @@ -4,7 +4,6 @@ */ #include <ctype.h> -#include <errno.h> #include <stdio.h> #include <stdlib.h> #include <string.h> diff --git a/util/kconfig/mconf.c b/util/kconfig/mconf.c index d921223..ba12d70 100644 --- a/util/kconfig/mconf.c +++ b/util/kconfig/mconf.c @@ -9,7 +9,6 @@ */ #include <ctype.h> -#include <errno.h> #include <fcntl.h> #include <limits.h> #include <stdarg.h> diff --git a/util/kconfig/nconf.h b/util/kconfig/nconf.h index 174b035..2408b2e 100644 --- a/util/kconfig/nconf.h +++ b/util/kconfig/nconf.h @@ -6,7 +6,6 @@ */ #include <ctype.h> -#include <errno.h> #include <fcntl.h> #include <limits.h> #include <stdarg.h> diff --git a/util/marvell/doimage_mv/doimage.c b/util/marvell/doimage_mv/doimage.c index 5ead1f8..28b8bb2 100644 --- a/util/marvell/doimage_mv/doimage.c +++ b/util/marvell/doimage_mv/doimage.c @@ -15,7 +15,6 @@ disclaimer. *******************************************************************************/ -#include <errno.h> #include <fcntl.h> #include <stdio.h> #include <stdlib.h> diff --git a/util/msrtool/darwin.c b/util/msrtool/darwin.c index 051ef3b..6867405 100644 --- a/util/msrtool/darwin.c +++ b/util/msrtool/darwin.c @@ -5,7 +5,7 @@ #include <fcntl.h> #include <unistd.h> #include <string.h> -#include <errno.h> +#include <stdlib.h> #include "msrtool.h" diff --git a/util/msrtool/freebsd.c b/util/msrtool/freebsd.c index f1afc9a..0cfc351 100644 --- a/util/msrtool/freebsd.c +++ b/util/msrtool/freebsd.c @@ -5,7 +5,7 @@ #include <fcntl.h> #include <unistd.h> #include <string.h> -#include <errno.h> +#include <stdlib.h> #include "msrtool.h" diff --git a/util/msrtool/linux.c b/util/msrtool/linux.c index b2b7bdd..5a800a9 100644 --- a/util/msrtool/linux.c +++ b/util/msrtool/linux.c @@ -5,7 +5,7 @@ #include <fcntl.h> #include <unistd.h> #include <string.h> -#include <errno.h> +#include <stdlib.h> #include "msrtool.h" diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 02c641f..4005264 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -7,7 +7,6 @@ #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> -#include <errno.h> #include <pci/pci.h> #include "msrtool.h" diff --git a/util/nvramtool/common.h b/util/nvramtool/common.h index e15138c..3f1440c 100644 --- a/util/nvramtool/common.h +++ b/util/nvramtool/common.h @@ -6,7 +6,6 @@ #include <sys/types.h> #include <sys/stat.h> #include <assert.h> -#include <errno.h> #include <unistd.h> #include <fcntl.h> #include <stdint.h> diff --git a/util/pmh7tool/pmh7tool.c b/util/pmh7tool/pmh7tool.c index 346edae..1d2be00 100644 --- a/util/pmh7tool/pmh7tool.c +++ b/util/pmh7tool/pmh7tool.c @@ -4,7 +4,6 @@ #include <stdlib.h> #include <getopt.h> #include <sys/io.h> -#include <errno.h> #include <string.h> #include <unistd.h> #include <stdint.h> diff --git a/util/post/post.c b/util/post/post.c index 8578d04..fdc9e37 100644 --- a/util/post/post.c +++ b/util/post/post.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <errno.h> #include <limits.h> #include <stdarg.h> #include <stdio.h> diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 5fc8b4f..c220fc0 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -7,7 +7,6 @@ #include <string.h> #include <sys/types.h> #include <unistd.h> -#include <errno.h> #include <stdbool.h> struct resource; diff --git a/util/smmstoretool/main.c b/util/smmstoretool/main.c index 89d58d6..bdccdae 100644 --- a/util/smmstoretool/main.c +++ b/util/smmstoretool/main.c @@ -2,7 +2,6 @@ #include <unistd.h> -#include <errno.h> #include <stdbool.h> #include <stdint.h> #include <stdio.h> diff --git a/util/smmstoretool/utils.c b/util/smmstoretool/utils.c index 9f554e0..2bf4c6e 100644 --- a/util/smmstoretool/utils.c +++ b/util/smmstoretool/utils.c @@ -7,7 +7,6 @@ #include <fcntl.h> #include <unistd.h> -#include <errno.h> #include <limits.h> #include <stdbool.h> #include <stddef.h> diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 39839d9..2420c81 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -12,7 +12,7 @@ VERSION := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"' CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ - -Werror-implicit-function-declaration -std=c11 -pedantic $(VERSION) \ + -Werror-implicit-function-declaration -std=c2x -pedantic $(VERSION) \ -Wno-variadic-macros -I $(TOP)/src/commonlib/bsd/include LDFLAGS += -lz diff --git a/util/supermicro/smcbiosinfo/smcbiosinfo.c b/util/supermicro/smcbiosinfo/smcbiosinfo.c index 6a27ba7..96674dd 100644 --- a/util/supermicro/smcbiosinfo/smcbiosinfo.c +++ b/util/supermicro/smcbiosinfo/smcbiosinfo.c @@ -8,7 +8,6 @@ #include <sys/types.h> #include <sys/stat.h> #include <getopt.h> -#include <errno.h> #include <stdarg.h> /* Place the following struct somewhere in the ROM: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85060?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97208106f801899f5e0de019d1de8ccf56513f36 Gerrit-Change-Number: 85060 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Subrata Banik (Code Review) 09 Nov '24

09 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... mb/google/fatcat: Add ISH support with FW_CONFIG toggle This patch adds support for the Integrated Sensor Hub (ISH) on the Fatcat mainboard. ISH can be enabled or disabled via FW_CONFIG bit 24. This allows for flexible configuration depending on the system requirements. The GPIO configuration for ISH is also updated based on CBI settings, ensuring correct initialization and communication. Verified that the device tree correctly probes ISH based on the FW_CONFIG setting: * FW_CONFIG with bit 24 set: ISH is probed successfully. * FW_CONFIG with bit 24 cleared: ISH is not probed. BUG=b:370984186 TEST=Verified ISH probing behavior with different FW_CONFIG settings using CBI. Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 4 files changed, 46 insertions(+), 16 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index bc68972..04ea54d 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -40,6 +40,7 @@ def_bool n select BOARD_GOOGLE_FATCAT_COMMON select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_INTEL_ISH select DRIVERS_INTEL_USB4_RETIMER select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 46ef6a8..f3fd5d2 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -453,6 +453,24 @@ PAD_NC(GPP_F18, NONE), }; +static const struct pad_config ish_disable_pads[] = { + /* GPP_D05: NC */ + PAD_NC(GPP_D05, NONE), + /* GPP_D06: NC */ + PAD_NC(GPP_D06, NONE), + /* GPP_E05: NC */ + PAD_NC(GPP_E05, NONE), +}; + +static const struct pad_config ish_enable_pads[] = { + /* GPP_D05: ISH_UART0_RXD */ + PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), + /* GPP_D06: ISH_UART0_TXD */ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), + /* GPP_E05: ISH_GP_7_SNSR_HDR */ + PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4), +}; + void fw_config_configure_pre_mem_gpio(void) { if (!fw_config_is_provisioned()) { @@ -578,6 +596,11 @@ else GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads); + if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE))) + GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads); + else + GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads); + /* NOTE: disable PEG (x8 slot) and x4 slot wake for now */ GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads); } diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index b76db5a..7833fe8 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -163,14 +163,10 @@ PAD_CFG_GPO(GPP_D03, 1, PLTRST), /* GPP_D04: IMGCLKOUT_0 */ PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), - /* GPP_D05: ISH_SPI_CS_N_SNSR_HDR */ - PAD_CFG_NF(GPP_D05, NONE, DEEP, NF3), - /* GPP_D06: ISH_SPI_CLK_SNSR_HDR */ - PAD_CFG_NF(GPP_D06, NONE, DEEP, NF3), - /* GPP_D07: ISH_SPI_MISO_SNSR_HDR */ - PAD_CFG_NF(GPP_D07, NONE, DEEP, NF3), - /* GPP_D08: ISH_SPI_MOSI_SNSR_HDR */ - PAD_CFG_NF(GPP_D08, NONE, DEEP, NF3), + /* GPP_D07: NC */ + PAD_NC(GPP_D07, NONE), + /* GPP_D08: NC */ + PAD_NC(GPP_D08, NONE), /* GPP_D09: PEG_SLOT_RST_N */ PAD_CFG_GPO(GPP_D09, 1, PLTRST), /* GPP_D10: HDA_BCLK */ @@ -212,8 +208,6 @@ PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL), /* GPP_E03: M2_GEN5_SSD_RESET_N */ PAD_CFG_GPO(GPP_E03, 1, PLTRST), - /* GPP_E05: ISH_GP_7_SNSR_HDR */ - PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4), /* GPP_E06: SECURE_CAM_SW */ PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI), /* GPP_E07: Not used */ @@ -274,8 +268,8 @@ PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), /* GPP_F08: TCH_PNL1_PWR_EN */ PAD_CFG_GPO(GPP_F08, 1, PLTRST), - /* GPP_F09: ISH_INT_GP11_CVS */ - PAD_CFG_NF(GPP_F09, NONE, DEEP, NF4), + /* GPP_F09: NC */ + PAD_NC(GPP_F09, NONE), /* GPP_F10: PEG_SLOT_PWR_EN_N */ PAD_CFG_GPO(GPP_F10, 0, PLTRST), /* GPP_F11: MOD_TCSS2_TYP_A_VBUS_EN */ @@ -329,10 +323,10 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* GPP_H13: CPU_C10_GATE_N_R */ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - /* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */ - PAD_CFG_NF(GPP_H14, NONE, DEEP, NF4), - /* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */ - PAD_CFG_NF(GPP_H15, NONE, DEEP, NF4), + /* GPP_H14: NC */ + PAD_NC(GPP_H14, NONE), + /* GPP_H15: NC */ + PAD_NC(GPP_H15, NONE), /* GPP_H16: WWAN_PWREN */ PAD_CFG_GPO(GPP_H16, 1, PLTRST), /* GPP_H17: MIC MUTE LED */ diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index efea054..bed928e 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -62,6 +62,10 @@ option WFC_MIPI 1 option WFC_USB 2 end + field ISH 24 + option ISH_DISABLE 0 + option ISH_ENABLE 1 + end end chip soc/intel/pantherlake @@ -227,6 +231,14 @@ end end + device ref ish on + probe ISH ISH_ENABLE + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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