coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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1925 discussions

[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Jarried Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Runyang Chen. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84896?usp=email ) Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84896/comment/cc19f187_668fb822?us… : PS5, Line 12: If the interrupt is not handled, it will cause the system fail to boot. > Either move this to the previous line, or add a blank line above to start a new paragraph. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 02 Nov 2024 07:15:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Jarried Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Runyang Chen. Hello Hung-Te Lin, Runyang Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84896?usp=email to look at the new patch set (#6). Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... soc/mediatek/mt8196: Disable irq2axi feature Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled by checking /proc/interrupts. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 --- M src/mainboard/google/rauru/romstage.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/irq2axi.h A src/soc/mediatek/mt8196/irq2axi.c 4 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84896/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Jarried Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Guangjie Song, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84497?usp=email to look at the new patch set (#25). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... soc/mediatek/mt8196: Add mtcmos init support Add mtcmos init code and APIs for controlling power domain. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h A src/soc/mediatek/mt8196/mtcmos.c 5 files changed, 993 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84497/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 25 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and Clock init support
by Jarried Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Paul Menzel. Hello Guangjie Song, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84495?usp=email to look at the new patch set (#25). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PLL and Clock init support ...................................................................... soc/mediatek/mt8196: Add PLL and Clock init support Add PLL and clock init code, frequency meter and APIs for raising little CPU frequency and set tvdpll frequency. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/pll.c 6 files changed, 2,260 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84495/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/84495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Gerrit-Change-Number: 84495 Gerrit-PatchSet: 25 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add devicetree for MAX98357A codec
by Subrata Banik (Code Review) 02 Nov '24

02 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84888?usp=email ) Change subject: mb/google/fatcat: Add devicetree for MAX98357A codec ...................................................................... mb/google/fatcat: Add devicetree for MAX98357A codec Update device tree to support speaker o/p on MAX98357A AIC. BUG=b:357011633 TEST=build coreboot image and test audio playback on Google/Fatcat board. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84888 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index f47e5a5..bc68972 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -53,6 +53,7 @@ config BOARD_GOOGLE_MODEL_FATCAT def_bool n select BOARD_GOOGLE_BASEBOARD_FATCAT + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index bcaf92a..efea054 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -614,6 +614,14 @@ end end end + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO AUDIO_MAX98360_ALC5682I_I2S + end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/84888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200 Gerrit-Change-Number: 84888 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: configure espi alarm gpio
by Subrata Banik (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Pranava Y N, Sukumar Ghorai. Subrata Banik has posted comments on this change by Sukumar Ghorai. ( https://review.coreboot.org/c/coreboot/+/84957?usp=email ) Change subject: mb/google/fatcat: configure espi alarm gpio ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84957/comment/88509bb2_1f2b5e20?us… : PS3, Line 7: configure espi alarm gpio looks like you are configuring BT_RF_KILL_N from GPO to NC. I'm unable to find the mapping between BT_RF_KILL_N and eSPI Alarm GPIO. As per Platform mapping doc, GPP_A16 is BT_RF_KILL_N. -- To view, visit https://review.coreboot.org/c/coreboot/+/84957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Gerrit-Change-Number: 84957 Gerrit-PatchSet: 3 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 02 Nov 2024 04:46:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Disable package c-state auto-demotion
by Subrata Banik (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Pranava Y N, Sukumar Ghorai. Subrata Banik has posted comments on this change by Sukumar Ghorai. ( https://review.coreboot.org/c/coreboot/+/84956?usp=email ) Change subject: mb/google/fatcat: Disable package c-state auto-demotion ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84956/comment/449086e1_38352ab8?us… : PS1, Line 42: demotion nit: auto-demotion https://review.coreboot.org/c/coreboot/+/84956/comment/63de2e24_f633b961?us… : PS1, Line 43: register "disable_package_c_state_demotion" = "true" initially when this was implemented in ADL, I thought this is a W/A and we won't need this in future soc, but looks like this is now a new norm ? description from Brya platform ``` # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84956?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01f2cb8ac1093ae98cc076e35ad1924baa53aa59 Gerrit-Change-Number: 84956 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 02 Nov 2024 04:42:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/common: Refactor `struct tracker`
by Yidi Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84958?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/common: Refactor `struct tracker` ...................................................................... soc/mediatek/common: Refactor `struct tracker` Rather than using a static array size for the `offset` variable, use a pointer named `offsets` that points to a dynamically allocated array. A separate variable called `offset_size` stores the size of this array. TEST=emerge-corsola coreboot && emerge-geralt coreboot Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/tracker_common.h M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v1.c M src/soc/mediatek/common/tracker_v2.c 4 files changed, 20 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/84958/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Gerrit-Change-Number: 84958 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add devicetree for MAX98357A codec
by Subrata Banik (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N. Subrata Banik has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/84888?usp=email ) Change subject: mb/google/fatcat: Add devicetree for MAX98357A codec ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS2: > can we please merge this change ? this CL was rebased on top of CB:84863 which was not CR+2 therefore, noone can merge this CL without testing there is zero dependency and no rebase to maintain such dependency relationship. -- To view, visit https://review.coreboot.org/c/coreboot/+/84888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200 Gerrit-Change-Number: 84888 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 02 Nov 2024 03:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Use write32p and read32p for tracker
by Yidi Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84959?usp=email ) Change subject: soc/mediatek/common: Use write32p and read32p for tracker ...................................................................... soc/mediatek/common: Use write32p and read32p for tracker TEST=emerge-geralt coreboot Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v2.c 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/84959/1 diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 1341d5a..be83999 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -21,7 +21,7 @@ for (j = 0; j < TRACKER_NUM; j++) { tra = &tracker_data[j]; - if (!(read32((void *)(tra->base_addr)) & tra->timeout)) + if (!(read32p(tra->base_addr) & tra->timeout)) continue; printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); @@ -29,7 +29,7 @@ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offsets[k] + i * 4; - printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); + printk(BIOS_INFO, "%#lx:%#x,", reg, read32p(reg)); if (i % 4 == 3 || i == size - 1) printk(BIOS_INFO, "\n"); diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c index 415cd0b..5eb9974 100644 --- a/src/soc/mediatek/common/tracker_v2.c +++ b/src/soc/mediatek/common/tracker_v2.c @@ -61,16 +61,16 @@ * peri tracker clock: 78MHz */ val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0, val); + write32p(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1, val); val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0, val); + write32p(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1, val); /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1, 1 << BUS_TRACE_EN); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2, 1 << BUS_TRACE_EN); /* * Enable infra/peri tracker. @@ -81,6 +81,6 @@ * bit[14] - BUS_OT_WEN_CTRL */ val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1, val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2, val); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Gerrit-Change-Number: 84959 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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coreboot-gerrit November 2024