coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Naveen M (Code Review) 10 Nov '24

10 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N, Subrata Banik, Varun Upadhyay. Naveen M has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/2c02438f_4ca2f862?us… : PS2, Line 8: AUDIO_ALC721_SNDW > > The external Audio Card (ALC721) goes to Link 3 (SND3) while the onboard ALC722 goes to link 1(SND […] Hello Subrata, Please find the config.star configuration, ucm_suffix for RT722 & RT721 depends on this coreboot configuration. https://chrome-internal-review.googlesource.com/c/chromeos/project/fatcat/f… -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 10 Nov 2024 15:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Subrata Banik (Code Review) 10 Nov '24

10 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N, Varun Upadhyay. Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/7af6c3d9_0e824dce?us… : PS2, Line 8: AUDIO_ALC721_SNDW > The external Audio Card (ALC721) goes to Link 3 (SND3) while the onboard ALC722 goes to link 1(SND1). That's the reason defined separate FW_CONFIG. can you please check is this a static configuration that OS driver has relied on ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 10 Nov 2024 15:48:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Varun Upadhyay (Code Review) 10 Nov '24

10 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N, Subrata Banik. Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/6e7d32f5_5c1a549d?us… : PS2, Line 8: AUDIO_ALC721_SNDW > knowing we can have either one AIC between ALC721 or ALC722 while both selects the same driver, do w […] The external Audio Card (ALC721) goes to Link 3 (SND3) while the onboard ALC722 goes to link 1(SND1). That's the reason defined separate FW_CONFIG. -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 10 Nov 2024 15:10:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: sconfig: Move (WEAK_)DEV_PTR from device.h to static.h
by Felix Singer (Code Review) 10 Nov '24

10 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84676?usp=email ) Change subject: sconfig: Move (WEAK_)DEV_PTR from device.h to static.h ...................................................................... sconfig: Move (WEAK_)DEV_PTR from device.h to static.h Similar to commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), move these macros to static.h to separate dependencies on device.h and static.h. These macros resolve to device alises that are declared in the generated static_devices.h header, so move them to static.h which includes static_devices.h. Since static.h remains included in device.h, any source that uses these macros should still compile correctly. Subsequent commits will add static.h to files that need them, after which static.h can be dropped from device.h. Change-Id: I1c76ad749769591da9c102b11eb618e93b68bd7c Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84676 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/include/device/device.h M util/sconfig/main.c 2 files changed, 9 insertions(+), 9 deletions(-) Approvals: Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/include/device/device.h b/src/include/device/device.h index b52be54..6b4f64c 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -502,12 +502,4 @@ void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus); -/* Macro to generate `struct device *` name that points to a device with the given alias. */ -#define DEV_PTR(_alias) _dev_##_alias##_ptr - -/* Macro to generate weak `struct device *` definition that points to a device with the given - alias. */ -#define WEAK_DEV_PTR(_alias) \ - __weak DEVTREE_CONST struct device *const DEV_PTR(_alias) - #endif /* DEVICE_H */ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 677b9d2..fc2aa73 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1906,7 +1906,15 @@ fprintf(f, "#include <%s>\n\n", device_header); fprintf(f, "/* Returns pointer to config structure of root device (B:D:F = 0:00:0) */\n"); - fprintf(f, "#define config_of_soc() __pci_0_00_0_config\n"); + fprintf(f, "#define config_of_soc() __pci_0_00_0_config\n\n"); + + fprintf(f, "/* Macro to generate `struct device *` name that points to a device with the given alias. */\n"); + fprintf(f, "#define DEV_PTR(_alias) \t_dev_##_alias##_ptr\n\n"); + + fprintf(f, "/* Macro to generate weak `struct device *` definition that points to a device with the given\n"); + fprintf(f, " alias. */\n"); + fprintf(f, "#define WEAK_DEV_PTR(_alias)\t\t\t\\\n"); + fprintf(f, "\t__weak DEVTREE_CONST struct device *const DEV_PTR(_alias)\n"); fprintf(f, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84676?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c76ad749769591da9c102b11eb618e93b68bd7c Gerrit-Change-Number: 84676 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc
by Felix Singer (Code Review) 10 Nov '24

10 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84609?usp=email ) Change subject: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc ...................................................................... soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84609 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/meteorlake/cpu.c M src/soc/intel/meteorlake/espi.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/pmc.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/systemagent.c M src/soc/intel/meteorlake/tcss.c M src/soc/intel/pantherlake/acpi.c M src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/cpu.c M src/soc/intel/pantherlake/espi.c M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/pmc.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/pantherlake/romstage/fsp_params.c M src/soc/intel/pantherlake/systemagent.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/fsp_params.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/pmc.c M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/lpc.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 44 files changed, 44 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index a3ee198..e3aa44e 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -20,6 +20,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index d2011f9..a0a1399 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -24,6 +24,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/tcss.h> +#include <static.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index e990ae3..4a74be0 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> bool cpu_soc_is_in_untrusted_mode(void) { diff --git a/src/soc/intel/meteorlake/espi.c b/src/soc/intel/meteorlake/espi.c index a3952a3..98fd9fc 100644 --- a/src/soc/intel/meteorlake/espi.c +++ b/src/soc/intel/meteorlake/espi.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> +#include <static.h> void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 0ae36e6..5bd28aa 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -32,6 +32,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> #include <stdlib.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/meteorlake/pmc.c b/src/soc/intel/meteorlake/pmc.c index 5c4fa2c..837a8f3 100644 --- a/src/soc/intel/meteorlake/pmc.c +++ b/src/soc/intel/meteorlake/pmc.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdint.h> #include <bootstate.h> diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 09fb46b..8e91b27 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 917503e..bc7c20b 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -26,6 +26,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> #include <string.h> #include <ux_locales.h> diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 774a99f..bb841aa 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -12,6 +12,7 @@ #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * SoC implementation diff --git a/src/soc/intel/meteorlake/tcss.c b/src/soc/intel/meteorlake/tcss.c index 7509504..3d46f0a 100644 --- a/src/soc/intel/meteorlake/tcss.c +++ b/src/soc/intel/meteorlake/tcss.c @@ -2,6 +2,7 @@ #include <intelblocks/tcss.h> #include <soc/soc_chip.h> +#include <static.h> const struct soc_tcss_ops tcss_ops = { .configure_aux_bias_pads = ioe_tcss_configure_aux_bias_pads_sbi, diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index c49555b..5df3ef9 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -20,6 +20,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 2202878..61e00fa 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -24,6 +24,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/tcss.h> +#include <static.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c index 1b81856..9109263 100644 --- a/src/soc/intel/pantherlake/cpu.c +++ b/src/soc/intel/pantherlake/cpu.c @@ -20,6 +20,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> bool cpu_soc_is_in_untrusted_mode(void) { diff --git a/src/soc/intel/pantherlake/espi.c b/src/soc/intel/pantherlake/espi.c index 02bec6f..d5b5cf9 100644 --- a/src/soc/intel/pantherlake/espi.c +++ b/src/soc/intel/pantherlake/espi.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> +#include <static.h> void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index 1c764fa..eaef582 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -16,6 +16,7 @@ #include <soc/intel/common/vbt.h> #include <soc/pcie.h> #include <soc/ramstage.h> +#include <static.h> #define MAX_ONBOARD_PCIE_DEVICES 256 diff --git a/src/soc/intel/pantherlake/pmc.c b/src/soc/intel/pantherlake/pmc.c index 1c1ca5d..de6bf0c 100644 --- a/src/soc/intel/pantherlake/pmc.c +++ b/src/soc/intel/pantherlake/pmc.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdint.h> #define PMC_HID "INTC1026" diff --git a/src/soc/intel/pantherlake/pmutil.c b/src/soc/intel/pantherlake/pmutil.c index 892972c..888bb56 100644 --- a/src/soc/intel/pantherlake/pmutil.c +++ b/src/soc/intel/pantherlake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index f6ba498..b105d3d 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -9,6 +9,7 @@ #include <soc/msr.h> #include <soc/pcie.h> #include <soc/romstage.h> +#include <static.h> #define FSP_CLK_NOTUSED 0xff #define FSP_CLK_LAN 0x70 diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c index 418f41c..e7a0701 100644 --- a/src/soc/intel/pantherlake/systemagent.c +++ b/src/soc/intel/pantherlake/systemagent.c @@ -12,6 +12,7 @@ #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * SoC implementation diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e0381e8..3a60ada 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -17,6 +17,7 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index cc2d384..df00bb8 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,6 +18,7 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> #include <soc/pmc.h> +#include <static.h> #include "../chip.h" #define PCR_DMI_ACPIBA 0x27B4 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d1cc6f9..a6844e0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -28,6 +28,7 @@ #include <soc/ramstage.h> #include <soc/systemagent.h> #include <soc/usb.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 057aece..8f294f7 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index 693218f..5de44d3 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <static.h> #include "chip.h" void soc_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index eea86fc..4b957df 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -10,6 +10,7 @@ #include <soc/iomap.h> #include <soc/pcr_ids.h> #include <soc/intel/common/block/lpc/lpc_def.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 71d1ef0..7c8d7c1 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -11,6 +11,7 @@ #include <intelblocks/rtc.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 5152237..5e7d543 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pmc.h> #include <soc/smbus.h> #include <security/vboot/vbnv.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index f24054a..bd3d086 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -10,6 +10,7 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <static.h> static void cpu_flex_override(FSP_M_CONFIG *m_cfg) { diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index d203bda..3708f05 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -12,6 +12,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index c34b185..dd9ef73 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -19,6 +19,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * List of supported C-states in this processor. diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 64e8b2e..084bd7f 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -27,6 +27,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> +#include <static.h> #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1000 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index f90f8ad..f2ccb48 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -16,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <static.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 3d0f0e9..0c6f36e 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -20,6 +20,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> bool cpu_soc_is_in_untrusted_mode(void) diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 6ef7c6d..3b56e29 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> +#include <static.h> void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index fa95e47..c3400b4 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -27,6 +27,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/tcss.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 0bba1a0..8912cb3 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <bootstate.h> #define PMC_HID "INTC1026" diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index ba33e49..cd22942 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -30,6 +30,7 @@ #include <soc/smbus.h> #include <soc/soc_chip.h> #include <security/vboot/vbnv.h> +#include <static.h> /* * SMI diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 00b5315..5ebd46d 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -16,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <static.h> #include <string.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 06282ea..143fd72 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -17,6 +17,7 @@ #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * SoC implementation diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 8d74240..916e2df 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -9,6 +9,7 @@ #include <soc/pci_devs.h> #include <soc/util.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <static.h> #include <stdint.h> #include <stdio.h> #include <stdlib.h> diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 2a85032..ffcb052 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> #include <soc/soc_util.h> +#include <static.h> #include <string.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index bf1dedd..1b44ddd 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -4,6 +4,7 @@ #include <intelblocks/lpc_lib.h> #include <soc/iomap.h> #include <soc/pcr_ids.h> +#include <static.h> #include <chip.h> diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index 4a8c6b0..21b3522 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -4,6 +4,7 @@ #include <intelblocks/rtc.h> #include <soc/romstage.h> #include <soc/soc_util.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 4d95a33..4438a59 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -18,6 +18,7 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/soc_pch.h> +#include <static.h> #include <string.h> #include <soc/config.h> #include <soc/soc_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/84609?usp=email To unsubscribe, or for help writing mail filters, visit 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[S] Change in coreboot[main]: sconfig: Move (WEAK_)DEV_PTR from device.h to static.h
by Felix Singer (Code Review) 10 Nov '24

10 Nov '24

Attention is currently required from: Martin L Roth, Nicholas Chin. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84676?usp=email ) Change subject: sconfig: Move (WEAK_)DEV_PTR from device.h to static.h ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84676?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c76ad749769591da9c102b11eb618e93b68bd7c Gerrit-Change-Number: 84676 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Nov 2024 10:34:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc
by Felix Singer (Code Review) 10 Nov '24

10 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nicholas Chin, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Shuo Liu, Subrata Banik, Tarun, Tim Chu. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84609?usp=email ) Change subject: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Gerrit-Change-Number: 84609 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 10 Nov 2024 10:32:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brox: Do not select HAVE_ACPI_RESUME
by Bob Moragues (Code Review) 09 Nov '24

09 Nov '24

Attention is currently required from: Edward Hill, Karthik Ramasubramanian, Shyam Sundar Radjacoumar, Subrata Banik. Bob Moragues has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85038?usp=email ) Change subject: mb/google/brox: Do not select HAVE_ACPI_RESUME ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Gerrit-Change-Number: 85038 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Edward Hill <ecgh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 09 Nov 2024 21:11:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 09 Nov '24

09 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nicholas Chin, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Shuo Liu, Subrata Banik, Tarun, Tim Chu. Hello Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Shuo Liu, Subrata Banik, Tarun, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84609?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc ...................................................................... soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/meteorlake/cpu.c M src/soc/intel/meteorlake/espi.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/pmc.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/systemagent.c M src/soc/intel/meteorlake/tcss.c M src/soc/intel/pantherlake/acpi.c M src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/cpu.c M src/soc/intel/pantherlake/espi.c M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/pmc.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/pantherlake/romstage/fsp_params.c M src/soc/intel/pantherlake/systemagent.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/fsp_params.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/pmc.c M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/lpc.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 44 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/84609/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Gerrit-Change-Number: 84609 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot
by Karthik Ramasubramanian (Code Review) 09 Nov '24

09 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email ) Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Gerrit-Change-Number: 84996 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 09 Nov 2024 17:59:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit November 2024