coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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2521 discussions

[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
by Name of user not set (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Angel Pons, Felix Held. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email ) Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/itss/itss.c: https://review.coreboot.org/c/coreboot/+/85012/comment/a53d2756_13e971b1?us… : PS5, Line 138: enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin) > Where is this function used? This function is used to return which PIRQ a device INT pin is routed to. In https://review.coreboot.org/c/coreboot/+/85013, I improved `intel_write_pci_PRT()` so that it could write _PRT method for other domains. To use that function, SoC should read ITSS PCI Interrupt Route (PIR) registers to get connections between INT pin and PIRQ. -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 5 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Nov 2024 02:19:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Jarried Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84932?usp=email ) Change subject: mb/google/rauru: Configure TPM ...................................................................... Patch Set 14: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84932/comment/41bf4d0d_8b3e4c8d?us… : PS11, Line 9: Add TPM support > Add Google Ti50 TPM support Done Commit Message: https://review.coreboot.org/c/coreboot/+/84932/comment/eb670421_06ab97dc?us… : PS13, Line 19: BUG=b:317009620 > move to line 14 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 02:18:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Jarried Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84932?usp=email to look at the new patch set (#14). Change subject: mb/google/rauru: Configure TPM ...................................................................... mb/google/rauru: Configure TPM 1. Add Google Ti50 TPM support 2. Configure I2C speed to I2C_SPEED_FAST_PLUS 3. Pass GPIO_GSC_AP_INT_ODL to the payload 4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now BUG=b:317009620 TEST=build pass, boot ok and there is no CR50 TPM timeout log Pass log: [INFO ] Probing TPM I2C: done! DID_VID 0x504a6666 [DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a) Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/bootblock.c M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 4 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84932/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot
by Eric Lai (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email ) Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Gerrit-Change-Number: 84996 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 11 Nov 2024 02:07:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/telith: Add Fn key scancode
by Eric Lai (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85045?usp=email ) Change subject: mb/google/nissa/var/telith: Add Fn key scancode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85045?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib69af9a8448312b275de46f9c835f8a9d592312a Gerrit-Change-Number: 85045 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 02:05:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER
by Name of user not set (Code Review) 11 Nov '24

11 Nov '24

yuchi.chen(a)intel.com has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84200?usp=email ) Change subject: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER ...................................................................... Abandoned This patch is not needed any since Snow Ridge will use server system agent. -- To view, visit https://review.coreboot.org/c/coreboot/+/84200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af Gerrit-Change-Number: 84200 Gerrit-PatchSet: 5 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[S] Change in coreboot[main]: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro
by Nicholas Chin (Code Review) 10 Nov '24

10 Nov '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85093?usp=email ) Change subject: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro ...................................................................... mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro Use the DEV_PTR macro to resolve devicetree aliases instead of using the autogenerated reference names from sconfig directly. TEST=Timeless build did not change Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/purism/librem_l1um_v2/ramstage.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85093/1 diff --git a/src/mainboard/purism/librem_l1um_v2/ramstage.c b/src/mainboard/purism/librem_l1um_v2/ramstage.c index 87b7822..39c078c 100644 --- a/src/mainboard/purism/librem_l1um_v2/ramstage.c +++ b/src/mainboard/purism/librem_l1um_v2/ramstage.c @@ -26,13 +26,13 @@ * Control Register), but we have to use one of the LDNs as the device * because the chip ops are only assigned to the LDNs. */ - pnp_enter_conf_mode(_dev_nvt_superio_gpio1_ptr); + pnp_enter_conf_mode(DEV_PTR(nvt_superio_gpio1)); printk(BIOS_DEBUG, "GCR 0x2f was: %02X\n", - pnp_read_config(_dev_nvt_superio_gpio1_ptr, 0x2f)); - pnp_write_config(_dev_nvt_superio_gpio1_ptr, 0x2f, 0x00); + pnp_read_config(DEV_PTR(nvt_superio_gpio1), 0x2f)); + pnp_write_config(DEV_PTR(nvt_superio_gpio1), 0x2f, 0x00); printk(BIOS_DEBUG, "GCR 0x2f is now: %02X\n", - pnp_read_config(_dev_nvt_superio_gpio1_ptr, 0x2f)); - pnp_exit_conf_mode(_dev_nvt_superio_gpio1_ptr); + pnp_read_config(DEV_PTR(nvt_superio_gpio1), 0x2f)); + pnp_exit_conf_mode(DEV_PTR(nvt_superio_gpio1)); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21 Gerrit-Change-Number: 85093 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: mb/hardkernel/odroid-h4: Correct number of jacks in hda_verb.c
by Felix Singer (Code Review) 10 Nov '24

10 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85076?usp=email ) Change subject: mb/hardkernel/odroid-h4: Correct number of jacks in hda_verb.c ...................................................................... mb/hardkernel/odroid-h4: Correct number of jacks in hda_verb.c This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I401e94b107612f8b7e8a73b3dbc12d7a5227ef01 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85076 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/hardkernel/odroid-h4/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/hardkernel/odroid-h4/hda_verb.c b/src/mainboard/hardkernel/odroid-h4/hda_verb.c index 0ac706c..c289cdc 100644 --- a/src/mainboard/hardkernel/odroid-h4/hda_verb.c +++ b/src/mainboard/hardkernel/odroid-h4/hda_verb.c @@ -5,7 +5,7 @@ const u32 cim_verb_data[] = { 0x10ec0897, /* Vendor ID: Realtek ALC897 */ 0x10ec0897, /* Subsystem ID */ - 16, /* Number of entries */ + 15, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x10ec0897), AZALIA_PIN_CFG(0, 0x11, 0x40000000), AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), -- To view, visit https://review.coreboot.org/c/coreboot/+/85076?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401e94b107612f8b7e8a73b3dbc12d7a5227ef01 Gerrit-Change-Number: 85076 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Fix typo and missing carriage return character
by Elyes Haouas (Code Review) 10 Nov '24

10 Nov '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85020?usp=email ) Change subject: mb/google/fatcat: Fix typo and missing carriage return character ...................................................................... mb/google/fatcat: Fix typo and missing carriage return character Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85020 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index f3fd5d2..3162df4 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -474,7 +474,7 @@ void fw_config_configure_pre_mem_gpio(void) { if (!fw_config_is_provisioned()) { - printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing"); + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); return; } @@ -519,7 +519,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (!fw_config_is_provisioned()) { - printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing"); + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Gerrit-Change-Number: 85020 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Fix typo and missing carriage return character
by Elyes Haouas (Code Review) 10 Nov '24

10 Nov '24

Attention is currently required from: Jérémy Compostella, Paul Menzel, Pranava Y N, Subrata Banik. Elyes Haouas has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85020?usp=email ) Change subject: mb/google/fatcat: Fix typo and missing carriage return character ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Gerrit-Change-Number: 85020 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 10 Nov 2024 22:07:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit November 2024