coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Elyes Haouas (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Felix Singer, Matt DeVillier. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84986?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84986/comment/495ee0a5_0f4274fa?us… : PS1, Line 9: commit id 68328e2 The SHA-1 references in this auto-generated message use only 7 characters and do not follow the Linux-style convention: commit <12+ chars of sha1> ("<title line>"). Could it be aligned with this standard for consistency across commit messages? https://review.coreboot.org/c/coreboot/+/84986/comment/104cf4a7_3650d955?us… : PS1, Line 12: d793185 same here https://review.coreboot.org/c/coreboot/+/84986/comment/05365355_7877b6e2?us… : PS1, Line 16: d793185 same here -- To view, visit https://review.coreboot.org/c/coreboot/+/84986?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4887f9ce8a76c374aeaa3fb03a8679ba446dff4 Gerrit-Change-Number: 84986 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 07:01:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Hello Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85025?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE ...................................................................... soc/intel/cmn/pmc: Perform PM register init for CSE Before entering FSP-M, AP firmware must ensure the PM1_CNT register reflects the correct sleep state if a global reset occurred. This is crucial when Intel CSE has reset the system, as indicated by the global reset bit and wake status register. If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP firmware must enforce an S5 exit path before handing control to FSP-M for CSE initialization. This ensures proper system initialization and avoids potential issues caused by an inconsistent sleep state. Additionally, clears the PM1 status register (PM1_STS) after retrieving the power state. This prevents stale status information from persisting across power cycles, which could lead to confusion during subsequent boots. BUG=b:265939425 TEST=Verified that `prev_sleep_state` holds the correct value (5 for S5) after CSE performs a global reset. Fixes: Inconsistent sleep state after CSE reset. Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85025/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Gerrit-Change-Number: 85025 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85025?usp=email ) Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE ...................................................................... Patch Set 1: (3 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/85025/comment/8dc6dbab_96bc9f39?us… : PS1, Line 492: ps->pm1_cnt > Should we check again specifically for SLP_TYP bits based on the comment i.e. […] Acknowledged https://review.coreboot.org/c/coreboot/+/85025/comment/8e9ca12a_b63a0787?us… : PS1, Line 495: ps->pm1_cnt = pm1_cnt_value; > Should it be `ps->pm1_cnt | = pm1_cnt_value;` to reflect the value in PM1_CNT? Acknowledged https://review.coreboot.org/c/coreboot/+/85025/comment/621093fb_57db95de?us… : PS1, Line 496: pmc_enable_pm1_control(pm1_cnt_value) > Should we reset all other SLP_TYP, if any, in the PM1_CNT register? Currently this one sets S5 SLP_T […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Gerrit-Change-Number: 85025 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 06:55:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: xcompile: Use Walloc-size GCC option
by Elyes Haouas (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Felix Singer, Martin L Roth, Paul Menzel. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84074?usp=email to look at the new patch set (#12). Change subject: xcompile: Use Walloc-size GCC option ...................................................................... xcompile: Use Walloc-size GCC option Warn about allocation function calls with insufficient size for the target type of the pointer. commit 6ab188ee6c99 (Makefile.mk: Use Walloc-size GCC option) introduced this GCC option, but commit d05fe9fd3ce9 (Revert "Makefile.mk: Use Localiser GCC option") reverted it because older GCC versions did not support it. This change re-enables it for modern GCC versions. Change-Id: If5d36b073bb5b4cccb0cf2b67b43edb3f97f168c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/xcompile/xcompile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84074/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/84074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5d36b073bb5b4cccb0cf2b67b43edb3f97f168c Gerrit-Change-Number: 84074 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config
by V Sowmya (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik, Tarun. V Sowmya has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85028?usp=email ) Change subject: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Gerrit-Change-Number: 85028 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 06:31:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common: Apply Intel recommendation for early ramtop caching
by V Sowmya (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Subrata Banik. V Sowmya has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85027?usp=email ) Change subject: soc/intel/common: Apply Intel recommendation for early ramtop caching ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071 Gerrit-Change-Number: 85027 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 06:31:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/common: Add RAMTOP size in ramtop_table
by V Sowmya (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Subrata Banik. V Sowmya has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85003?usp=email ) Change subject: soc/intel/common: Add RAMTOP size in ramtop_table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16d610c5791895b59da57d543c54da6621617912 Gerrit-Change-Number: 85003 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 06:30:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/google/rex/var/kanix: Add initial GPIO config
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang. Subrata Banik has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85042?usp=email ) Change subject: mb/google/rex/var/kanix: Add initial GPIO config ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id23b836b48925a30b212b444c9f51cfd6166b9f8 Gerrit-Change-Number: 85042 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 06:08:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Generate SPD ID for supported memory part
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang. Subrata Banik has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85040?usp=email ) Change subject: mb/google/rex/var/kanix: Generate SPD ID for supported memory part ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ce92bac8d8e7ed64135c26387f52b7cc488c391 Gerrit-Change-Number: 85040 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 06:07:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
by Jarried Lin (Code Review) 11 Nov '24

11 Nov '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85094?usp=email ) Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K ...................................................................... mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K The DRAMC Parameters size is larger than before, therefore the size of CBFS_MCACHE needs to be increased to avoid mcache overflow. TEST=Build pass BUG=b:317009620 Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/85094/1 diff --git a/src/mainboard/google/rauru/chromeos.fmd b/src/mainboard/google/rauru/chromeos.fmd index 5b2234d..a1595df 100644 --- a/src/mainboard/google/rauru/chromeos.fmd +++ b/src/mainboard/google/rauru/chromeos.fmd @@ -28,9 +28,9 @@ RW_FWID_A 0x100 } RW_MISC 36K { - RW_VPD(PRESERVE) 16K # At least 8K. + RW_VPD(PRESERVE) 8K # At least 8K. RW_NVRAM(PRESERVE) 8K - RW_MRC_CACHE(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 16K RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. } RW_SECTION_B 1500K { -- To view, visit https://review.coreboot.org/c/coreboot/+/85094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Gerrit-Change-Number: 85094 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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coreboot-gerrit November 2024