coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE
by Kapil Porwal (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85025?usp=email ) Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/85025/comment/fd20de64_fb3a5259?us… : PS2, Line 494: /* Clear pending SLP_TYP */ : pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP)); @kramasub@google.com and @subratabanik@google.com I think, we do not need to clear the sleep type here since we got here due to the same reason (SLP_TYP being 0). WDYT? we can also avoid line#497. -- To view, visit https://review.coreboot.org/c/coreboot/+/85025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Gerrit-Change-Number: 85025 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 08:23:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Amanda Hwang, Pranava Y N. Subrata Banik has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/85095?usp=email ) Change subject: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: let me come back with something that is more meaningful here -- To view, visit https://review.coreboot.org/c/coreboot/+/85095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45227cda12009b1cd1294a275393faa48b3e76a7 Gerrit-Change-Number: 85095 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 08:08:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: scripts/update_submodules: Ensure SHA-1 and commit messages align wit...
by Elyes Haouas (Code Review) 11 Nov '24

11 Nov '24

Elyes Haouas has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/85096?usp=email ) Change subject: scripts/update_submodules: Ensure SHA-1 and commit messages align with Linux style ...................................................................... scripts/update_submodules: Ensure SHA-1 and commit messages align with Linux style Replaces the abbreviated SHA-1 (`%h`) with the full SHA-1 (`%H`) truncated to 12 characters to ensure consistent length. Add double quotes around commit titles: `commit <12+ chars of sha1> ("<title line>")`. These changes improve the consistency and readability of auto-generated commit messages for submodule updates. Change-Id: If62ba4e491b75f3dd3bf526787d608040646bcac Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/scripts/update_submodules 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85096/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If62ba4e491b75f3dd3bf526787d608040646bcac Gerrit-Change-Number: 85096 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
by Hung-Te Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Jarried Lin, Yidi Lin. Hung-Te Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85094?usp=email ) Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Gerrit-Change-Number: 85094 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 07:46:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: scripts/update_submodules: Ensure SHA-1 and commit messages align wit...
by Elyes Haouas (Code Review) 11 Nov '24

11 Nov '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85096?usp=email ) Change subject: scripts/update_submodules: Ensure SHA-1 and commit messages align with Linux style ...................................................................... scripts/update_submodules: Ensure SHA-1 and commit messages align with Linux style - Replaces the abbreviated SHA-1 (`%h`) with the full SHA-1 (`%H`) truncated to 12 characters to ensure consistent length. - Updates the commit message format to include double quotes around commit titles: `commit <12+ chars of sha1> ("<title line>")`. These changes improve the consistency and readability of auto-generated commit messages for submodule updates. Change-Id: If62ba4e491b75f3dd3bf526787d608040646bcac Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/scripts/update_submodules 1 file changed, 6 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85096/1 diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules index 9f6c14f..8cbdfb3 100755 --- a/util/scripts/update_submodules +++ b/util/scripts/update_submodules @@ -102,8 +102,8 @@ exit 1 fi - initial_commit_id="$(git log --pretty='%h' -n 1)" - initial_commit_description="$(git log --pretty='%ci - (%s)' -n 1)" + initial_commit_id="$(git log --pretty='%H' -n 1 | cut -c1-12)" + initial_commit_description="$(git log --pretty='%ci - ("%s")' -n 1)" if [[ ${skip_sync} != "1" ]]; then git fetch 2>/dev/null fi @@ -116,8 +116,8 @@ fi done - updated_commit_id="$(git log --pretty='%h' -n 1 "${branch_name}" -- )" - updated_commit_description="$(git log --pretty='%ci - (%s)' -n 1 "${updated_commit_id}")" + updated_commit_id="$(git log --pretty='%H' -n 1 "${branch_name}" -- | cut -c1-12)" + updated_commit_description="$(git log --pretty='%ci - ("%s")' -n 1 "${updated_commit_id}")" if [ "${initial_commit_id}" = "${updated_commit_id}" ]; then echo "No updates for ${submodule}" continue @@ -140,11 +140,9 @@ git commit -s -F- > /dev/null 2>&1 <<-EOF Update ${submodule##*/} submodule to upstream ${branch##*/} - Updating from commit id ${initial_commit_id}: - $initial_commit_description + Updating from commit ${initial_commit_id} ("$(echo $initial_commit_description)"): - to commit id ${updated_commit_id}: - ${updated_commit_description} + to commit ${updated_commit_id} ("$(echo $updated_commit_description)"): This brings in ${update_count} new commits${new_commit_terminator} ${update_log} -- To view, visit https://review.coreboot.org/c/coreboot/+/85096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If62ba4e491b75f3dd3bf526787d608040646bcac Gerrit-Change-Number: 85096 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
by Yu-Ping Wu (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85094?usp=email ) Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85094/comment/449857eb_e64a42ba?us… : PS1, Line 9: The DRAMC Parameters size is larger than before, therefore the size of : CBFS_MCACHE needs to be increased to avoid mcache overflow. Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is larger (xxx bytes) compared to previous SoCs (yyy bytes), enlarge RW_MRC_CACHE from 8K to 16K. -- To view, visit https://review.coreboot.org/c/coreboot/+/85094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Gerrit-Change-Number: 85094 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 07:27:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
by Angel Pons (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Felix Held, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email ) Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/itss/itss.c: https://review.coreboot.org/c/coreboot/+/85012/comment/904183e3_33ac7aeb?us… : PS5, Line 138: enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin) > This function is used to return which PIRQ a device INT pin is routed to. In https://review. […] Huh, I don't see `itss_get_dev_pirq` getting called in CB:85013 though. -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 6 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Nov 2024 07:26:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F
by Eric Lai (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Amanda Hwang, Pranava Y N, Subrata Banik. Eric Lai has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/85095?usp=email ) Change subject: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I think this can update in variant.c. -- To view, visit https://review.coreboot.org/c/coreboot/+/85095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45227cda12009b1cd1294a275393faa48b3e76a7 Gerrit-Change-Number: 85095 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 07:15:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F
by Amanda Hwang (Code Review) 11 Nov '24

11 Nov '24

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85095?usp=email ) Change subject: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F ...................................................................... mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F Due to the hardware limitation on francka, reduce the memory speed to 7467 MT/s. BUG=b:373394046 TEST=emerge-fatcat coreboot Change-Id: I45227cda12009b1cd1294a275393faa48b3e76a7 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85095/1 diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c index 7b56e28..ac7de54 100644 --- a/src/mainboard/google/fatcat/romstage.c +++ b/src/mainboard/google/fatcat/romstage.c @@ -32,5 +32,8 @@ memset(&spd_info, 0, sizeof(spd_info)); variant_get_spd_info(&spd_info); +#if CONFIG(BOARD_GOOGLE_FRANCKA) + memupd->FspmConfig.DdrFreqLimit = 7467; +#endif memcfg_init(memupd, mem_config, &spd_info, half_populated); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45227cda12009b1cd1294a275393faa48b3e76a7 Gerrit-Change-Number: 85095 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Increase DEV_MEM memory range to 16GB
by Yu-Ping Wu (Code Review) 11 Nov '24

11 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85035?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common: Increase DEV_MEM memory range to 16GB ...................................................................... soc/mediatek/common: Increase DEV_MEM memory range to 16GB Map a proper DRAM range for memory test during calibration. TEST=memory test passed on Rauru BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/85035 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/mmu_operations.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index cbd6c09..be216f6 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -19,11 +19,11 @@ mmu_init(); /* - * Set 0x0 to 8GB address as device memory. We want to config IO_PHYS + * Set 0x0 to 16GB address as device memory. We want to config IO_PHYS * address to DEV_MEM, and map a proper range of dram for the memory * test during calibration. */ - mmu_config_range((void *)0, (uintptr_t)8U * GiB, DEV_MEM); + mmu_config_range((void *)0, (uintptr_t)16U * GiB, DEV_MEM); /* SRAM is cached */ mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM); -- To view, visit https://review.coreboot.org/c/coreboot/+/85035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef Gerrit-Change-Number: 85035 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2024