coreboot-gerrit November 2024

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[S] Change in coreboot[main]: nb/via/cx700: Add south module devices to chipset.cb
by Lean Sheng Tan (Code Review) 11 Nov '24

11 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82767?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/via/cx700: Add south module devices to chipset.cb ...................................................................... nb/via/cx700: Add south module devices to chipset.cb Change-Id: Ibd7a7b8c9e1461fa665bb72082489b9a48da63c3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82767 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/via/cx700/chipset.cb 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/northbridge/via/cx700/chipset.cb b/src/northbridge/via/cx700/chipset.cb index 4dd11f3..25c2f11 100644 --- a/src/northbridge/via/cx700/chipset.cb +++ b/src/northbridge/via/cx700/chipset.cb @@ -12,6 +12,19 @@ device pci 00.0 alias vga off end end + device pci 0f.0 alias ata off end + device pci 10.0 alias uhci0 off end + device pci 10.1 alias uhci1 off end + device pci 10.2 alias uhci2 off end + device pci 10.4 alias ehci off end + device pci 11.0 alias lpc on end + device pci 11.6 alias mc97 off end + device pci 11.7 alias south_end on end + device pci 13.0 alias pcie off + device pci 01.0 alias hda off end + end + device pci 13.1 alias south_pci off end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/82767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd7a7b8c9e1461fa665bb72082489b9a48da63c3 Gerrit-Change-Number: 82767 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: cpu/via: Implement cache as RAM
by Lean Sheng Tan (Code Review) 11 Nov '24

11 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82766?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu/via: Implement cache as RAM ...................................................................... cpu/via: Implement cache as RAM The overall procedure is taken from the original code that was removed in commit 4c38ed3c38ac (cpu/via/nano: Drop support). Boilerplate at the start and end was updated (expect timestamp and BIST result in `xmm*' registers), stack is aligned to 16B, and linker symbols are now used for the CAR and cached XIP ranges. Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82766 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/via/c7/Kconfig M src/cpu/via/car/cache_as_ram.S 2 files changed, 161 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index df81b3f..b6a970b 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -14,4 +14,10 @@ config DCACHE_BSP_STACK_SIZE default 0x1000 +config DCACHE_RAM_BASE + default 0xffef0000 + +config DCACHE_RAM_SIZE + default 0x10000 + endif diff --git a/src/cpu/via/car/cache_as_ram.S b/src/cpu/via/car/cache_as_ram.S index 5c5066d..9a2cec4 100644 --- a/src/cpu/via/car/cache_as_ram.S +++ b/src/cpu/via/car/cache_as_ram.S @@ -1,13 +1,167 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -.section .init, "ax", @progbits +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +.section .init .global bootblock_pre_c_entry .code32 +_cache_as_ram_setup: + bootblock_pre_c_entry: + +cache_as_ram: + post_code(POSTCODE_BOOTBLOCK_CAR) + + /* Disable cache. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + invd + + /* Set the default memory type and enable fixed and variable MTRRs. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + xorl %edx, %edx + movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + wrmsr + + /* Clear all MTRRs. */ + xorl %edx, %edx + movl $all_mtrr_msrs, %esi + +clear_fixed_var_mtrr: + lodsl (%esi), %eax + testl %eax, %eax + jz clear_fixed_var_mtrr_out + + movl %eax, %ecx + xorl %eax, %eax + wrmsr + + jmp clear_fixed_var_mtrr + +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRR_FIX_64K_00000 + .long MTRR_FIX_16K_80000 + .long MTRR_FIX_16K_A0000 + .long MTRR_FIX_4K_C0000 + .long MTRR_FIX_4K_C8000 + .long MTRR_FIX_4K_D0000 + .long MTRR_FIX_4K_D8000 + .long MTRR_FIX_4K_E0000 + .long MTRR_FIX_4K_E8000 + .long MTRR_FIX_4K_F0000 + .long MTRR_FIX_4K_F8000 + + /* var MTRR MSRs */ + .long MTRR_PHYS_BASE(0) + .long MTRR_PHYS_MASK(0) + .long MTRR_PHYS_BASE(1) + .long MTRR_PHYS_MASK(1) + .long MTRR_PHYS_BASE(2) + .long MTRR_PHYS_MASK(2) + .long MTRR_PHYS_BASE(3) + .long MTRR_PHYS_MASK(3) + .long MTRR_PHYS_BASE(4) + .long MTRR_PHYS_MASK(4) + .long MTRR_PHYS_BASE(5) + .long MTRR_PHYS_MASK(5) + .long MTRR_PHYS_BASE(6) + .long MTRR_PHYS_MASK(6) + .long MTRR_PHYS_BASE(7) + .long MTRR_PHYS_MASK(7) + + .long 0x000 /* NULL, end of table */ + +clear_fixed_var_mtrr_out: + movl $MTRR_PHYS_BASE(0), %ecx + xorl %edx, %edx + movl $_car_mtrr_start, %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRR_PHYS_MASK(0), %ecx + /* This assumes we never access addresses above 2^36 in CAR. */ + movl $0x0000000f, %edx + movl $_car_mtrr_mask, %eax + orl $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + /* + * Enable write base caching so we can do execute in place (XIP) + * on the flash ROM. + */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $_program, %eax + andl $_xip_mtrr_mask, %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + movl $0x0000000f, %edx + movl $_xip_mtrr_mask, %eax + orl $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + /* Set the default memory type and enable variable MTRRs. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + xorl %edx, %edx + movl $(MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + movl %eax, %cr0 + + /* Read the range with lodsl. */ + cld + movl $_car_mtrr_start, %esi + movl %esi, %edi + movl $_car_mtrr_size, %ecx + shr $2, %ecx + movl %ecx, %ebx + rep lodsl + + /* Zero out the cache-as-ram area. */ + movl %ebx, %ecx + xorl %eax, %eax + rep stosl + + /* + * The key point of this CAR code is C7 cache does not turn into + * "no fill" mode, which is not compatible with general CAR code. + */ + + /* Setup the stack. */ + mov $_ecar_stack, %esp + + /* Need to align stack to 16 bytes at call instruction. Account for + the pushes below. */ + andl $0xfffffff0, %esp + subl $4, %esp + + /* push TSC and BIST to stack */ + movd %mm0, %eax + pushl %eax /* BIST */ + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ + + /* Copy .data section content to Cache-As-Ram */ +#include <cpu/x86/copy_data_section.inc> + +before_c_entry: call bootblock_c_entry_bist + /* Should never see this postcode */ + post_code(POSTCODE_DEAD_CODE) + .Lhlt: hlt jmp .Lhlt -- To view, visit https://review.coreboot.org/c/coreboot/+/82766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1 Gerrit-Change-Number: 82766 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: via: Start template for VIA C7 w/ CX700 northbridge
by Lean Sheng Tan (Code Review) 11 Nov '24

11 Nov '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82765?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: via: Start template for VIA C7 w/ CX700 northbridge ...................................................................... via: Start template for VIA C7 w/ CX700 northbridge The first steps to bring C7 and CX700 support back mainline. Most is skeleton copied from the `min86' example. The romstage entry is placed in the northbridge code, as that's where we'll perform raminit. Support to read the FSB frequency is added right away, same for a reset function (using CF9 reset), as both are required for a minimal build test. A mainboard VIA EPIA-EX is also introduced for build testing, and in later stages boot testing as well. Links: DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b… PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/… Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/Makefile.mk A src/cpu/via/Kconfig A src/cpu/via/Makefile.mk A src/cpu/via/c7/Kconfig A src/cpu/via/c7/Makefile.mk A src/cpu/via/car/cache_as_ram.S A src/cpu/via/car/exit_car.S A src/mainboard/via/Kconfig A src/mainboard/via/Kconfig.name A src/mainboard/via/epia-ex/Kconfig A src/mainboard/via/epia-ex/Kconfig.name A src/mainboard/via/epia-ex/board_info.txt A src/mainboard/via/epia-ex/devicetree.cb A src/northbridge/via/cx700/Kconfig A src/northbridge/via/cx700/Makefile.mk A src/northbridge/via/cx700/chip.c A src/northbridge/via/cx700/chipset.cb A src/northbridge/via/cx700/clock.c A src/northbridge/via/cx700/reset.c A src/northbridge/via/cx700/romstage.c 20 files changed, 207 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/cpu/Makefile.mk b/src/cpu/Makefile.mk index af24027..0afe454 100644 --- a/src/cpu/Makefile.mk +++ b/src/cpu/Makefile.mk @@ -6,6 +6,7 @@ subdirs-y += amd subdirs-y += armltd subdirs-y += intel +subdirs-y += via subdirs-$(CONFIG_ARCH_X86) += x86 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 subdirs-$(CONFIG_CPU_POWER9) += power9 diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig new file mode 100644 index 0000000..20f7c95 --- /dev/null +++ b/src/cpu/via/Kconfig @@ -0,0 +1 @@ +source "src/cpu/via/*/Kconfig" diff --git a/src/cpu/via/Makefile.mk b/src/cpu/via/Makefile.mk new file mode 100644 index 0000000..e8b7820 --- /dev/null +++ b/src/cpu/via/Makefile.mk @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +subdirs-$(CONFIG_CPU_VIA_C7) += c7 diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig new file mode 100644 index 0000000..df81b3f --- /dev/null +++ b/src/cpu/via/c7/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config CPU_VIA_C7 + bool + select ARCH_X86 + select NO_SMM + select SSE2 + select UNKNOWN_TSC_RATE + select UDELAY_LAPIC + select LAPIC_MONOTONIC_TIMER + +if CPU_VIA_C7 + +config DCACHE_BSP_STACK_SIZE + default 0x1000 + +endif diff --git a/src/cpu/via/c7/Makefile.mk b/src/cpu/via/c7/Makefile.mk new file mode 100644 index 0000000..0890cee --- /dev/null +++ b/src/cpu/via/c7/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += ../car/cache_as_ram.S +bootblock-y += ../../intel/car/bootblock.c + +postcar-y += ../car/exit_car.S diff --git a/src/cpu/via/car/cache_as_ram.S b/src/cpu/via/car/cache_as_ram.S new file mode 100644 index 0000000..5c5066d --- /dev/null +++ b/src/cpu/via/car/cache_as_ram.S @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.section .init, "ax", @progbits + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/cpu/via/car/exit_car.S b/src/cpu/via/car/exit_car.S new file mode 100644 index 0000000..0f1b227 --- /dev/null +++ b/src/cpu/via/car/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig new file mode 100644 index 0000000..8fff542 --- /dev/null +++ b/src/mainboard/via/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_VIA + +choice + prompt "Mainboard model" + +source "src/mainboard/via/*/Kconfig.name" + +endchoice + +source "src/mainboard/via/*/Kconfig" + +config MAINBOARD_VENDOR + default "VIA" + +endif # VENDOR_VIA diff --git a/src/mainboard/via/Kconfig.name b/src/mainboard/via/Kconfig.name new file mode 100644 index 0000000..c3d6cfd --- /dev/null +++ b/src/mainboard/via/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_VIA + bool "VIA" diff --git a/src/mainboard/via/epia-ex/Kconfig b/src/mainboard/via/epia-ex/Kconfig new file mode 100644 index 0000000..76347f2 --- /dev/null +++ b/src/mainboard/via/epia-ex/Kconfig @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_VIA_EPIA_EX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CX700 + select BOARD_ROMSIZE_KB_512 + select NO_UART_ON_SUPERIO + +config MAINBOARD_DIR + default "via/epia-ex" + +config MAINBOARD_PART_NUMBER + default "EPIA-EX" + +endif diff --git a/src/mainboard/via/epia-ex/Kconfig.name b/src/mainboard/via/epia-ex/Kconfig.name new file mode 100644 index 0000000..067e6b4 --- /dev/null +++ b/src/mainboard/via/epia-ex/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_VIA_EPIA_EX + bool "EPIA-EX (work in progress)" diff --git a/src/mainboard/via/epia-ex/board_info.txt b/src/mainboard/via/epia-ex/board_info.txt new file mode 100644 index 0000000..b236799 --- /dev/null +++ b/src/mainboard/via/epia-ex/board_info.txt @@ -0,0 +1,8 @@ +Board name: EPIA-EX +Category: mini +Board URL: https://web.archive.org/web/20211129175218/https://www.viatech.com/en/suppo… +ROM package: PLCC +ROM protocol: LPC +ROM socketed: y +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/via/epia-ex/devicetree.cb b/src/mainboard/via/epia-ex/devicetree.cb new file mode 100644 index 0000000..3f76279 --- /dev/null +++ b/src/mainboard/via/epia-ex/devicetree.cb @@ -0,0 +1,6 @@ +chip northbridge/via/cx700 + + device domain 0 on + end + +end diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig new file mode 100644 index 0000000..95f289a --- /dev/null +++ b/src/northbridge/via/cx700/Kconfig @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_VIA_CX700 + bool + select PCI + select NO_ECAM_MMCONF_SUPPORT + select HAVE_CF9_RESET + +if NORTHBRIDGE_VIA_CX700 + +config CHIPSET_DEVICETREE + default "northbridge/via/cx700/chipset.cb" + +endif diff --git a/src/northbridge/via/cx700/Makefile.mk b/src/northbridge/via/cx700/Makefile.mk new file mode 100644 index 0000000..550ee2d --- /dev/null +++ b/src/northbridge/via/cx700/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_NORTHBRIDGE_VIA_CX700),y) + +romstage-y += romstage.c +ramstage-y += chip.c +all-y += clock.c reset.c + +endif diff --git a/src/northbridge/via/cx700/chip.c b/src/northbridge/via/cx700/chip.c new file mode 100644 index 0000000..57583b8 --- /dev/null +++ b/src/northbridge/via/cx700/chip.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations northbridge_via_cx700_ops = { NULL }; diff --git a/src/northbridge/via/cx700/chipset.cb b/src/northbridge/via/cx700/chipset.cb new file mode 100644 index 0000000..4dd11f3 --- /dev/null +++ b/src/northbridge/via/cx700/chipset.cb @@ -0,0 +1,17 @@ +chip northbridge/via/cx700 + + device domain 0 on + + device pci 00.0 alias host_ctrl on end + device pci 00.1 alias host_err on end + device pci 00.2 alias host_if on end + device pci 00.3 alias dram_ctrl on end + device pci 00.4 alias pm_ctrl on end + device pci 00.7 alias north_end on end + device pci 01.0 alias north_pci off + device pci 00.0 alias vga off end + end + + end + +end diff --git a/src/northbridge/via/cx700/clock.c b/src/northbridge/via/cx700/clock.c new file mode 100644 index 0000000..6bd5942 --- /dev/null +++ b/src/northbridge/via/cx700/clock.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ +#include <console/console.h> +#include <device/pci_ops.h> +#include <static_devices.h> +#include <delay.h> + +static unsigned int read_timer_fsb(void) +{ + /* Allows access to all northbridge PCI devfn's */ + pci_write_config8(_sdev_host_ctrl, 0x4f, 0x01); + + const u8 misc_1 = pci_read_config8(_sdev_host_if, 0x54); + switch (misc_1 >> 5) { + case 0: + return 100; + case 1: + return 133; + case 2: + return 166; + case 3: + return 200; + default: + printk(BIOS_WARNING, "Unknown FSB frequency encoding: 0x%x\n", misc_1 >> 5); + return 200; + } +} + +u32 get_timer_fsb(void) +{ + static unsigned int fsb_mhz; + + if (!fsb_mhz) + fsb_mhz = read_timer_fsb(); + + return fsb_mhz; +} diff --git a/src/northbridge/via/cx700/reset.c b/src/northbridge/via/cx700/reset.c new file mode 100644 index 0000000..b052f1d --- /dev/null +++ b/src/northbridge/via/cx700/reset.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> +#include <cf9_reset.h> + +void do_board_reset(void) +{ + full_reset(); +} diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c new file mode 100644 index 0000000..f4c5584 --- /dev/null +++ b/src/northbridge/via/cx700/romstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <romstage_common.h> +#include <halt.h> + +void __noreturn romstage_main(void) +{ + /* Needed for __noreturn */ + halt(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574 Gerrit-Change-Number: 82765 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Dtrain Hsu (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Amanda Hwang, Ian Feng, Pranava Y N. Dtrain Hsu has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/85037?usp=email ) Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/fatcat/variants/francka/gpio.c: https://review.coreboot.org/c/coreboot/+/85037/comment/7eaf7547_1778fdd8?us… : PS6, Line 219: used_R Should it delete _R? -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 6 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 09:05:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Dtrain Hsu (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Amanda Hwang, Ian Feng, Pranava Y N. Dtrain Hsu has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/85037?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/fatcat/variants/francka/gpio.c: https://review.coreboot.org/c/coreboot/+/85037/comment/b423c9cf_addee43e?us… : PS6, Line 62: ISH_GP_1_SNSR_HDR Please modify the pin name. https://review.coreboot.org/c/coreboot/+/85037/comment/ebc9c4a3_edf62d51?us… : PS6, Line 390: /* GPP_V13: GPP_V13_CATERR_N */ : PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), : /* GPP_V14: GPP_V14_FORCEPR_N */ : PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), : /* GPP_V15: GPP_V15_THERMTRIP_N */ : PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), Please check settings with EE, I didn't see the settings in the GPIO table. -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 6 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 09:03:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE
by Kapil Porwal (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85025?usp=email ) Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Gerrit-Change-Number: 85025 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 08:58:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85025?usp=email ) Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/85025/comment/1131d85d_040680be?us… : PS2, Line 494: /* Clear pending SLP_TYP */ : pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP)); > @kramasub@google.com and @subratabanik@google.com […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Gerrit-Change-Number: 85025 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 08:57:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Hello Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85025?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE ...................................................................... soc/intel/cmn/pmc: Perform PM register init for CSE Before entering FSP-M, AP firmware must ensure the PM1_CNT register reflects the correct sleep state if a global reset occurred. This is crucial when Intel CSE has reset the system, as indicated by the global reset bit and wake status register. If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP firmware must enforce an S5 exit path before handing control to FSP-M for CSE initialization. This ensures proper system initialization and avoids potential issues caused by an inconsistent sleep state. Additionally, clears the PM1 status register (PM1_STS) after retrieving the power state. This prevents stale status information from persisting across power cycles, which could lead to confusion during subsequent boots. BUG=b:265939425 TEST=Verified that `prev_sleep_state` holds the correct value (5 for S5) after CSE performs a global reset. Fixes: Inconsistent sleep state after CSE reset. Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85025/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Gerrit-Change-Number: 85025 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[L] Change in coreboot[main]: mb/google/rex/var/kanix: Add initial overridetree settings
by Kapil Porwal (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Tarun, Tyler Wang. Kapil Porwal has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85021?usp=email ) Change subject: mb/google/rex/var/kanix: Add initial overridetree settings ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468ca388f495b2e527841145f8162b21074058cc Gerrit-Change-Number: 85021 Gerrit-PatchSet: 10 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 08:56:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/google/rex/var/kanix: Add initial GPIO config
by Kapil Porwal (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Tarun, Tyler Wang. Kapil Porwal has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85042?usp=email ) Change subject: mb/google/rex/var/kanix: Add initial GPIO config ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id23b836b48925a30b212b444c9f51cfd6166b9f8 Gerrit-Change-Number: 85042 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 08:56:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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