coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dram type define to coreboot
by Yidi Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85099?usp=email ) Change subject: soc/mediatek/mt8196: Add dram type define to coreboot ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Gerrit-Change-Number: 85099 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 11:42:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85028?usp=email ) Change subject: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config ...................................................................... soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs (ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type for the RAMTOP range. Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was crucial to ensure data consistency, as WB caches both reads and writes. However, since the RAMTOP range now relies on WC MTRR, the role of CLFLUSH becomes less critical. Removing CLFLUSH in this scenario can improve performance, as it avoids unnecessary cache invalidations. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85028 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/pantherlake/Kconfig 3 files changed, 0 insertions(+), 3 deletions(-) Approvals: V Sowmya: Looks good to me, approved Jayvik Desai: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dddf71f..f6e9182 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -96,7 +96,6 @@ select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N && !SOC_INTEL_RAPTORLAKE select VBOOT_LIB - select X86_CLFLUSH_CAR help Intel Alderlake support. Mainboards should specify the PCH type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 4dc6082..73d68df 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -102,7 +102,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202302_BINDING - select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI select INTEL_KEYLOCKER help diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 76a84cd..96324b7 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -105,7 +105,6 @@ select UDELAY_TSC select UDK_202302_BINDING select USE_X86_64_SUPPORT - select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI help Intel Pantherlake support. Mainboards should specify the SoC -- To view, visit https://review.coreboot.org/c/coreboot/+/85028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Gerrit-Change-Number: 85028 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/common: Apply Intel recommendation for early ramtop caching
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85027?usp=email ) Change subject: soc/intel/common: Apply Intel recommendation for early ramtop caching ...................................................................... soc/intel/common: Apply Intel recommendation for early ramtop caching Configuring the Early Caching Ramtop range as Write-Back (WB) before memory initialization is NOT RECOMMENDED. Speculative execution within this WB range can lead to issues. WB configuration should be applied to this range ONLY AFTER memory initialization is complete. To enable Ramtop caching before memory initialization, use Write-Combining (WC) instead of Write-Back (WB). This change applies the recommendation by always configuring the early ramtop caching range as WC. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85027 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/basecode/ramtop/ramtop.c 1 file changed, 14 insertions(+), 20 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified V Sowmya: Looks good to me, approved diff --git a/src/soc/intel/common/basecode/ramtop/ramtop.c b/src/soc/intel/common/basecode/ramtop/ramtop.c index 0ef531a..203d343 100644 --- a/src/soc/intel/common/basecode/ramtop/ramtop.c +++ b/src/soc/intel/common/basecode/ramtop/ramtop.c @@ -181,25 +181,19 @@ } size_t ramtop_size = get_ramtop_size(); - /* - * Background: Some SoCs have a critical bug inside the NEM logic which is responsible - * for mapping cached memory to physical memory during tear down and - * eventually malfunctions if the number of cache sets is not a power of two. - * This can lead to runtime hangs. - * - * Workaround: To mitigate this issue on affected SoCs, we force the MTRR type to - * WC (Write Combining) unless the cache set count is a power of two. - * This change alters caching behavior but prevents the runtime failures. - */ - unsigned int mtrr_type = MTRR_TYPE_WRCOMB; - /* - * Late romstage (including FSP-M post-memory initialization) needs to be - * executed from cache for performance reasons. This requires caching - * `ramtop_size`, which encompasses both FSP reserved memory and the CBMEM - * range, to guarantee sufficient cache coverage for late romstage. - */ - if (is_cache_sets_power_of_two()) - mtrr_type = MTRR_TYPE_WRBACK; + if (!ramtop_size) + return; - set_var_mtrr(mtrr, ramtop - ramtop_size, ramtop_size, mtrr_type); + /* + * INTEL RECOMMENDATION: Early Ramtop Caching Configuration + * + * Configuring the Early Caching Ramtop range as Write-Back (WB) before + * memory initialization is NOT RECOMMENDED. Speculative execution within + * this WB range can lead to issues. WB configuration should be applied + * to this range ONLY AFTER memory initialization is complete. + * + * To enable Ramtop caching before memory initialization, use Write-Combining + * (WC) instead of Write-Back (WB). + */ + set_var_mtrr(mtrr, ramtop - ramtop_size, ramtop_size, MTRR_TYPE_WRCOMB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071 Gerrit-Change-Number: 85027 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Yidi Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 11:41:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/common: Add RAMTOP size in ramtop_table
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85003?usp=email ) Change subject: soc/intel/common: Add RAMTOP size in ramtop_table ...................................................................... soc/intel/common: Add RAMTOP size in ramtop_table This patch adds a new field, `size`, to the `ramtop_table` structure to store the size of the RAMTOP region. The RAMTOP size is calculated as the difference between the cbmem top and the FSP reserved memory base address, aligned up to the nearest 4MB boundary. This change allows for more accurate tracking of the RAMTOP region and improves compatibility with different memory configurations. Previously, the RAMTOP size was always assumed to be 16MB. This could lead to boot hangs on systems with different memory configurations, where the actual RAMTOP size exceeded 16MB. By dynamically calculating and storing the RAMTOP size, this patch ensures that the correct memory range is used for intermediate caching, preventing boot hangs and improving boot speed. The `update_ramtop()` function is updated to write the calculated RAMTOP size to CMOS along with the RAMTOP address. The `early_ramtop_enable_cache_range()` function is also updated to use the RAMTOP size from CMOS to set the correct MTRR range. BUG=b:373290479 TEST=Built and booted successfully on various platforms. Verified that the RAMTOP size is correctly calculated and stored in CMOS Change-Id: I16d610c5791895b59da57d543c54da6621617912 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85003 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/basecode/ramtop/ramtop.c 1 file changed, 63 insertions(+), 7 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved V Sowmya: Looks good to me, approved diff --git a/src/soc/intel/common/basecode/ramtop/ramtop.c b/src/soc/intel/common/basecode/ramtop/ramtop.c index 9cef9b1..0ef531a 100644 --- a/src/soc/intel/common/basecode/ramtop/ramtop.c +++ b/src/soc/intel/common/basecode/ramtop/ramtop.c @@ -4,13 +4,14 @@ #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> +#include <fsp/util.h> #include <intelbasecode/ramtop.h> #include <pc80/mc146818rtc.h> #include <stdint.h> /* We need a region in CMOS to store the RAMTOP address */ -#define RAMTOP_SIGNATURE 0x52544F50 /* 'RTOP' */ +#define RAMTOP_SIGNATURE 0x504F5452 /* 'RTOP' */ /* * Address of the ramtop byte in CMOS. Should be reserved @@ -39,6 +40,7 @@ struct ramtop_table { uint32_t signature; uint32_t addr; + size_t size; uint16_t checksum; } __packed; @@ -57,6 +59,12 @@ return -1; } + /* Verify RAMTOP size */ + if (ramtop->size == 0) { + printk(BIOS_DEBUG, "ramtop_table holds invalid size\n"); + return -1; + } + /* Verify checksum over signature and counter only */ csum = ipchksum(ramtop, offsetof(struct ramtop_table, checksum)); @@ -80,6 +88,36 @@ cmos_write(*p, (CMOS_VSTART_ramtop / 8) + i); } +/* + * RAMTOP range: + * + * This defines the memory range covered by RAMTOP, which extends from + * cbmem_top down to FSP TOLUM. This range includes essential components: + * + * +---------------------------+ TOLUM / top_of_ram / cbmem_top + * | CBMEM Root | + * +---------------------------+ + * | FSP Reserved Memory | + * +---------------------------+ + * | various CBMEM entries | + * +---------------------------+ top_of_stack (8 byte aligned) + * | stack (CBMEM entry) | + * +---------------------------+ FSP TOLUM + * | | + * +---------------------------+ 0 +*/ +static size_t calculate_ramtop_size(uint32_t addr) +{ + struct range_entry fsp_mem; + uint32_t fsp_reserve_base; + fsp_find_reserved_memory(&fsp_mem); + + fsp_reserve_base = range_entry_base(&fsp_mem); + size_t ramtop_size = ALIGN_UP(addr - fsp_reserve_base, 4 * MiB); + + return ramtop_size; +} + /* Update the RAMTOP if required based on the input top_of_ram address */ void update_ramtop(uint32_t addr) { @@ -90,18 +128,23 @@ /* Structure invalid, re-initialize */ ramtop.signature = RAMTOP_SIGNATURE; ramtop.addr = 0; + ramtop.size = 0; } + size_t size = calculate_ramtop_size(addr); + /* Update ramtop if required */ - if (ramtop.addr == addr) + if ((ramtop.addr == addr) && (ramtop.size == size)) return; ramtop.addr = addr; + ramtop.size = size; /* Write the new top_of_ram address to CMOS */ ramtop_cmos_write(&ramtop); - printk(BIOS_DEBUG, "Updated the RAMTOP address into CMOS 0x%x\n", ramtop.addr); + printk(BIOS_DEBUG, "Updated the RAMTOP address (0x%x) with size (0x%zx) into CMOS\n", + ramtop.addr, ramtop.size); } uint32_t get_ramtop_addr(void) @@ -114,6 +157,16 @@ return ramtop.addr; } +static uint32_t get_ramtop_size(void) +{ + struct ramtop_table ramtop; + + if (ramtop_cmos_read(&ramtop) < 0) + return 0; + + return ramtop.size; +} + /* Early caching of top_of_ram region */ void early_ramtop_enable_cache_range(void) { @@ -127,6 +180,7 @@ return; } + size_t ramtop_size = get_ramtop_size(); /* * Background: Some SoCs have a critical bug inside the NEM logic which is responsible * for mapping cached memory to physical memory during tear down and @@ -139,11 +193,13 @@ */ unsigned int mtrr_type = MTRR_TYPE_WRCOMB; /* - * We need to make sure late romstage (including FSP-M post mem) will be run - * cached. Caching 16MB below ramtop is a safe to cover late romstage. - */ + * Late romstage (including FSP-M post-memory initialization) needs to be + * executed from cache for performance reasons. This requires caching + * `ramtop_size`, which encompasses both FSP reserved memory and the CBMEM + * range, to guarantee sufficient cache coverage for late romstage. + */ if (is_cache_sets_power_of_two()) mtrr_type = MTRR_TYPE_WRBACK; - set_var_mtrr(mtrr, ramtop - 16 * MiB, 16 * MiB, mtrr_type); + set_var_mtrr(mtrr, ramtop - ramtop_size, ramtop_size, mtrr_type); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16d610c5791895b59da57d543c54da6621617912 Gerrit-Change-Number: 85003 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add dram calibration support
by Yidi Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85098?usp=email ) Change subject: soc/mediatek/mt8196: Add dram calibration support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b Gerrit-Change-Number: 85098 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 11:41:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR
by Lean Sheng Tan (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email ) Change subject: soc/intel/xeon_sp: Reserve PRMRR ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/84314/comment/4688efbf_c7631d2c?us… : PS4, Line 169: printk(BIOS_ERR, "%s(): PRMRR is not supported.\n", __func__); > It is for some engineering samples not fully get the feature turned on. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Gerrit-Change-Number: 84314 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 11:36:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config
by Jayvik Desai (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Nick Vaccaro, Pranava Y N, Subrata Banik, Tarun. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85028?usp=email ) Change subject: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Gerrit-Change-Number: 85028 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 11:33:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dram type define to coreboot
by Jarried Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Crystal Guo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85099?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Add dram type define to coreboot ...................................................................... soc/mediatek/mt8196: Add dram type define to coreboot Implement map_to_lpddr_dram_type to convert MT8196 specific DRAM_DRAM_TYPE_T values to mem_chip_type. BUG=b:357743097 TEST=Firmware shows the following log: LPDDR5 chan0(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan0(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank1: density 12288mbits x16, MF 06 rev 0800 Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/dramc_soc.h A src/soc/mediatek/mt8196/memory.c 3 files changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85099/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 2493464..3d04a5d 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -23,7 +23,7 @@ romstage-y += ../common/emi.c romstage-y += irq2axi.c romstage-y += l2c_ops.c -romstage-y += ../common/memory.c +romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h index dde00c2..c01daf5 100644 --- a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h +++ b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h @@ -43,6 +43,23 @@ IMP_DRV_MAX, } DRAM_IMP_DRV_T; +typedef enum { + TYPE_DDR1 = 1, + TYPE_DDR2, + TYPE_DDR3, + TYPE_DDR4, + TYPE_DDR5, + TYPE_LPDDR2, + TYPE_LPDDR3, + TYPE_PCDDR3, + TYPE_LPDDR4, + TYPE_LPDDR4X, + TYPE_LPDDR4P, + TYPE_LPDDR5, + TYPE_LPDDR5X, + TYPE_MAX, +} DRAM_DRAM_TYPE_T; + #define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX #define DQS_NUMBER_LP5 2 #define DQ_DATA_WIDTH_LP5 16 diff --git a/src/soc/mediatek/mt8196/memory.c b/src/soc/mediatek/mt8196/memory.c new file mode 100644 index 0000000..2689e5a --- /dev/null +++ b/src/soc/mediatek/mt8196/memory.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <commonlib/bsd/mem_chip_info.h> +#include <soc/emi.h> + +enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type) +{ + switch (lpddr_type) { + case TYPE_LPDDR4X: + return MEM_CHIP_LPDDR4X; + case TYPE_LPDDR5: + return MEM_CHIP_LPDDR5; + case TYPE_LPDDR5X: + return MEM_CHIP_LPDDR5X; + default: + return MEM_CHIP_UNDEFINED; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Gerrit-Change-Number: 85099 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Jarried Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Crystal Guo, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85034?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... mem_chip_info: Add LPDDR5 enums to mem_chip_type Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. BUG=b:357743097 TEST=build pass Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85034/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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