coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2521 discussions

[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR
by Angel Pons (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email ) Change subject: soc/intel/xeon_sp: Reserve PRMRR ...................................................................... Patch Set 6: (1 comment) File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/84314/comment/dc209531_efda229e?us… : PS6, Line 171: /* : * fls64: find least significant bit set in a 64-bit word : * As samples, fls64(0x0) = 64; fls64(0x4400) = 10; : * fls64(0x40400000000) = 34. : */ : static uint32_t fls64(uint64_t x) : { : uint32_t lo = (uint32_t)x; : if (lo) : return fls(lo); : uint32_t hi = x >> 32; : return fls(hi) + 32; : } https://github.com/coreboot/coreboot/blob/2dd8f2e13b9e8bf10cd98e707534975f9… I know there's https://github.com/coreboot/coreboot/blob/2dd8f2e13b9e8bf10cd98e707534975f9… but I think it makes more sense to use what's in `lib.h` Though I would prefer to replace `fls` and `fms` in a separate commit. Would like to know others' thoughts. -- To view, visit https://review.coreboot.org/c/coreboot/+/84314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Gerrit-Change-Number: 84314 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 14:19:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dram type define to coreboot
by Yu-Ping Wu (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85099?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Add dram type define to coreboot ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85099/comment/15903bb6_f22b4faf?us… : PS2, Line 7: Add dram type define to coreboot Map LPDDR type to mem_chip_type -- To view, visit https://review.coreboot.org/c/coreboot/+/85099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Gerrit-Change-Number: 85099 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 13:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Amanda Hwang, Pranava Y N. Subrata Banik has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/85095?usp=email ) Change subject: mb/google/fatcat: Limit memory speed for MT62F2G32D4DS-020 WT:F ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > let me come back with something that is more meaningful here can you please check https://review.coreboot.org/c/coreboot/+/85101/1 and https://review.coreboot.org/c/coreboot/+/85102/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45227cda12009b1cd1294a275393faa48b3e76a7 Gerrit-Change-Number: 85095 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 13:11:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Override DRAM Freq
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85102?usp=email ) Change subject: mb/google/fatcat/var/francka: Override DRAM Freq ...................................................................... mb/google/fatcat/var/francka: Override DRAM Freq Due to the hardware limitation on francka, reduce the memory speed to 7467 MT/s. BUG=b:373394046 TEST=emerge-fatcat coreboot Change-Id: I9c45c90952e20fc96943df03f591075338624e88 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/francka/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/85102/1 diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index bfd637a..e38b186 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -1,5 +1,7 @@ chip soc/intel/pantherlake + register "max_dram_speed_mts" = "7467" + device domain 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c45c90952e20fc96943df03f591075338624e88 Gerrit-Change-Number: 85102 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add config option to limit DRAM frequency
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85101?usp=email ) Change subject: soc/intel/pantherlake: Add config option to limit DRAM frequency ...................................................................... soc/intel/pantherlake: Add config option to limit DRAM frequency This patch adds a new config option to limit the maximum DRAM frequency for Pantherlake platforms. The mainboard code should try to set `max_dram_speed_mts` from override device tree if required. BUG=b:373394046 TEST=Able to build and boot google/fatcat. Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/85101/1 diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index b59ce5e..5846037 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -512,6 +512,8 @@ */ uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + uint16_t max_dram_speed_mts; + }; typedef struct soc_intel_pantherlake_config config_t; diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index b105d3d..e6ed19ec 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -74,6 +74,9 @@ m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; } + if (config->max_dram_speed_mts) + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + m_cfg->RMT = config->rmt; m_cfg->MrcFastBoot = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65 Gerrit-Change-Number: 85101 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Subrata Banik (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Anil Kumar K, Naveen M, Pranava Y N, Varun Upadhyay. Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/23a297fc_65f1a095?us… : PS2, Line 8: AUDIO_ALC721_SNDW > jfyi, at kernel, we add driver data & match table for codec at sndw3.. > https://lore.kernel.org/all/20241007075955.12575-4-yung-chuan.liao@linux.in… > > This hardware connection data needs to be exposed by Coreboot configuration. so this is like static hardware configuration that you wish to keep in sync between kernel driver and coreboot, while cros config via config.star is the way to pass the information ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 12:45:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Naveen M <naveen.m(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
by Yu-Ping Wu (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85094?usp=email ) Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Gerrit-Change-Number: 85094 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 12:38:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Yu-Ping Wu (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Crystal Guo, Jarried Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 12:35:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Naveen M (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N, Subrata Banik, Varun Upadhyay. Naveen M has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/934bbde1_b1cc1a47?us… : PS2, Line 8: AUDIO_ALC721_SNDW > Hello Subrata, […] jfyi, at kernel, we add driver data & match table for codec at sndw3.. https://lore.kernel.org/all/20241007075955.12575-4-yung-chuan.liao@linux.in… This hardware connection data needs to be exposed by Coreboot configuration. -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 12:32:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Naveen M <naveen.m(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
by Jarried Lin (Code Review) 11 Nov '24

11 Nov '24

Attention is currently required from: Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85094?usp=email ) Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85094/comment/12dd8b50_f7829ed1?us… : PS1, Line 9: The DRAMC Parameters size is larger than before, therefore the size of : CBFS_MCACHE needs to be increased to avoid mcache overflow. > Rauru has MT8196 SoC. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Gerrit-Change-Number: 85094 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 11 Nov 2024 12:13:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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coreboot-gerrit November 2024