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Change subject: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
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Change subject: soc/intel/jasperlake: add support for RP LTR mechanism
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Patch Set 3:
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https://review.coreboot.org/c/coreboot/+/84866/comment/f516a348_f6ba310a?us… :
PS3, Line 13: Tested on Awasuki with RTL8852BE
> How to check this exactly? coreboot logs or `lspci`?
You can check root port configuration space dump, LTR Mechanism Enable bit is offset 68h[10].
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Change subject: soc/mediatek/mt8196: Disable irq2axi feature
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(1 comment)
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https://review.coreboot.org/c/coreboot/+/84896/comment/5f32eb4b_59362752?us… :
PS5, Line 12: If the interrupt is not handled, it will cause the system fail to boot.
Either move this to the previous line, or add a blank line above to start a new paragraph.
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Change subject: mb/google/rauru: Pass reset gpio parameter to BL31
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Change subject: mb/google/rauru: Configure TPM
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Change subject: mb/google/rauru: Enable ChromeOS EC
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Change subject: soc/mediatek/mt8196: Add SPI driver support
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Patch Set 3:
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File src/soc/mediatek/mt8196/include/soc/spi.h:
https://review.coreboot.org/c/coreboot/+/84930/comment/77378dd5_457530c4?us… :
PS3, Line 8: #ifndef __SOC_MEDIATEK_MT8196_SPI_H__
Why change it? The code in mediatek/ is already inconsistent.
https://review.coreboot.org/c/coreboot/+/84930/comment/3db69873_0868ec4e?us… :
PS3, Line 15: x
`(x)`
File src/soc/mediatek/mt8196/spi.c:
https://review.coreboot.org/c/coreboot/+/84930/comment/9cf45a66_cf894d7f?us… :
PS3, Line 123: SPI_BUS_NUMBER
`ARRAY_SIZE(pad_funcs[0])`
I fixed mt8188 in CB:84950.
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Change subject: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
......................................................................
soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
The size of the inner array of the 2-dimensional array pad_funcs should
be 4 instead of SPI_BUS_NUMBER (6). This bug leads to two extra
gpio_set_mode() calls with unexpected GPIOs.
Inspecting spi.o, the data immediately after the .rodata.pad_funcs
section is .rodata.spi_ctrlr_bus_map, with the following data:
00000428 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00
00000438 00 00 00 00 00 00 00 00 ...
This is equivalent to the following calls:
gpio_set_mode(GPIO(GPIO05), 0);
gpio_set_mode(GPIO(GPIO00), 0);
The second call is already included in the pad_funcs array, so the first
call is the only practical impact of this bug.
Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8188/spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/84950/1
diff --git a/src/soc/mediatek/mt8188/spi.c b/src/soc/mediatek/mt8188/spi.c
index 994663d..66fbf0f 100644
--- a/src/soc/mediatek/mt8188/spi.c
+++ b/src/soc/mediatek/mt8188/spi.c
@@ -114,7 +114,7 @@
ptr = pad_funcs[bus];
- for (unsigned int i = 0; i < SPI_BUS_NUMBER; i++)
+ for (unsigned int i = 0; i < ARRAY_SIZE(pad_funcs[0]); i++)
gpio_set_mode(ptr[i].gpio, ptr[i].func);
}
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