coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/fatcat: Move CSE sync at payload
by Kapil Porwal (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Paul Menzel, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85233?usp=email ) Change subject: mb/google/fatcat: Move CSE sync at payload ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f1dd2e153ed0f1e671699002cf34a58d758ce2f Gerrit-Change-Number: 85233 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 04:16:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Held, Felix Singer, Frans Hendriks, Jérémy Compostella, Patrick Rudolph, Paul Menzel, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 60: Code-Review+1 (6 comments) File src/soc/intel/snowridge/acpi.c: https://review.coreboot.org/c/coreboot/+/83321/comment/4eaf1bae_bca5460e?us… : PS60, Line 94: /* PCH PCIe root port needs further swizzle. */ Not sure the root port itself needs such pin swizzle or not (though I agree its child device's intx message needs such transformation). https://review.coreboot.org/c/coreboot/+/83321/comment/dbe62fd7_31918f30?us… : PS60, Line 115: intel_write_pci_PRT(scope, pin_irq_map, map_count, &pirq_map); The scope could be obtained from domain's device path, e.g. acpi_device_acope() https://review.coreboot.org/c/coreboot/+/83321/comment/e1b2d794_30eba74d?us… : PS60, Line 127: /* Generating accelerator domains dynamically since they are SKU-dependent. */ Maybe add a comment that pch domain (domain0) is in dsdt https://review.coreboot.org/c/coreboot/+/83321/comment/dd299d59_3d3ded73?us… : PS60, Line 280: if (dev == DEV_PTR(dlb_sa)) { If using devicetree ptr in soc codes, there should be a soc layer devicetree.cb to be consistent. https://review.coreboot.org/c/coreboot/+/83321/comment/7a6e963b_52aad638?us… : PS60, Line 333: struct device *dev = PCH_DEV_XHCI; Not sure if this could be represented as a devicetree ptr, thus to reduce the types of dev reference overall. File src/soc/intel/snowridge/lpc.c: https://review.coreboot.org/c/coreboot/+/83321/comment/c75c76a3_23349e8b?us… : PS60, Line 47: swizzle_pin = get_pci_irq_pins(dev, &bridge); Can this code working with multiple pcie bridge layers? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 60 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 22 Nov 2024 04:13:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brya/var/redrix: Add ACPI fan definitions
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85175?usp=email ) Change subject: mb/google/brya/var/redrix: Add ACPI fan definitions ...................................................................... mb/google/brya/var/redrix: Add ACPI fan definitions Add entries in overridetree.cb required for exposing fan control via ACPI, which is used then by acpi-fan driver in Linux kernel. This includes: 1. Fan duty-cycle/rpm table. The RPM numbers were adjusted to the values reported by ACPI on different duty cycle levels. 2. Dummy Active DPTF policy. This is required to mark the TFNx devices as active and therefore let the acpi-fan driver probe. BUG=b:358089775 TEST=Build and flash on redrix and check /sys/class/thermal for TFN1 Change-Id: Iaeffe8bc48cd8cd800efa7be29ec81447ecf2935 Signed-off-by: Stanislaw Kardach <skardach(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85175 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 56 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 1843670..7acb3ff 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -162,6 +162,41 @@ register "options.tsr[2].desc" = ""Charger"" register "options.tsr[3].desc" = ""5V regulator"" + ## Active Policy + # NOTE: Copy from EC. Only to enable acpi-fan. + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(100, 85), + TEMP_PCT( 58, 78), + TEMP_PCT( 57, 71), + TEMP_PCT( 56, 68), + TEMP_PCT( 55, 66), + TEMP_PCT( 54, 53), + } + }, + [1] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(100, 85), + TEMP_PCT( 58, 78), + TEMP_PCT( 57, 71), + TEMP_PCT( 56, 68), + TEMP_PCT( 55, 66), + TEMP_PCT( 54, 53), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(100, 100), + TEMP_PCT( 58, 63), + TEMP_PCT( 57, 61), + } + } + }" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ @@ -194,6 +229,27 @@ [2] = { 16, 1000 }, [3] = { 8, 500 } }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + # NOTE: Noise and Power numbers are placeholders. + register "controls.fan_perf" = "{ + [ 0] = { 100, 9500, 200, 2000, }, + [ 1] = { 90, 8700, 180, 1800, }, + [ 2] = { 80, 8000, 160, 1600, }, + [ 3] = { 70, 7200, 140, 1400, }, + [ 4] = { 60, 6300, 120, 1200, }, + [ 5] = { 50, 5400, 100, 1000, }, + [ 6] = { 40, 4400, 80, 800, }, + [ 7] = { 30, 3300, 60, 600, }, + [ 8] = { 20, 2100, 40, 400, }, + [ 9] = { 10, 800, 20, 200, }, + [10] = { 0, 0, 0, 0, }, + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + device generic 0 alias dptf_policy on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaeffe8bc48cd8cd800efa7be29ec81447ecf2935 Gerrit-Change-Number: 85175 Gerrit-PatchSet: 3 Gerrit-Owner: Stanisław Kardach <skardach(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Turn off camera during S0ix
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85133?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/pujjoga: Turn off camera during S0ix ...................................................................... mb/google/nissa/var/pujjoga: Turn off camera during S0ix Add a variant specific S0ix hook to fill the SSDT table to disable and enable camera during suspend and resume respectively. For safety concern, our client LENOVO want us to follow the Boten project to create the function. BUG=b:378525209 TEST=Build Pujjoga BIOS image. Ensure that camera is disabled during suspend and enabled during resume. Do the powerd_dbus_suspend and measure the camera power 3.3V which is disable. And resume will recover. Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993 Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85133 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjoga/variant.c 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjoga/variant.c b/src/mainboard/google/brya/variants/pujjoga/variant.c index c4a6fac..2264264c 100644 --- a/src/mainboard/google/brya/variants/pujjoga/variant.c +++ b/src/mainboard/google/brya/variants/pujjoga/variant.c @@ -2,8 +2,23 @@ #include <fw_config.h> #include <sar.h> +#include <acpi/acpigen.h> +#include <gpio.h> +#include <acpi/acpi.h> +#include <baseboard/variants.h> + const char *get_wifi_sar_cbfs_filename(void) { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); } + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + /* GPP_C3 control the 3.3V of user facing camera, + pull down when do suspend and pull high when resume. */ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(GPP_C3); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(GPP_C3); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993 Gerrit-Change-Number: 85133 Gerrit-PatchSet: 12 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nikki Huang <nikki.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/fatcat/var/francka: Add memory DQ map
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85205?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat/var/francka: Add memory DQ map ...................................................................... mb/google/fatcat/var/francka: Add memory DQ map Follow latest schematics MB_SCH_1102A to add the DQ map. BUG=b:372395010 TEST=emerge-fatcat coreboot Change-Id: I2ea0c5a07d83df108e41fc838e702b793c878096 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85205 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/memory.c 2 files changed, 94 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/Makefile.mk index bb28536..f4b5d45 100644 --- a/src/mainboard/google/fatcat/variants/francka/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/francka/Makefile.mk @@ -3,6 +3,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c diff --git a/src/mainboard/google/fatcat/variants/francka/memory.c b/src/mainboard/google/fatcat/variants/francka/memory.c new file mode 100644 index 0000000..74d74cd --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/memory.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 14, 12, 15, 11, 10, 8, 9 }, + .dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 }, + }, + .ddr1 = { + .dq0 = { 1, 3, 0, 2, 7, 4, 6, 5 }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, + }, + .ddr2 = { + .dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 14, 13, 15, 12, 8, 11, 10, 9 }, + }, + .ddr3 = { + .dq0 = { 6, 5, 7, 4, 2, 3, 1, 0 }, + .dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 }, + }, + .ddr4 = { + .dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 }, + .dq1 = { 15, 14, 12, 13, 9, 11, 10, 8 }, + }, + .ddr5 = { + .dq0 = { 6, 5, 7, 4, 3, 1, 0, 2 }, + .dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 }, + }, + .ddr6 = { + .dq0 = { 9, 10, 11, 8, 14, 12, 13, 15 }, + .dq1 = { 0, 1, 2, 3, 5, 7, 4, 6 }, + }, + .ddr7 = { + .dq0 = { 0, 1, 2, 3, 7, 5, 6, 4 }, + .dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .lp_ddr_dq_dqs_re_training = 1, + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_D08 + * GPIO_MEM_CONFIG_1 GPP_D07 + * GPIO_MEM_CONFIG_2 NC + * GPIO_MEM_CONFIG_3 NC + */ + gpio_t spd_gpios[] = { + GPP_D08, + GPP_D07, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ea0c5a07d83df108e41fc838e702b793c878096 Gerrit-Change-Number: 85205 Gerrit-PatchSet: 6 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85206?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F ...................................................................... mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F Change the ram_id to 1 for MT62F2G32D4DS-020 WT:F based on the hardware schematic MB_SCH_1102A. BUG=b:372395010 TEST=Run part_id_gen tool and check the generated files. Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85206 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk M src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt M src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 5 deletions(-) Approvals: Dtrain Hsu: Looks good to me, approved build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk index 62c45356..310ef55 100644 --- a/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ptl lp5 src/mainboard/google/fatcat/variants/francka/memory/ src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/francka/memory src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 0(0b0000) Parts = MT62F2G32D4DS-020 WT:F +SPD_SOURCES += spd/lp5/set-0/spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 1(0b0001) Parts = MT62F2G32D4DS-020 WT:F diff --git a/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt index 31165c4..dcb790a 100644 --- a/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt +++ b/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ptl lp5 src/mainboard/google/fatcat/variants/francka/memory/ src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/francka/memory src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt DRAM Part Name ID to assign -MT62F2G32D4DS-020 WT:F 0 (0000) +MT62F2G32D4DS-020 WT:F 1 (0001) diff --git a/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt index e6822f6..9b80035 100644 --- a/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt +++ b/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt @@ -9,4 +9,4 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name -MT62F2G32D4DS-020 WT:F +MT62F2G32D4DS-020 WT:F,1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3 Gerrit-Change-Number: 85206 Gerrit-PatchSet: 3 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Enable UFS controller
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85192?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat/var/fatcat: Enable UFS controller ...................................................................... mb/google/fatcat/var/fatcat: Enable UFS controller This commit enables the UFS controller on the Google Fatcat mainboard based on FW_CONFIG. This change allows the system to utilize the UFS storage device. TEST=Built google/fatcat with UFS enabled. Change-Id: Ib32523e7865b2ea23d990b2cf9b7406a4d6ecde3 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85192 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 0fd79d0..586cf4f 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -307,6 +307,11 @@ end end + device ref ufs on + probe STORAGE STORAGE_UFS + probe STORAGE STORAGE_UNKNOWN + end + device ref pcie_rp2 on probe CELLULAR CELLULAR_PCIE register "pcie_rp[PCIE_RP(2)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/85192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib32523e7865b2ea23d990b2cf9b7406a4d6ecde3 Gerrit-Change-Number: 85192 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add option to enable UFS controller
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85191?usp=email ) Change subject: soc/intel/pantherlake: Add option to enable UFS controller ...................................................................... soc/intel/pantherlake: Add option to enable UFS controller This patch adds a Kconfig option to enable the UFS controller for mainboards using the Intel Panther Lake-UH SoC. By default, the UFS controller is disabled as it is not supported by other SoC configurations. This prevents accidental enabling of the UFS controller on unsupported platforms. BUG=b:379828045 TEST=Built google/fatcat with and without UFS enabled. Change-Id: Ica89ae85582367809128fc6cf0cd5fe5d40a2235 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85191 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/acpi/southbridge.asl M src/soc/intel/pantherlake/chipset.cb M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/include/soc/pci_devs.h A src/soc/intel/pantherlake/include/soc/ufs.h 6 files changed, 48 insertions(+), 1 deletion(-) Approvals: Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 96c09b8..26a4987 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -421,4 +421,8 @@ int default 42 +config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 38400000 + endif diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl index 219a971..c047a71 100644 --- a/src/soc/intel/pantherlake/acpi/southbridge.asl +++ b/src/soc/intel/pantherlake/acpi/southbridge.asl @@ -49,6 +49,8 @@ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> /* UFS 0:17:0 */ -/* TODO: Add ufs.asl entry for PTL-U SKU */ +#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) +#include <soc/intel/common/block/acpi/acpi/ufs.asl> +#endif #endif diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb index 2f6bf02..67e0785 100644 --- a/src/soc/intel/pantherlake/chipset.cb +++ b/src/soc/intel/pantherlake/chipset.cb @@ -143,6 +143,7 @@ device pci 16.1 alias heci2 off end device pci 16.4 alias heci3 off end device pci 16.5 alias heci4 off end + device pci 17.0 alias ufs off end device pci 18.0 alias eheci1 off end device pci 18.1 alias eheci2 off end device pci 18.2 alias eheci3 off end diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index eaef582..e0b0adf 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -658,6 +658,20 @@ s_cfg->IaxEnable = is_devfn_enabled(PCI_DEVFN_IAA); } +static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_pantherlake_config *config) +{ +#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) + /* Setting FSP UPD (1,0) to enable controller 0 */ + s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS); + s_cfg->UfsEnable[1] = 0; +#else + /* Setting FSP UPD (0,0) to keep both controllers disabled */ + s_cfg->UfsEnable[0] = 0; + s_cfg->UfsEnable[1] = 0; +#endif +} + static void arch_silicon_init_params(FSPS_ARCH2_UPD *s_arch_cfg) { /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ @@ -696,6 +710,7 @@ fill_fsps_npu_params, fill_fsps_audio_params, fill_fsps_iax_params, + fill_fsps_ufs_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h index dc419d0..bff5bd3 100644 --- a/src/soc/intel/pantherlake/include/soc/pci_devs.h +++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h @@ -139,6 +139,12 @@ #define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) #define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) +#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) +#define PCI_DEV_SLOT_UFS 0x17 +#define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0) +#define PCI_DEV_UFS _PCI_DEV(UFS, 0) +#endif + #define PCI_DEV_SLOT_ESE 0x18 #define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) #define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) diff --git a/src/soc/intel/pantherlake/include/soc/ufs.h b/src/soc/intel/pantherlake/include/soc/ufs.h new file mode 100644 index 0000000..ffd9b1f --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/ufs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Panther Lake Processor PCH Datasheet + * Document number: TBD + */ + +#ifndef _SOC_PANTHERLAKE_UFS_H_ +#define _SOC_PANTHERLAKE_UFS_H_ + +#include <soc/pci_devs.h> + +/* Calculate _ADR for Intel UFS Controller */ +#define UFS_ACPI_DEVICE (PCI_DEV_SLOT_UFS << 16 | 0x0007) + +#define R_SCS_CFG_PCS 0x84 +#define R_SCS_CFG_PG_CONFIG 0xA2 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica89ae85582367809128fc6cf0cd5fe5d40a2235 Gerrit-Change-Number: 85191 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/cmn/acpi: Use Kconfig guards for UFS workarounds
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85208?usp=email ) Change subject: soc/intel/cmn/acpi: Use Kconfig guards for UFS workarounds ...................................................................... soc/intel/cmn/acpi: Use Kconfig guards for UFS workarounds This change introduces Kconfig guards around the UFS workaround code in the common ACPI ASL file. This ensures that these workarounds are only applied when necessary, allowing future SoCs with UFS controllers to reuse the common ASL file without modification. By using Kconfig, we can enable or disable the workarounds based on the specific SoC configuration, providing greater flexibility and maintainability. BUG=b:379828045 TEST=Able to compile google/fatcat. Change-Id: I968b8811e508378a36648bd8234ff0fd7237b00d Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85208 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi/ufs.asl 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl index fcfe9bd..7d8d25d 100644 --- a/src/soc/intel/common/block/acpi/acpi/ufs.asl +++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl @@ -28,6 +28,7 @@ } }) +#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) /* * OCP Timer need to be disabled in SCS UFS IOSF Bridge to work around * the Silicon Issue due to which LTR mechanism doesn't work. @@ -47,6 +48,7 @@ PCRA (PID_UFSX2, R_SCS_PCR_5820, 0x0) PCRA (PID_UFSX2, R_SCS_PCR_1078, 0x0) } +#endif /* Memory Region to access to the UFS PCI Configuration Space */ OperationRegion(SCSR, PCI_Config, 0x00, 0x100) @@ -62,6 +64,7 @@ PGEN, 1 } +#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY) OperationRegion(PWMR, SystemMemory, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE) Field(PWMR, DWordAcc, NoLock, Preserve) { @@ -73,6 +76,7 @@ Method (ULTR, 1, Serialized) { LTRU = Arg0 } +#endif Method (_PS0, 0, Serialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/85208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I968b8811e508378a36648bd8234ff0fd7237b00d Gerrit-Change-Number: 85208 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update Touch Controller UPD params
by Subrata Banik (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85199?usp=email ) Change subject: soc/intel/pantherlake: Update Touch Controller UPD params ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85199/comment/8ed02cde_35a2a7d1?us… : PS3, Line 563: if (is_devfn_enabled(PCI_DEVFN_THC0)) { : s_cfg->ThcAssignment[0] = THC_0; : s_cfg->ThcMode[0] = config->thc_mode[0]; : s_cfg->ThcWakeOnTouch[0] = config->thc_wake_on_touch[0]; : } else { : s_cfg->ThcAssignment[0] = THC_NONE; : } : if (is_devfn_enabled(PCI_DEVFN_THC1)) { : s_cfg->ThcAssignment[1] = THC_1; : s_cfg->ThcMode[1] = config->thc_mode[1]; : s_cfg->ThcWakeOnTouch[1] = config->thc_wake_on_touch[1]; : } else { : s_cfg->ThcAssignment[1] = THC_NONE; : } : } ``` if (is_devfn_enabled(PCI_DEVFN_THC0)) { s_cfg->ThcAssignment[0] = THC_0; s_cfg->ThcAssignment[1] = THC_NONE; s_cfg->ThcMode[0] = config->thc_mode[0]; s_cfg->ThcWakeOnTouch[0] = config->thc_wake_on_touch[0]; } else if (is_devfn_enabled(PCI_DEVFN_THC1)) { s_cfg->ThcAssignment[0] = THC_NONE; s_cfg->ThcAssignment[1] = THC_1; s_cfg->ThcMode[1] = config->thc_mode[1]; s_cfg->ThcWakeOnTouch[1] = config->thc_wake_on_touch[1]; } else { s_cfg->ThcAssignment[0] = THC_NONE; s_cfg->ThcAssignment[1] = THC_NONE; } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Gerrit-Change-Number: 85199 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 02:48:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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