coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
1925 discussions

[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F
by Amanda Hwang (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Paul Menzel. Amanda Hwang has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/85206?usp=email ) Change subject: mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85206/comment/af696220_43918e1f?us… : PS1, Line 7: Change RAM_ID to 1 > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/85206/comment/966394ef_5a567103?us… : PS1, Line 11: > Out of curiosity: What is the actual problem? Is 0 reserved for the empty SPD? just follow HW schematic and use Google part_id_gen tool to regenerate the RAM_ID mapping. -- To view, visit https://review.coreboot.org/c/coreboot/+/85206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3 Gerrit-Change-Number: 85206 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 22 Nov 2024 02:14:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F
by Amanda Hwang (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Amanda Hwang. Hello Dtrain Hsu, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85206?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F ...................................................................... mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:F Change the ram_id to 1 for MT62F2G32D4DS-020 WT:F based on the hardware schematic MB_SCH_1102A. BUG=b:372395010 TEST=Run part_id_gen tool and check the generated files. Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk M src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt M src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85206/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3 Gerrit-Change-Number: 85206 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: ec/acpi/ec.c: Promote timeout messages to errors
by Elyes Haouas (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Elyes HAOUAS, Nicholas Sudsgaard. Elyes Haouas has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/85229?usp=email ) Change subject: ec/acpi/ec.c: Promote timeout messages to errors ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85229?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60be6191dcd8ff576fa525f08720b6ea2d0a7454 Gerrit-Change-Number: 85229 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes HAOUAS Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 01:24:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Yidi Lin (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84497?usp=email ) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... Patch Set 34: (2 comments) File src/soc/mediatek/mt8196/mtcmos.c: https://review.coreboot.org/c/coreboot/+/84497/comment/f2d69c42_004158bf?us… : PS34, Line 150: CB_TYPE_PRE_OFF_SRAM, : CB_TYPE_POST_ON_SRAM, we don't need them in our case. https://review.coreboot.org/c/coreboot/+/84497/comment/5b19c94a_bac170b5?us… : PS34, Line 368: int mtcmos_cb_register(struct mtcmos_cb *cb) : { : struct mtcmos_cb *item = NULL; : bool exist = false; : : if (!cb) { : printk(BIOS_ERR, "node is NULL\n"); : return -EINVAL; : } : : if (!cb->name) { : printk(BIOS_ERR, "callback name NULL\n"); : return -EINVAL; : } : : if (!cb->pre_off && !cb->pre_on && !cb->post_on && !cb->post_off) { : printk(BIOS_ERR, "callback api NULL\n"); : return -EINVAL; : } : : /* add node to link list */ : list_for_each(item, mtcmos_cb_head, node) { : if (!strcmp(item->name, cb->name)) { : exist = true; : break; : } : } : if (exist) { : printk(BIOS_ERR, "ERR: %s exist\n", cb->name); : return -EEXIST; : } : : list_insert_after(&cb->node, &mtcmos_cb_head); : return 0; : } : : static int mtcmos_callback(u32 id, enum mtcmos_cb_type type) : { : struct mtcmos_cb *cb; : int ret = 0; : : list_for_each(cb, mtcmos_cb_head, node) { : if (cb->id == id) { : switch (type) { : case CB_TYPE_PRE_ON: : if (cb->pre_on) : ret = cb->pre_on(); : break; : case CB_TYPE_POST_ON: : if (cb->post_on) : ret = cb->post_on(); : break; : case CB_TYPE_PRE_OFF: : if (cb->pre_off) : ret = cb->pre_off(); : break; : case CB_TYPE_POST_OFF: : if (cb->post_off) : ret = cb->post_off(); : break; : case CB_TYPE_POST_ON_SRAM: : if (cb->post_on_sram) : ret = cb->post_on_sram(); : break; : case CB_TYPE_PRE_OFF_SRAM: : if (cb->pre_off_sram) : ret = cb->pre_off_sram(); : break; : default: : printk(BIOS_ERR, "%s(%u, %d) invalid type\n", __func__, id, type); : return -EINVAL; : } : : if (ret) : break; : } : } : : if (ret) : printk(BIOS_ERR, "%s(%u, %d) failed(%d)\n", __func__, id, type, ret); : : return ret; : } : : static inline int mtcmos_pre_on_callback(u32 id) : { : return mtcmos_callback(id, CB_TYPE_PRE_ON); : } : : static inline int mtcmos_pre_off_callback(u32 id) : { : return mtcmos_callback(id, CB_TYPE_PRE_OFF); : } : : static inline int mtcmos_post_on_callback(u32 id) : { : return mtcmos_callback(id, CB_TYPE_POST_ON); : } : : static inline int mtcmos_post_off_callback(u32 id) : { : return mtcmos_callback(id, CB_TYPE_POST_OFF); : } : : static inline int mtcmos_pre_off_sram_callback(u32 id) : { : return mtcmos_callback(id, CB_TYPE_PRE_OFF_SRAM); : } : : static inline int mtcmos_post_on_sram_callback(u32 id) : { : return mtcmos_callback(id, CB_TYPE_POST_ON_SRAM); : } I don't think it is worth to add such complex logic to register the callback for only for `4` types of mtcmos? (1 in mtcmos.c and 3 in mmfra_pd.c) These 4 types only need `PRE_ON`, `POST_ON`, `PRE_OFF` and `POST_OFF` settings. Can we just simplify them like this ? ``` mtcmos_disp_vcore_pre_on(); mtcmos_ctrl(MTCMOS_ID_DISP_VCORE, MTCMOS_POWER_ON); mtcmos_disp_vcore_post_on(); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 34 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 01:03:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MMinfra driver support
by Yidi Lin (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85188?usp=email ) Change subject: soc/mediatek/mt8196: Add MMinfra driver support ...................................................................... Patch Set 5: (2 comments) File src/soc/mediatek/mt8196/mminfra_pd.c: https://review.coreboot.org/c/coreboot/+/85188/comment/31bdd278_8542a847?us… : PS5, Line 35: while (read32p(MMINFRA_MM0_GALS_PROT_TX_RDY) != 0xff) : ; > I agree with Paul. With a timeout or retry limit, we can print an error log. […] You can implement a common function and pass register address and expected value to that function. ``` static void wait_for_write_done(u32 addr, u32 val) { write32p(addr, val); if (!wait_us(TIMEOUT_US, read32p(addr) == val))) die(... error message...); } ``` https://review.coreboot.org/c/coreboot/+/85188/comment/96634223_e4abcd24?us… : PS5, Line 66: static int pd_mm_infra_ao_pre_on(void) : { : return 0; : } : : static int pd_mm_infra_ao_post_on(void) : { : return 0; : } : : static int pd_mm_infra_ao_pre_off(void) : { : return 0; : } : : static int pd_mm_infra_ao_post_off(void) : { : return 0; : } Just remove if not used. `mtcmos_callback` will check if the callback is existed. -- To view, visit https://review.coreboot.org/c/coreboot/+/85188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75 Gerrit-Change-Number: 85188 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 22 Nov 2024 01:02:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Name of user not set (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email ) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... Patch Set 64: (1 comment) File src/mainboard/intel/frost_creek/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/83322/comment/7feb6086_2e10eb74?us… : PS19, Line 3: // IO-Trap at 0x800. This is the ACPI->SMI communication interface. > The object and method defined in this file is not referenced any where in the whole ASL source file, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 64 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 22 Nov 2024 00:09:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Held, Felix Singer, Frans Hendriks, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 60: (1 comment) File src/soc/intel/snowridge/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/83321/comment/e57a5512_36f08cbc?us… : PS28, Line 55: const struct mem_spd spd_info = { : .topo = MEM_TOPO_DIMM_MODULE, : .smbus[0] = {.addr_dimm[0] = SPD_DIMM_ADDR(0, 0), : .addr_dimm[1] = SPD_DIMM_ADDR(0, 1)}, : .smbus[1] = {.addr_dimm[0] = SPD_DIMM_ADDR(1, 0), : .addr_dimm[1] = SPD_DIMM_ADDR(1, 1)}, : }; > The mapping is standard. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 60 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 22 Nov 2024 00:09:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Held, Felix Singer, Frans Hendriks, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 60: (1 comment) File src/soc/intel/snowridge/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/83321/comment/1f33ff4e_890314ed?us… : PS28, Line 55: const struct mem_spd spd_info = { : .topo = MEM_TOPO_DIMM_MODULE, : .smbus[0] = {.addr_dimm[0] = SPD_DIMM_ADDR(0, 0), : .addr_dimm[1] = SPD_DIMM_ADDR(0, 1)}, : .smbus[1] = {.addr_dimm[0] = SPD_DIMM_ADDR(1, 0), : .addr_dimm[1] = SPD_DIMM_ADDR(1, 1)}, : }; > Snow Ridge SoC has one Integrated Memory Controller containing 2 SPD SMBus, each SMBus is connected […] The mapping is standard. If there slots without DRAMs, the first byte of SPD data would less than 0 and the current code could handle that. -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 60 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 22 Nov 2024 00:07:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: [WIP] soc/amd/common/psp: add delay after boot done command in PSP SM...
by Felix Held (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85237?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [WIP] soc/amd/common/psp: add delay after boot done command in PSP SMI case ...................................................................... [WIP] soc/amd/common/psp: add delay after boot done command in PSP SMI case When the PSP SMI support is enabled, the PSP might send PSP SMI commands to the SMI handler to access the SPI flash. Since coreboot is booting quite fast and especially when DEBUG_SMI is enabled causing additional delays in the PSP SMI handler, this seems to interfere with the Windows kernel or some WIndows kernel driver, causing the OS to get stuck early in the boot process somewhere between when it sends the enter ACPI mode SMI and when it starts the boot animation. Adding a 5 second delay after the boot done PSP mailbox command in case SOC_AMD_COMMON_BLOCK_PSP_SMI is selected and additional 5 seconds when DEBUG_SMI is selected too seems to makes sure that this will be done before the OS takes over which avoids the problem. The problem hasn't been fully root-cause yet, so for now this patch mainly treats the symptoms. TEST=Now Windows 10 boots successfully every time when the PSP SMI support is enabled. Before that the first boot after power on failed due to PSP SMI flash access activity or possibly due to the PSP not being done with its flash write and RPMC activity. In subsequent boots no flash access PSP SMIs were sent from the PSP and the system booted successfully. Change-Id: Icd4b76af829cfaa48e02da2ed224599b863af3b0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85237/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd4b76af829cfaa48e02da2ed224599b863af3b0 Gerrit-Change-Number: 85237 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/rex/var/ovis: Fix variant_update_cpu_power_limits call
by Jérémy Compostella (Code Review) 22 Nov '24

22 Nov '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85245?usp=email to look at the new patch set (#3). Change subject: mb/google/rex/var/ovis: Fix variant_update_cpu_power_limits call ...................................................................... mb/google/rex/var/ovis: Fix variant_update_cpu_power_limits call Change-Id: Id2cf95839fb10f07412175cd7f162d83ebdddfe0 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c 1 file changed, 19 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85245/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2cf95839fb10f07412175cd7f162d83ebdddfe0 Gerrit-Change-Number: 85245 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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coreboot-gerrit November 2024