coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: include/device/pci_ids.h: Add DIDs for Touch controller
by Cliff Huang (Code Review) 21 Nov '24

21 Nov '24

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[S] Change in coreboot[main]: acpi/acpigen: generate Create*Field() from name string directly
by Cliff Huang (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Kyoung Il Kim, Lance Zhao, Subrata Banik, Tim Wawrzynczak. Hello Bora Guvendik, Jérémy Compostella, Kyoung Il Kim, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85197?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: acpi/acpigen: generate Create*Field() from name string directly ...................................................................... acpi/acpigen: generate Create*Field() from name string directly The following functions are added: _create_buffer_field acpigen_write_create_buffer_byte_field acpigen_write_create_buffer_word_field acpigen_write_create_buffer_dword_field acpigen_write_create_buffer_qword_field These functions are to generate: CreateByteField (<namestring> , offset, <field name>) CreateWordField (<namestring> , offset, <field name>) CreateDWordField (<namestring> , offset, <field name>) CreateQWordField (<namestring> , offset, <field name>) NOTE: There are set of acpigen_write_create_[byte/word/dword/qword]_field functions already, but the field can only be created from Arg[n] or Local[n] variable objects. A Name object must be first assigned to such variable. The new functions here will allow us to create field directly from Name object. BUG=none Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915 --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85197/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915 Gerrit-Change-Number: 85197 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

1 0

[L] Change in coreboot[main]: [WIP,UNTESTED] soc/amd/common/psp: add support for early PSP v2 acces...
by Felix Held (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85242?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: [WIP,UNTESTED] soc/amd/common/psp: add support for early PSP v2 access via SMN ...................................................................... [WIP,UNTESTED] soc/amd/common/psp: add support for early PSP v2 access via SMN The MMIO mapping of the PSP mailbox registers can only be accessed once the FSP or in the future openSIL has initialized the PSP MMIO region. Before that, the PSP mailbox registers can only be accessed via their SMN mapping. TODO Change-Id: Ice23d85b22a1974f8a0c100a16ac210073cc22fc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.mk M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c A src/soc/amd/common/block/psp/psp_gen2_mmio.c A src/soc/amd/common/block/psp/psp_gen2_smn.c 7 files changed, 176 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85242/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice23d85b22a1974f8a0c100a16ac210073cc22fc Gerrit-Change-Number: 85242 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: [NOTFORMERGE] test case for SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS
by Felix Held (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85243?usp=email ) Change subject: [NOTFORMERGE] test case for SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS ...................................................................... [NOTFORMERGE] test case for SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS Change-Id: Ia4097aa1de7c7a811cb91cfe6cbb9a412aa20042 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85243/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f450e29..93b23e2 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -78,6 +78,7 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI select HAVE_X86_64_SUPPORT + select SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS help AMD Picasso support -- To view, visit https://review.coreboot.org/c/coreboot/+/85243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4097aa1de7c7a811cb91cfe6cbb9a412aa20042 Gerrit-Change-Number: 85243 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

1 0

[L] Change in coreboot[main]: [WIP,UNTESTED] soc/amd/common/psp: add support for early PSP v2 acces...
by Felix Held (Code Review) 21 Nov '24

21 Nov '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85242?usp=email ) Change subject: [WIP,UNTESTED] soc/amd/common/psp: add support for early PSP v2 access via SMN ...................................................................... [WIP,UNTESTED] soc/amd/common/psp: add support for early PSP v2 access via SMN The MMIO mapping of the PSP mailbox registers can only be accessed once the FSP or in the future openSIL has initialized the PSP MMIO region. Before that, the PSP mailbox registers can only be accessed via their SMN mapping. TODO Change-Id: Ice23d85b22a1974f8a0c100a16ac210073cc22fc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.mk M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c A src/soc/amd/common/block/psp/psp_gen2_mmio.c A src/soc/amd/common/block/psp/psp_gen2_smn.c 7 files changed, 176 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85242/1 diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 3ae5e43..f76d78d 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -20,6 +20,14 @@ help Used by the PSP in AMD family 17h, 19h and possibly newer CPUs. +config SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + bool + depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_SMN + help + Allow PSP mailbox access in bootblock and romstage using the SMN + access method to the mailbox registers. + config SOC_AMD_PSP_SELECTABLE_SMU_FW bool help diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index dc811f90..7e0cc25 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y) -romstage-y += psp.c ramstage-y += psp.c smm-y += psp.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi.c @@ -15,6 +14,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) +romstage-y += psp.c romstage-y += psp_gen1.c ramstage-y += psp_gen1.c @@ -25,12 +25,22 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2),y) +ifeq ($(SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS),y) +bootblock-y += psp.c +bootblock-y += psp_gen2.c +bootblock-y += psp_gen2_smn.c +romstage-y += psp.c romstage-y += psp_gen2.c +romstage-y += psp_gen2_smn.c +endif # SOC_AMD_COMMON_BLOCK_PSP_GEN2_EARLY_ACCESS + ramstage-y += psp_gen2.c +ramstage-y += psp_gen2_mmio.c ramstage-$(CONFIG_PSP_PLATFORM_SECURE_BOOT) += psb.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) += tpm.c smm-y += psp_gen2.c +smm-y += psp_gen2_mmio.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi_flash_gen2.c smm-y += psp_smm_gen2.c diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c index 5e497a2..71b766b 100644 --- a/src/soc/amd/common/block/psp/psb.c +++ b/src/soc/amd/common/block/psp/psb.c @@ -84,13 +84,13 @@ static enum cb_err get_psb_status(uint32_t *psb_status_value) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + const uint64_t base = get_psp_base(); - if (!psp_mmio) { + if (!base) { printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); return CB_ERR; } - *psb_status_value = read32p(psp_mmio | PSB_STATUS_OFFSET); + *psb_status_value = psp_read32(base, PSB_STATUS_OFFSET); return CB_SUCCESS; } diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index d11199d..a2d7e4c 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -146,7 +146,11 @@ MBOX_PSP_SPI_BUSY = 0x0b, }; -uintptr_t get_psp_mmio_base(void); +/* TODO */ +uint64_t psp_get_base(void); +uint32_t psp_read32(uint64_t base, uint32_t offset); +void psp_write32(uint64_t base, uint32_t offset, uint32_t data); +void psp_write64(uint64_t base, uint32_t offset, uint64_t data); void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 21c1f2a..05e3971 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -1,86 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/psp.h> +#include <console/console.h> +#include <device/mmio.h> #include <timer.h> #include <types.h> -#include <amdblocks/psp.h> -#include <amdblocks/root_complex.h> -#include <amdblocks/smn.h> -#include <device/mmio.h> #include "psp_def.h" #define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ #define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */ -#define IOHC_MISC_PSP_MMIO_REG 0x2e0 - -static uint64_t get_psp_mmio_mask(void) -{ - const struct non_pci_mmio_reg *mmio_regs; - size_t reg_count; - mmio_regs = get_iohc_non_pci_mmio_regs(&reg_count); - - for (size_t i = 0; i < reg_count; i++) { - if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG) - return mmio_regs[i].mask; - } - - printk(BIOS_ERR, "No PSP MMIO register description found.\n"); - return 0; -} - -#define PSP_MMIO_LOCK BIT(8) - -/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM, - so we have to read this from the hardware registers */ -uintptr_t get_psp_mmio_base(void) -{ - static uintptr_t psp_mmio_base; - const struct domain_iohc_info *iohc; - size_t iohc_count; - - if (psp_mmio_base) - return psp_mmio_base; - - iohc = get_iohc_info(&iohc_count); - const uint64_t psp_mmio_mask = get_psp_mmio_mask(); - - if (!psp_mmio_mask) - return 0; - - for (size_t i = 0; i < iohc_count; i++) { - uint64_t reg64 = smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG); - - if (!(reg64 & IOHC_MMIO_EN)) - continue; - - const uint64_t base = reg64 & psp_mmio_mask; - - if (ENV_X86_32 && base >= 4ull * GiB) { - printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n"); - continue; - } - - /* If the PSP MMIO base is enabled but the register isn't locked, set the lock - bit. This shouldn't happen, but better be a bit too careful here */ - if (!(reg64 & PSP_MMIO_LOCK)) { - printk(BIOS_WARNING, "Enabled PSP MMIO in domain %zu isn't locked. " - "Locking it.\n", i); - reg64 |= PSP_MMIO_LOCK; - /* Since the lock bit lives in the lower one of the two 32 bit SMN - registers, we only need to write that one to lock it */ - smn_write32(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG, - reg64 & 0xffffffff); - } - - psp_mmio_base = base; - } - - if (!psp_mmio_base) - printk(BIOS_ERR, "No usable PSP MMIO found.\n"); - - return psp_mmio_base; -} - union pspv2_mbox_command { uint32_t val; struct pspv2_mbox_cmd_fields { @@ -92,37 +21,37 @@ } __packed fields; }; -static uint16_t rd_mbox_sts(uintptr_t psp_mmio) +static uint16_t rd_mbox_sts(uint64_t base) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); return tmp.fields.mbox_status; } -static void wr_mbox_cmd(uintptr_t psp_mmio, uint8_t cmd) +static void wr_mbox_cmd(uint64_t base, uint8_t cmd) { union pspv2_mbox_command tmp = { .val = 0 }; /* Write entire 32-bit area to begin command execution */ tmp.fields.mbox_command = cmd; - write32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET, tmp.val); + psp_write32(base, PSP_MAILBOX_COMMAND_OFFSET, tmp.val); } -static uint8_t rd_mbox_recovery(uintptr_t psp_mmio) +static uint8_t rd_mbox_recovery(uint64_t base) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); return !!tmp.fields.recovery; } -static void wr_mbox_buffer_ptr(uintptr_t psp_mmio, void *buffer) +static void wr_mbox_buffer_ptr(uint64_t base, void *buffer) { - write64p(psp_mmio | PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); + psp_write64(base, PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); } -static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) +static int wait_command(uint64_t base, bool wait_for_ready) { union pspv2_mbox_command and_mask = { .val = ~0 }; union pspv2_mbox_command expected = { .val = 0 }; @@ -140,7 +69,7 @@ stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); do { - tmp = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp = psp_read32(base, PSP_MAILBOX_COMMAND_OFFSET); tmp &= ~and_mask.val; if (tmp == expected.val) return 0; @@ -151,27 +80,27 @@ int send_psp_command(uint32_t command, void *buffer) { - const uintptr_t psp_mmio = get_psp_mmio_base(); - if (!psp_mmio) + const uint64_t base = psp_get_base(); + if (!base) return -PSPSTS_NOBASE; - if (rd_mbox_recovery(psp_mmio)) + if (rd_mbox_recovery(base)) return -PSPSTS_RECOVERY; - if (wait_command(psp_mmio, true)) + if (wait_command(base, true)) return -PSPSTS_CMD_TIMEOUT; /* set address of command-response buffer and write command register */ - wr_mbox_buffer_ptr(psp_mmio, buffer); - wr_mbox_cmd(psp_mmio, command); + wr_mbox_buffer_ptr(base, buffer); + wr_mbox_cmd(base, command); /* PSP clears command register when complete. All commands except * SxInfo set the Ready bit. */ - if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO)) + if (wait_command(base, command != MBOX_BIOS_CMD_SX_INFO)) return -PSPSTS_CMD_TIMEOUT; /* check delivery status */ - if (rd_mbox_sts(psp_mmio)) + if (rd_mbox_sts(base)) return -PSPSTS_SEND_ERROR; return 0; @@ -202,12 +131,12 @@ enum cb_err soc_read_c2p38(uint32_t *msg_38_value) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + const uint64_t base = psp_get_base(); - if (!psp_mmio) { + if (!base) { printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); return CB_ERR; } - *msg_38_value = read32p(psp_mmio | CORE_2_PSP_MSG_38_OFFSET); + *msg_38_value = psp_read32(base, CORE_2_PSP_MSG_38_OFFSET); return CB_SUCCESS; } diff --git a/src/soc/amd/common/block/psp/psp_gen2_mmio.c b/src/soc/amd/common/block/psp/psp_gen2_mmio.c new file mode 100644 index 0000000..14f0327 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen2_mmio.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/psp.h> +#include <amdblocks/root_complex.h> +#include <amdblocks/smn.h> +#include <console/console.h> +#include <device/mmio.h> +#include <types.h> +#include "psp_def.h" + +#define IOHC_MISC_PSP_MMIO_REG 0x2e0 + +static uint64_t get_psp_mmio_mask(void) +{ + const struct non_pci_mmio_reg *mmio_regs; + size_t reg_count; + mmio_regs = get_iohc_non_pci_mmio_regs(&reg_count); + + for (size_t i = 0; i < reg_count; i++) { + if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG) + return mmio_regs[i].mask; + } + + printk(BIOS_ERR, "No PSP MMIO register description found.\n"); + return 0; +} + +#define PSP_MMIO_LOCK BIT(8) + +/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM, + so we have to read this from the hardware registers */ +static uintptr_t get_psp_mmio_base(void) +{ + static uintptr_t psp_mmio_base; + const struct domain_iohc_info *iohc; + size_t iohc_count; + + if (psp_mmio_base) + return psp_mmio_base; + + iohc = get_iohc_info(&iohc_count); + const uint64_t psp_mmio_mask = get_psp_mmio_mask(); + + if (!psp_mmio_mask) + return 0; + + for (size_t i = 0; i < iohc_count; i++) { + uint64_t reg64 = smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG); + + if (!(reg64 & IOHC_MMIO_EN)) + continue; + + const uint64_t base = reg64 & psp_mmio_mask; + + if (ENV_X86_32 && base >= 4ull * GiB) { + printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n"); + continue; + } + + /* If the PSP MMIO base is enabled but the register isn't locked, set the lock + bit. This shouldn't happen, but better be a bit too careful here */ + if (!(reg64 & PSP_MMIO_LOCK)) { + printk(BIOS_WARNING, "Enabled PSP MMIO in domain %zu isn't locked. " + "Locking it.\n", i); + reg64 |= PSP_MMIO_LOCK; + /* Since the lock bit lives in the lower one of the two 32 bit SMN + registers, we only need to write that one to lock it */ + smn_write32(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG, + reg64 & 0xffffffff); + } + + psp_mmio_base = base; + } + + if (!psp_mmio_base) + printk(BIOS_ERR, "No usable PSP MMIO found.\n"); + + return psp_mmio_base; +} + +uint64_t psp_get_base(void) +{ + return get_psp_mmio_base(); +} + +uint32_t psp_read32(uint64_t base, uint32_t offset) +{ + return read32p((uintptr_t)(base | offset)); +} + +void psp_write32(uint64_t base, uint32_t offset, uint32_t data) +{ + write32p((uintptr_t)(base | offset), data); +} + +void psp_write64(uint64_t base, uint32_t offset, uint64_t data) +{ + write64p((uintptr_t)(base | offset), data); +} diff --git a/src/soc/amd/common/block/psp/psp_gen2_smn.c b/src/soc/amd/common/block/psp/psp_gen2_smn.c new file mode 100644 index 0000000..16ec827 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_gen2_smn.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/psp.h> +#include <amdblocks/smn.h> +#include <types.h> +#include "psp_def.h" + +uint64_t psp_get_base(void) +{ + return SMN_PSP_PUBLIC_BASE; +} + +uint32_t psp_read32(uint64_t base, uint32_t offset) +{ + return smn_read32(base | offset); +} + +void psp_write32(uint64_t base, uint32_t offset, uint32_t data) +{ + smn_write32(base | offset, data); +} + +void psp_write64(uint64_t base, uint32_t offset, uint64_t data) +{ + write64p((uintptr_t)(base | offset), data); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/85242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice23d85b22a1974f8a0c100a16ac210073cc22fc Gerrit-Change-Number: 85242 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: acpi/acpigen: generate Create*Field() from name string directly
by Cliff Huang (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Kyoung Il Kim, Lance Zhao, Subrata Banik, Tim Wawrzynczak. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85197?usp=email ) Change subject: acpi/acpigen: generate Create*Field() from name string directly ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85197/comment/5613c250_d95df931?us… : PS1, Line 7: acpi/acpigen: generate Create*Field() from name string directly > nit: What do you mean by `directly` ? There are set of acpigen_write_create_[byte/word/dword/qword]_field functions already, but the field can be be created from Arg[n] or Local[n] variable objects. A Name object must be first assigned to such variables. The new functions here will allow to create directly from Name object. Let me add more details in the comment messages. File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/85197/comment/e7a875e6_b3102a84?us… : PS1, Line 2441: byte > word_offset ? offset in byte. -- To view, visit https://review.coreboot.org/c/coreboot/+/85197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915 Gerrit-Change-Number: 85197 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 18:37:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: drivers/crb: Return an accurate status
by Matt DeVillier (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85228?usp=email ) Change subject: drivers/crb: Return an accurate status ...................................................................... Patch Set 1: (1 comment) File src/drivers/crb/tis.c: https://review.coreboot.org/c/coreboot/+/85228/comment/46bc45dd_77299931?us… : PS1, Line 93: ptt_active looks like you might need to guard using `HAVE_INTEL_PTT` as above -- To view, visit https://review.coreboot.org/c/coreboot/+/85228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8236021bf0e1264646971cff9c998fac99ac220 Gerrit-Change-Number: 85228 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 21 Nov 2024 18:36:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: include/device/pci_ids.h: Add DIDs for Touch controller
by Cliff Huang (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Kyoung Il Kim, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85196?usp=email ) Change subject: include/device/pci_ids.h: Add DIDs for Touch controller ...................................................................... Patch Set 1: (5 comments) Patchset: PS1: > should be clubbed with CB:85198 sure. will this change move to 85198. Commit Message: https://review.coreboot.org/c/coreboot/+/85196/comment/0bf6aa28_0232fb74?us… : PS1, Line 7: include/device/pci_ids.h: Add DIDs for Touch controller > Looking at git log, `device/pci_ids: ` prefix is enough. […] MTL DIDs are there there, but just to rename according to https://review.coreboot.org/c/coreboot/+/81330/comment/b7f5bc9d_a34d6a77/ Anyways, since Subrata suggests to move this to other CL. I will add this in the comment messages. https://review.coreboot.org/c/coreboot/+/85196/comment/501826b6_c9accb3f?us… : PS1, Line 13: 0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0 > nit: If this is default, shouldn't the name of the constant be suffixed with `_DEFAULT` instead of ` […] ok https://review.coreboot.org/c/coreboot/+/85196/comment/50d879ee_29087dad?us… : PS1, Line 13: 0x7ea4 > 0x7ea4 ? or 0x7e4a ? 0x7e4a is correct one. thx https://review.coreboot.org/c/coreboot/+/85196/comment/53c2cf19_00ab6d75?us… : PS1, Line 19: > Unnecessary leading space Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9acd9dbba1cca1bb90bf49dbc3a1882262bd474 Gerrit-Change-Number: 85196 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 18:29:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: vc/google/chromeos/sar: Use size_t instead of int for size function
by Jérémy Compostella (Code Review) 21 Nov '24

21 Nov '24

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85178?usp=email ) Change subject: vc/google/chromeos/sar: Use size_t instead of int for size function ...................................................................... vc/google/chromeos/sar: Use size_t instead of int for size function BUG=b:346600091 TEST=Compilation successful Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e225 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85178 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/google/chromeos/sar.c 1 file changed, 8 insertions(+), 8 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Elyes Haouas: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 50c59d5..e8d4410 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -53,7 +53,7 @@ return sar_bin; } -static int sar_table_size(const struct sar_profile *sar) +static size_t sar_table_size(const struct sar_profile *sar) { if (sar == NULL) return 0; @@ -62,7 +62,7 @@ sar->subbands_count)); } -static int wgds_table_size(const struct geo_profile *geo) +static size_t wgds_table_size(const struct geo_profile *geo) { if (geo == NULL) return 0; @@ -70,7 +70,7 @@ return sizeof(struct geo_profile) + (geo->chains_count * geo->bands_count); } -static int gain_table_size(const struct gain_profile *gain) +static size_t gain_table_size(const struct gain_profile *gain) { if (gain == NULL) return 0; @@ -78,7 +78,7 @@ return sizeof(struct gain_profile) + (gain->chains_count * gain->bands_count); } -static int sar_avg_table_size(const struct avg_profile *sar_avg) +static size_t sar_avg_table_size(const struct avg_profile *sar_avg) { if (sar_avg == NULL) return 0; @@ -86,7 +86,7 @@ return sizeof(struct avg_profile); } -static int dsm_table_size(const struct dsm_profile *dsm) +static size_t dsm_table_size(const struct dsm_profile *dsm) { if (dsm == NULL) return 0; @@ -94,7 +94,7 @@ return sizeof(struct dsm_profile); } -static int bsar_table_size(const struct bsar_profile *bsar) +static size_t bsar_table_size(const struct bsar_profile *bsar) { if (bsar == NULL) return 0; @@ -102,7 +102,7 @@ return sizeof(struct bsar_profile); } -static int wbem_table_size(const struct wbem_profile *wbem) +static size_t wbem_table_size(const struct wbem_profile *wbem) { if (wbem == NULL) return 0; @@ -121,7 +121,7 @@ return false; } -static int sar_header_size(void) +static size_t sar_header_size(void) { return (MAX_PROFILE_COUNT * sizeof(uint16_t)) + sizeof(struct sar_header); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e225 Gerrit-Change-Number: 85178 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable ALC721 on fatcat mainboard
by Varun Upadhyay (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N, Subrata Banik. Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85240?usp=email ) Change subject: mb/google/fatcat: Enable ALC721 on fatcat mainboard ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2a19e9cca9a9dcec34f285086d0053aead4d176 Gerrit-Change-Number: 85240 Gerrit-PatchSet: 1 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 17:45:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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