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Change subject: soc/intel/xeon_sp: Improve IRQ routing for Gen6
......................................................................
soc/intel/xeon_sp: Improve IRQ routing for Gen6
1. Route IRQ for on-chip end-points only.
2. Route IRQ based on FSP programmed end-point device ID <->
PIRQ mapping.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/include/soc/irq.h
M src/soc/intel/xeon_sp/lpc_gen6.c
2 files changed, 52 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/85153/9
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Change subject: mb/google/brya: Create uldrenite variant
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/fatcat: Common Kconfig for ALC7XX soundwire codecs
......................................................................
Patch Set 4:
This change is ready for review.
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Change subject: soc/intel/xeon_sp: Fix debug print
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Good catch!
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 5:
(3 comments)
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/af8bbfa1_4670af71?us… :
PS4, Line 47: }
> that is correct.
Is there special reason that in SKX, the linear GSI assignment is not usable? I guess is to match the static _PRT reporting results?
https://review.coreboot.org/c/coreboot/+/85170/comment/9df52943_033dbd73?us… :
PS4, Line 49: i
> #include <arch/ioapic. […]
So, do we need to rebase this patch on https://review.coreboot.org/c/coreboot/+/85226/?https://review.coreboot.org/c/coreboot/+/85170/comment/0041f208_04c2bad1?us… :
PS4, Line 61: .enable_resources = pci_dev_enable_resources,
> it's a PCI endpoint device
Are 0x2036/0x2026 PCI root port devices?
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85170/comment/c0835dd3_613723c5?us… :
PS4, Line 15: from advertising wrong GSI addresses.
> Yes, it should be dropped on CPX as well. […]
Acknowledged
File src/soc/intel/xeon_sp/lpc_gen1.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/d43c19db_8aefa4f3?us… :
PS4, Line 14: register_new_ioapic_gsi0(IO_APIC_ADDR);
> Currently it's not created as dev object. […]
Acknowledged
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Change subject: commonlib/bsd/mem_chip_info: Add mem_chip_info_entry_density_bytes
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp/skx: Fix CPU init
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
TESTED = tiogapass?
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Attention is currently required from: Angel Pons, Name of user not set #1005283.
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79979?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mainboard: Add MSI MS-7788
......................................................................
mainboard: Add MSI MS-7788
HACKS:
* The SSKPD read hangs the boot, not sure why
* I disabled it and everything seems to work...
* I changed Sandybridge `chipset.cb` because I was
getting warnings in my logs about leftover
static devices
* This is definitely not the correct way to do
things, so I want to know what the right
course of action actually _is_
* Do I leave the warning be?
* Or is there something else I can do?
NOTES:
* Been running this BIOS for a while: it's working
well for the parts I've tested
* MSI h61m-p31/w8
* Winbond 25Q64FVSIG
* Fintek F71868A
* I haven't hooked this up because there is no
code specifically for this chip, I might
experiment with the F71869AD code in the
future, but right now it's working fine
without BIOS superio support
Working:
* PCIe graphics
* Integrated graphics (libgfxinit)
* USB (all ports)
* Ethernet
* All SATA ports
* Serial output
Yet-to-be-thoroughly-tested:
* Suspend states
Untested:
* PS/2
* PCIe x1 lane
Signed-off-by: mrhh69 <122405954+mrhh69(a)users.noreply.github.com>
Change-Id: Ia7830fcc7552e9734ec7c57e508a6a77f689e5b0
---
A src/mainboard/msi/ms7788/Kconfig
A src/mainboard/msi/ms7788/Kconfig.name
A src/mainboard/msi/ms7788/Makefile.mk
A src/mainboard/msi/ms7788/acpi/ec.asl
A src/mainboard/msi/ms7788/acpi/platform.asl
A src/mainboard/msi/ms7788/acpi/superio.asl
A src/mainboard/msi/ms7788/board_info.txt
A src/mainboard/msi/ms7788/data.vbt
A src/mainboard/msi/ms7788/devicetree.cb
A src/mainboard/msi/ms7788/dsdt.asl
A src/mainboard/msi/ms7788/gma-mainboard.ads
A src/mainboard/msi/ms7788/gpio.c
A src/mainboard/msi/ms7788/hda_verb.c
M src/northbridge/intel/sandybridge/chipset.cb
M src/northbridge/intel/sandybridge/romstage.c
15 files changed, 363 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/79979/6
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