coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and clock init support
by Yu-Ping Wu (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email ) Change subject: soc/mediatek/mt8196: Add PLL and clock init support ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Gerrit-Change-Number: 84495 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 02:35:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Guangjie Song (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Guangjie Song has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84497?usp=email ) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... Patch Set 27: (11 comments) File src/soc/mediatek/mt8196/mtcmos.c: https://review.coreboot.org/c/coreboot/+/84497/comment/929d412f_2baa83ab?us… : PS26, Line 257: MTCMOS_ID_SSUSB_DP_PHY_P0 > We don't need to store the `id` in `mtcmos_data`, if the array index is the id. Done https://review.coreboot.org/c/coreboot/+/84497/comment/60a43b57_9803319f?us… : PS26, Line 457: ret = -EINVAL; : break; > Print an error message and return `-EINVAL` directly. Done https://review.coreboot.org/c/coreboot/+/84497/comment/b703ad4d_b1551092?us… : PS26, Line 475: printk(BIOS_ERR, "%s failed(%d)\n", __func__, ret); > I think the error message could be further moved inside `mtcmos_callback()`, to further simplify the […] Done https://review.coreboot.org/c/coreboot/+/84497/comment/6e6a25d8_5dea1dc6?us… : PS26, Line 538: ( > remove Done https://review.coreboot.org/c/coreboot/+/84497/comment/51fd5ea2_70ee6caa?us… : PS26, Line 540: ( > remove Done https://review.coreboot.org/c/coreboot/+/84497/comment/ce8a39c6_c18389f1?us… : PS26, Line 591: const struct mtcmos_data md > Pass the const pointer instead. Done https://review.coreboot.org/c/coreboot/+/84497/comment/b5a7c327_cf5a3e04?us… : PS26, Line 640: mds[id] > Make this a local variable (as a pointer). Done https://review.coreboot.org/c/coreboot/+/84497/comment/4f322ee1_9d06e567?us… : PS26, Line 658: setbits32(ctl_addr, PWR_ISO); : setbits32(ctl_addr, PWR_CLK_DIS); : clrbits32(ctl_addr, PWR_RST_B); : clrbits32(ctl_addr, PWR_ON); > Can these be done in one clrsetbits32 call? no, here are requirements for the order of setting https://review.coreboot.org/c/coreboot/+/84497/comment/22b97279_ad315df3?us… : PS26, Line 690: clrbits32(ctl_addr, PWR_CLK_DIS); : clrbits32(ctl_addr, PWR_ISO); > One clrbits32 call? no, here are requirements for the order of setting https://review.coreboot.org/c/coreboot/+/84497/comment/414f3469_56614e6c?us… : PS26, Line 843: { > remove Done https://review.coreboot.org/c/coreboot/+/84497/comment/17a3dd09_41614c1b?us… : PS26, Line 886: mtcmos_cb_register > Is this the only caller of `mtcmos_cb_register`? Will there be other callers from other files? If no […] no, the api would be called in mminfra -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 02:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and clock init support
by Guangjie Song (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Guangjie Song has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email ) Change subject: soc/mediatek/mt8196: Add PLL and clock init support ...................................................................... Patch Set 27: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84495/comment/905b9721_0ef72dad?us… : PS26, Line 7: Clock > clock Done File src/soc/mediatek/mt8196/pll.c: https://review.coreboot.org/c/coreboot/+/84495/comment/079f99cc_baa1e849?us… : PS13, Line 1196: 30 > Agree with Yu-Ping. […] Done File src/soc/mediatek/mt8196/pll.c: https://review.coreboot.org/c/coreboot/+/84495/comment/9c6f79ad_0419d09e?us… : PS26, Line 863: ( > No need for the extra `()` Done https://review.coreboot.org/c/coreboot/+/84495/comment/03ee83f0_0194e401?us… : PS26, Line 1176: mmvote_mtcmos_mtcmos_table > `child_idx` is the same as `parent_idx`. […] it is expected now we remove the array to save space and initialize the corresponding registers according to the config rules -- To view, visit https://review.coreboot.org/c/coreboot/+/84495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Gerrit-Change-Number: 84495 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 02:28:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Jarried Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Guangjie Song, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84497?usp=email to look at the new patch set (#27). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... soc/mediatek/mt8196: Add mtcmos init support Add mtcmos init code and APIs for controlling power domain. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h A src/soc/mediatek/mt8196/mtcmos.c 5 files changed, 941 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84497/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and clock init support
by Jarried Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Hello Guangjie Song, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84495?usp=email to look at the new patch set (#27). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PLL and clock init support ...................................................................... soc/mediatek/mt8196: Add PLL and clock init support Add PLL and clock init code, frequency meter and APIs for raising little CPU frequency and set tvdpll frequency. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/include/soc/pll.h A src/soc/mediatek/mt8196/pll.c 6 files changed, 2,137 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84495/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/84495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Gerrit-Change-Number: 84495 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add Elan touchscreen
by Rui Zhou (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85015?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... mb/google/nissa/var/rull: Add Elan touchscreen Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. BUG=b:374629673 BRANCH=None TEST=Local build successfully and touchpanel function is normal Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85015/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XL] Change in coreboot[main]: RFC: Add initial support for the bootguarded framework tigerlake lapt...
by Alexandru Stan (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Christoph Pomaska, Felix Singer, J. Neuschäfer, Keith Hui, Martin L Roth, Mimoja, Paul Menzel. Alexandru Stan has posted comments on this change by Mimoja. ( https://review.coreboot.org/c/coreboot/+/62569?usp=email ) Change subject: RFC: Add initial support for the bootguarded framework tigerlake laptop (hx20) ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Alexandru - Would framework be interested in signing a bootblock so this could be used? […] Let's try to get anything booting first on some of our boards before we talk about signing (as there's probably future security implications). -- To view, visit https://review.coreboot.org/c/coreboot/+/62569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaf215cccae8836d691392e3e584f49f675f8456 Gerrit-Change-Number: 62569 Gerrit-PatchSet: 6 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexandru Stan <ams(a)frame.work> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: J. Neuschäfer <j.ne(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrik Tesarik <depate(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: J. Neuschäfer <j.ne(a)posteo.net> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Christoph Pomaska <github(a)slrie.de> Gerrit-Comment-Date: Thu, 07 Nov 2024 00:55:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Robert Chen (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Eric Lai. Robert Chen has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email ) Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Please rebase this change on top of coreboot tree for Jenkin to verify this CL. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 00:52:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XL] Change in coreboot[main]: RFC: Add initial support for the bootguarded framework tigerlake lapt...
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Alexandru Stan, Christoph Pomaska, J. Neuschäfer, Keith Hui, Mimoja, Paul Menzel. Felix Singer has posted comments on this change by Mimoja. ( https://review.coreboot.org/c/coreboot/+/62569?usp=email ) Change subject: RFC: Add initial support for the bootguarded framework tigerlake laptop (hx20) ...................................................................... Patch Set 6: Code-Review-1 (1 comment) Patchset: PS6: This port does not work. -- To view, visit https://review.coreboot.org/c/coreboot/+/62569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaf215cccae8836d691392e3e584f49f675f8456 Gerrit-Change-Number: 62569 Gerrit-PatchSet: 6 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexandru Stan <ams(a)frame.work> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: J. Neuschäfer <j.ne(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrik Tesarik <depate(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexandru Stan <ams(a)frame.work> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: J. Neuschäfer <j.ne(a)posteo.net> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Christoph Pomaska <github(a)slrie.de> Gerrit-Comment-Date: Thu, 07 Nov 2024 00:44:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Add printk log missing carriage return character
by Jérémy Compostella (Code Review) 07 Nov '24

07 Nov '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85020?usp=email ) Change subject: mb/google/fatcat: Add printk log missing carriage return character ...................................................................... mb/google/fatcat: Add printk log missing carriage return character Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85020/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 46ef6a8..7c95f38 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -456,7 +456,7 @@ void fw_config_configure_pre_mem_gpio(void) { if (!fw_config_is_provisioned()) { - printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing"); + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing\n"); return; } @@ -501,7 +501,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (!fw_config_is_provisioned()) { - printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing"); + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing\n"); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Gerrit-Change-Number: 85020 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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coreboot-gerrit November 2024