coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Name of user not set (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel, yuchi.chen(a)intel.com. Hello Angel Pons, Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83318?usp=email to look at the new patch set (#27). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... soc/intel/common/systemagent_server: Add server platform system agent Intel server process has a different system agent design, it has some differences with client platform such as (1) no BDSM and BGSM registers; (2) different alignment size and bit fields in TOLUD, TOUUD and TSEG registers. Thus this patch adds a new common block for server platform system agent. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/systemagent_server.h A src/soc/intel/common/block/systemagent-server/Kconfig A src/soc/intel/common/block/systemagent-server/Makefile.mk A src/soc/intel/common/block/systemagent-server/common.c A src/soc/intel/common/block/systemagent-server/memmap.c A src/soc/intel/common/block/systemagent-server/systemagent.c A src/soc/intel/common/block/systemagent-server/systemagent_early.c 7 files changed, 416 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 27 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Fix variant devicetree update
by Robert Chen (Code Review) 01 Nov '24

01 Nov '24

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84952?usp=email ) Change subject: mb/google/dedede/var/drawcia: Fix variant devicetree update ...................................................................... mb/google/dedede/var/drawcia: Fix variant devicetree update External VR update should be execute after 0xb board version. BUG=None BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I4a1ca49b9681d9a75194016353997c91eb49d198 --- M src/mainboard/google/dedede/variants/drawcia/ramstage.c 1 file changed, 20 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/84952/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c index aed160e..e9ce712 100644 --- a/src/mainboard/google/dedede/variants/drawcia/ramstage.c +++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c @@ -9,26 +9,37 @@ static void ext_vr_update(void) { + uint32_t board_version = board_id(); struct soc_intel_jasperlake_config *cfg = config_of_soc(); + + /* Power IC remove from board version 0xc */ + if (board_version < 0xc) + return; + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_ABSENT))) cfg->disable_external_bypass_vr = 1; } -void variant_devtree_update(void) +static void update_lte_device(void) { uint32_t board_version = board_id(); - struct device *lte_usb2 = DEV_PTR(lte_usb2); - struct drivers_usb_acpi_config *config; - struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0); + struct device *lte_usb2 = DEV_PTR(lte_usb2); + struct drivers_usb_acpi_config *config; + struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0); /* board version 9 is drawper EVT */ - if (board_version > 9) - return; + if (board_version > 9) + return; - if (lte_usb2 == NULL) - return; + if (lte_usb2 == NULL) + return; config = config_of(lte_usb2); - config->reset_gpio = lte_reset_gpio; + config->reset_gpio = lte_reset_gpio; +} + +void variant_devtree_update(void) +{ + update_lte_device(); ext_vr_update(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a1ca49b9681d9a75194016353997c91eb49d198 Gerrit-Change-Number: 84952 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Shuo Liu (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 26: (2 comments) File src/soc/intel/common/block/systemagent-server/Kconfig: https://review.coreboot.org/c/coreboot/+/83318/comment/c004585d_7e55bf3b?us… : PS26, Line 15: treated as 1s. to clean up? https://review.coreboot.org/c/coreboot/+/83318/comment/4d6622e2_7b759bb0?us… : PS26, Line 26: default 0x100000 to clean up? -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 26 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Nov 2024 09:09:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Name of user not set (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... Patch Set 25: (4 comments) File src/soc/intel/common/block/systemagent-server/memmap.c: https://review.coreboot.org/c/coreboot/+/83318/comment/0614ac0b_b29808de?us… : PS24, Line 23: */ > if you only support FSP_TEMP_RAM_EXIT now, can you assert instead? Added a `die()` here. File src/soc/intel/common/block/systemagent-server/systemagent.c: https://review.coreboot.org/c/coreboot/+/83318/comment/9063d06c_7a4b8212?us… : PS24, Line 76: continue; > if (mmio_descriptors[i].get_resource) { […] If `size` and `base` are not provided, get them from `get_resource()` function. https://review.coreboot.org/c/coreboot/+/83318/comment/287994b1_fb38b875?us… : PS24, Line 184: sa_server_soc_add_configurable_mmio_resources(dev, &index); > Maybe to merge these 2 MMIO config into 1 and do it for pch domain only. Done https://review.coreboot.org/c/coreboot/+/83318/comment/69ee4dab_36167ed5?us… : PS24, Line 191: .init = sa_server_soc_systemagent_init, > For the null implementation, can we skip the assignment directly? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 25 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Nov 2024 08:38:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Name of user not set (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel, yuchi.chen(a)intel.com. Hello Angel Pons, Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83318?usp=email to look at the new patch set (#26). Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... soc/intel/common/systemagent_server: Add server platform system agent Intel server process has a different system agent design, it has some differences with client platform such as (1) no BDSM and BGSM registers; (2) different alignment size and bit fields in TOLUD, TOUUD and TSEG registers. Thus this patch adds a new common block for server platform system agent. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/systemagent_server.h A src/soc/intel/common/block/systemagent-server/Kconfig A src/soc/intel/common/block/systemagent-server/Makefile.mk A src/soc/intel/common/block/systemagent-server/common.c A src/soc/intel/common/block/systemagent-server/memmap.c A src/soc/intel/common/block/systemagent-server/systemagent.c A src/soc/intel/common/block/systemagent-server/systemagent_early.c 7 files changed, 431 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 26 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#43). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/pch_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/dlb.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/itss.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 64 files changed, 4,859 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/43 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 43 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Name of user not set (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel, yuchi.chen(a)intel.com. Hello Angel Pons, Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83318?usp=email to look at the new patch set (#25). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... soc/intel/common/systemagent_server: Add server platform system agent Intel server process has a different system agent design, it has some differences with client platform such as (1) no BDSM and BGSM registers; (2) different alignment size and bit fields in TOLUD, TOUUD and TSEG registers. Thus this patch adds a new common block for server platform system agent. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/systemagent_server.h A src/soc/intel/common/block/systemagent-server/Kconfig A src/soc/intel/common/block/systemagent-server/Makefile.mk A src/soc/intel/common/block/systemagent-server/common.c A src/soc/intel/common/block/systemagent-server/memmap.c A src/soc/intel/common/block/systemagent-server/systemagent.c A src/soc/intel/common/block/systemagent-server/systemagent_early.c 7 files changed, 428 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 25 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism
by Lawrence Chang (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Nick Vaccaro, Paul Menzel, Simon Yang. Lawrence Chang has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email ) Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84866/comment/70cfc87d_2048af1b?us… : PS3, Line 13: Tested on Awasuki with RTL8852BE > Add details to the commit message Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Gerrit-Change-Number: 84866 Gerrit-PatchSet: 4 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: David Ruth <druth(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: David Ruth <druth(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 08:17:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lawrence Chang <lawrence.chang(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism
by Lawrence Chang (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Nick Vaccaro, Paul Menzel, Simon Yang. Lawrence Chang has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email ) Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84866/comment/7d9540ce_4a953c5f?us… : PS3, Line 13: Tested on Awasuki with RTL8852BE > Please add these details, and the command how to dump the root port configuration space. Add details to the commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/84866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Gerrit-Change-Number: 84866 Gerrit-PatchSet: 4 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: David Ruth <druth(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: David Ruth <druth(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 08:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lawrence Chang <lawrence.chang(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism
by Lawrence Chang (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Lawrence Chang, Nick Vaccaro, Simon Yang. Hello Curtis Chen, David Ruth, David Ruth, Jamie Chen, Nick Vaccaro, Simon Yang, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84866?usp=email to look at the new patch set (#4). Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ...................................................................... soc/intel/jasperlake: add support for RP LTR mechanism Reserve Root Port LTR mechanism in FSP, in case some devices need to optimize LTR. BUG=366383364 TEST=Tested on Awasuki with RTL8852BE use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable bit is offset 68h[10]. 00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01) 00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20 20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08 50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00 60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00 90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00 a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00 e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00 f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84 Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Signed-off-by: Lawrence Chang <lawrence.chang(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/84866/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Gerrit-Change-Number: 84866 Gerrit-PatchSet: 4 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: David Ruth <druth(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: David Ruth <druth(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com>

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coreboot-gerrit November 2024