coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: [RFC] device/resource: IOINDEX_SUBTRACTIVE oddities
by Martin L Roth (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Kyösti Mälkki. Martin L Roth has posted comments on this change by Kyösti Mälkki. ( https://review.coreboot.org/c/coreboot/+/64972?usp=email ) Change subject: [RFC] device/resource: IOINDEX_SUBTRACTIVE oddities ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: This seems reasonable to me, though the patch needs to be cleaned up. 3 of the files look like they're just adding blank lines now, only the Mediatek file is actually changing anything. Maybe someone from Mediatek can test and integrate this? -- To view, visit https://review.coreboot.org/c/coreboot/+/64972?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieff703ed39d69c8ef9edb2e8292ce82eb4e41351 Gerrit-Change-Number: 64972 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 18:29:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: RFC: Add initial support for the bootguarded framework tigerlake lapt...
by Martin L Roth (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Alexandru Stan, Christoph Pomaska, Felix Singer, J. Neuschäfer, Keith Hui, Mimoja, Paul Menzel. Martin L Roth has posted comments on this change by Mimoja. ( https://review.coreboot.org/c/coreboot/+/62569?usp=email ) Change subject: RFC: Add initial support for the bootguarded framework tigerlake laptop (hx20) ...................................................................... Patch Set 6: Code-Review+1 (2 comments) Patchset: PS6: Alexandru - Would framework be interested in signing a bootblock so this could be used? We have custom boards in the tree that aren't useful to people and this could be used as a reference even if people can't flash it directly to their boards, so I don't see a particular problem with having this in the tree. PS6: > In #coreboot@libera. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaf215cccae8836d691392e3e584f49f675f8456 Gerrit-Change-Number: 62569 Gerrit-PatchSet: 6 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexandru Stan <ams(a)frame.work> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: J. Neuschäfer <j.ne(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrik Tesarik <depate(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alexandru Stan <ams(a)frame.work> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: J. Neuschäfer <j.ne(a)posteo.net> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Christoph Pomaska <github(a)slrie.de> Gerrit-Comment-Date: Wed, 06 Nov 2024 18:23:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot
by Subrata Banik (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email ) Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/84996/comment/7bec0fcd_3762d3b1?us… : PS1, Line 200: if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) { > When you come out of global_reset, is the previous state S5? If not, then we will never end up disabling UFS. > > Atleast on my testing, the previous sleep state is not showing as S5. > > ``` > ␛[0m[INFO ] cse_lite: Set Boot Partition Info Command (RW)␛[0m > ␛[0m[DEBUG] HECI: Global Reset(Type:1) Command␛[0m > ␀␛[0m > ␛[0m > ␛[1m[NOTE ] coreboot-v1.9308_26_0.0.22-38623-g629ff30d2834 Sat Oct 19 18:42:55 UTC 2024 x86_32 romstage starting (log level: 8)...␛[0m > ␛[0m[DEBUG] pm1_sts: 8000 pm1_en: 0000 pm1_cnt: 00000000␛[0m > ␛[0m[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000␛[0m > ␛[0m[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000␛[0m > ␛[0m[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000␛[0m > ␛[0m[DEBUG] gpe0_sts[3]: 00014040 gpe0_en[3]: 00000000␛[0m > ␛[0m[DEBUG] TCO_STS: 0000 0000␛[0m > ␛[0m[DEBUG] GEN_PMCON: d9801038 00002200␛[0m > ␛[0m[DEBUG] GBLRST_CAUSE: 00000040 00000000␛[0m > ␛[0m[DEBUG] HPR_CAUSE0: 00000000␛[0m > ␛[0m[DEBUG] prev_sleep_state 0 (S0)␛[0m > ``` post global reset, we should see sleep state as S5. There were some bug reported previously where the sleep states are not working as expected. Details https://review.coreboot.org/c/coreboot/+/72053 and https://b.corp.google.com/issues/265939425#comment38 Trulo: ``` [NOTE ] coreboot-coreboot-unknown.9999.ea4a128 Sun Nov 3 05:55:26 UTC 2024 ramstage starting (log level: 8)... [DEBUG] Normal boot [DEBUG] FMAP: area RW_MRC_CACHE found @ 84d000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [INFO ] MMAP window: SPI flash base=0x3a0000, Host base=0xff3a0000, Size=0xc60000 [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [NOTE ] MRC: no data in 'RW_MRC_CACHE' [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update. [DEBUG] MRC: updated 'RW_MRC_CACHE'. [DEBUG] FMAP: area RW_ELOG found @ 85d000 (4096 bytes) [INFO ] ELOG: NV offset 0x85d000 size 0x1000 [INFO ] ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 [INFO ] ELOG: Event(17) added with size 13 at 2024-10-16 00:35:35 UTC [INFO ] ELOG: Event(AA) added with size 11 at 2024-10-16 00:35:35 UTC [INFO ] Probing TPM I2C: done! DID_VID 0x504a6666 [INFO ] Locality already claimed [DEBUG] cr50 TPM 2.0 (i2c 0:0x50 id 0x504a) [INFO ] VB2:vb2_digest_init() 63176 bytes, hash algo 2, HW acceleration enabled [INFO ] src/security/tpm/tss/tcg-2.0/tss.c:253 index 0x100d return code 0x0 [INFO ] tlcl_write: response is 0x0 [INFO ] MRC: TPM MRC hash idx 0x100d updated successfully. [DEBUG] BS: BS_PRE_DEVICE entry times (exec / console): 95 / 123 ms [INFO ] Reserved BERT region base: 0x7688e000, size: 0x10000 [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RO [DEBUG] cse_lite: Next partition = RO [DEBUG] cse_lite: Flags = 0x3 [DEBUG] cse_lite: RO version = 16.50.15.1515 (Status=0x0, Start=0x2000, End=0x144fff) [DEBUG] cse_lite: RW version = 16.50.15.1515 (Status=0x0, Start=0x1af000, End=0x39cfff) [DEBUG] rt_debug: dbg_feature_cntrl.cse_fw_update_disable=0 [DEBUG] FMAP: area SI_ME found @ 1000 (3796992 bytes) [DEBUG] cse_lite: CSE RW partition: offset = 0x1af000, size = 0x1ee000 [DEBUG] FMAP: area FW_MAIN_A found @ 3a2000 (2312128 bytes) [INFO ] CBFS: Found 'me_rw.version' @0x78e80 size 0xe in mcache @0x769dd35c [INFO ] VB2:vb2_digest_init() 14 bytes, hash algo 2, HW acceleration enabled [DEBUG] cse_lite: CSE CBFS RW version : 16.50.15.1515 [INFO ] cse_lite: Set Boot Partition Info Command (RW) [DEBUG] HECI: Global Reset(Type:1) Command ... ... [NOTE ] coreboot-coreboot-unknown.9999.ea4a128 Sun Nov 3 05:55:26 UTC 2024 romstage starting (log level: 8)... [DEBUG] pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00010000 gpe0_en[3]: 00082000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: d1801038 00002200 [DEBUG] GBLRST_CAUSE: 00000040 00000000 [DEBUG] HPR_CAUSE0: 00000000 [DEBUG] prev_sleep_state 5 [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [INFO ] TXT disabled successfully - Unlocked memory [INFO ] FW_CONFIG value from CBI is 0x20000005 [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! ``` Brox: ``` [NOTE ] coreboot-coreboot-unknown.9999.fa84db0 Tue Nov 05 14:51:43 UTC 2024 x86_32 romstage starting (log level: 8)... [DEBUG] pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00010000 gpe0_en[3]: 00080000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: d0015038 00002200 [DEBUG] GBLRST_CAUSE: 00000000 00000000 [DEBUG] HPR_CAUSE0: 00000000 [DEBUG] prev_sleep_state 5 (S5) [INFO ] OC Watchdog: disabling watchdog timer [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 [INFO ] TXT disabled successfully - Unlocked memory [INFO ] FW_CONFIG value from CBI is 0x12a [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RO [DEBUG] cse_lite: Next partition = RO [DEBUG] cse_lite: Flags = 0x3 [DEBUG] cse_lite: RO version = 16.1.35.2557 (Start=0x2000, End=0x19bfff) [DEBUG] cse_lite: RW version = 16.1.35.2557 (Start=0x205000, End=0x449fff) [DEBUG] rt_debug: dbg_feature_cntrl.cse_fw_update_disable=255 [DEBUG] FMAP: area SI_ME found @ 1000 (5238784 bytes) [DEBUG] cse_lite: CSE RW partition: offset = 0x205000, size = 0x245000 [DEBUG] FMAP: area FW_MAIN_A found @ 510000 (8323008 bytes) [INFO ] Fixed Decode Window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] Extended Decode Window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 [INFO ] CBFS: Found 'me_rw.version' @0x92d40 size 0xd in mcache @0xfef9155c [INFO ] VB2:vb2_digest_init() 13 bytes, hash algo 2, HW acceleration enabled [DEBUG] cse_lite: CSE CBFS RW version : 16.1.35.2557 [INFO ] cse_lite: Set Boot Partition Info Command (RW) [DEBUG] HECI: Global Reset(Type:1) Command ... ... [NOTE ] coreboot-coreboot-unknown.9999.fa84db0 Tue Nov 05 14:51:43 UTC 2024 x86_32 romstage starting (log level: 8)... [DEBUG] pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00010000 gpe0_en[3]: 00080000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: d1001038 00002200 [DEBUG] GBLRST_CAUSE: 00000040 00000000 [DEBUG] HPR_CAUSE0: 00000000 [DEBUG] prev_sleep_state 5 (S5) [INFO ] OC Watchdog: disabling watchdog timer [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 [INFO ] TXT disabled successfully - Unlocked memory [INFO ] FW_CONFIG value from CBI is 0x12a [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RW [DEBUG] cse_lite: Next partition = RW [DEBUG] cse_lite: Flags = 0x3 [DEBUG] cse_lite: RO version = 16.1.35.2557 (Start=0x2000, End=0x19bfff) [DEBUG] cse_lite: RW version = 16.1.35.2557 (Start=0x205000, End=0x449fff) [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Gerrit-Change-Number: 84996 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 18:21:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brox: Reduce PL4 only for battery disconnected scenario
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85002?usp=email ) Change subject: mb/google/brox: Reduce PL4 only for battery disconnected scenario ...................................................................... mb/google/brox: Reduce PL4 only for battery disconnected scenario This patch reduces PL4 only for no battery condition i.e. when battery is disconnected or not physically present. BUG=b:377305625 TEST=Build Brox and boot when the battery is disconnected Change-Id: I59a1028ce9cd3a6cf98f865d9c085a64f391f201 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/romstage.c M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c 2 files changed, 3 insertions(+), 5 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/romstage.c b/src/mainboard/google/brox/romstage.c index ced9184..19b99bb 100644 --- a/src/mainboard/google/brox/romstage.c +++ b/src/mainboard/google/brox/romstage.c @@ -21,8 +21,7 @@ size_t pads_num; /* If battery is not present - Boot with maximum non-turbo frequency */ - if (CONFIG(EC_GOOGLE_CHROMEEC) && - !google_chromeec_is_battery_present_and_above_critical_threshold()) { + if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_chromeec_is_battery_present()) { FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; mem_cfg->BootFrequency = MAX_NONTURBO_PERFORMANCE; printk(BIOS_DEBUG, "Boot Frequency is set to %u\n", mem_cfg->BootFrequency); diff --git a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c index 80c8499..f079d7a 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c @@ -53,9 +53,8 @@ if (!config->tdp_pl4) return; - /* limiting PL4 value for battery disconnected or below critical threshold */ - if (CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT && - (!google_chromeec_is_battery_present_and_above_critical_threshold())) + /* Limit PL4 when battery is disconnected */ + if (CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT && !google_chromeec_is_battery_present()) config->tdp_pl4 = CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT; else config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power, MILLIWATTS_TO_WATTS); -- To view, visit https://review.coreboot.org/c/coreboot/+/85002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59a1028ce9cd3a6cf98f865d9c085a64f391f201 Gerrit-Change-Number: 85002 Gerrit-PatchSet: 3 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller
by Martin L Roth (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Martin L Roth has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84842?usp=email ) Change subject: soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08543fc77f0f3e633b05889e921c5183e6e20d8e Gerrit-Change-Number: 84842 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 18:17:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Enable IRQ routing
by Martin L Roth (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Martin L Roth has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84328?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Enable IRQ routing ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Gerrit-Change-Number: 84328 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 18:15:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routed
by Martin L Roth (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Alicja Michalska, Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu. Martin L Roth has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82253?usp=email ) Change subject: soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routed ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c Gerrit-Change-Number: 82253 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 18:12:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Máté Kukri (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Máté Kukri, Paul Menzel. Hello Angel Pons, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82053?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) - Boots Linux 6.11 (Debian) - GRUB and SeaBIOS payloads work - SMSC SCH5553 SIO/EC + Serial port works + PWM fan control works - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/plugins/gitiles/deguard - Audio works - All USB ports work - Currently limited to the Micro form factor, but others are very similar - HDA verbs and VBT by Leah Rowe Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- A src/mainboard/dell/optiplex_3050/Kconfig A src/mainboard/dell/optiplex_3050/Kconfig.name A src/mainboard/dell/optiplex_3050/Makefile.mk A src/mainboard/dell/optiplex_3050/acpi/ec.asl A src/mainboard/dell/optiplex_3050/acpi/superio.asl A src/mainboard/dell/optiplex_3050/board_info.txt A src/mainboard/dell/optiplex_3050/bootblock.c A src/mainboard/dell/optiplex_3050/cmos.default A src/mainboard/dell/optiplex_3050/cmos.layout A src/mainboard/dell/optiplex_3050/data.vbt A src/mainboard/dell/optiplex_3050/devicetree.cb A src/mainboard/dell/optiplex_3050/dsdt.asl A src/mainboard/dell/optiplex_3050/gma-mainboard.ads A src/mainboard/dell/optiplex_3050/hda_verb.c A src/mainboard/dell/optiplex_3050/include/early_gpio.h A src/mainboard/dell/optiplex_3050/include/gpio.h A src/mainboard/dell/optiplex_3050/ramstage.c A src/mainboard/dell/optiplex_3050/romstage.c A src/mainboard/dell/optiplex_3050/sch5555_ec.c A src/mainboard/dell/optiplex_3050/sch5555_ec.h 20 files changed, 1,317 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 18 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email ) Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/84996/comment/c240330e_7155d01e?us… : PS1, Line 200: if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) { When you come out of global_reset, is the previous state S5? If not, then we will never end up disabling UFS. Atleast on my testing, the previous sleep state is not showing as S5. ``` ␛[0m[INFO ] cse_lite: Set Boot Partition Info Command (RW)␛[0m ␛[0m[DEBUG] HECI: Global Reset(Type:1) Command␛[0m ␀␛[0m ␛[0m ␛[1m[NOTE ] coreboot-v1.9308_26_0.0.22-38623-g629ff30d2834 Sat Oct 19 18:42:55 UTC 2024 x86_32 romstage starting (log level: 8)...␛[0m ␛[0m[DEBUG] pm1_sts: 8000 pm1_en: 0000 pm1_cnt: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[3]: 00014040 gpe0_en[3]: 00000000␛[0m ␛[0m[DEBUG] TCO_STS: 0000 0000␛[0m ␛[0m[DEBUG] GEN_PMCON: d9801038 00002200␛[0m ␛[0m[DEBUG] GBLRST_CAUSE: 00000040 00000000␛[0m ␛[0m[DEBUG] HPR_CAUSE0: 00000000␛[0m ␛[0m[DEBUG] prev_sleep_state 0 (S0)␛[0m ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Gerrit-Change-Number: 84996 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 17:54:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cmn/block/cse: Add API to check the current boot partition
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Eric Lai, Kapil Porwal, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84995?usp=email ) Change subject: soc/intel/cmn/block/cse: Add API to check the current boot partition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84995?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a63ae9992d83b439a0f995d599ee475f7abd75b Gerrit-Change-Number: 84995 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 17:30:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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