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Change subject: soc/intel/common/gpio: add function to lock GPIO configuration
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/84901/comment/c6f1cbc8_7b9be86e?us… :
PS3, Line 485: /* Clear lock for the exception PADs */
> I think it's implementation way difference.
> We can lock each pin mux table by using existing _LOCK macro but it may be work if we want to lock some of pin's configuration.
> Basic assumption for this change(having exception table for lock) is for locking most of pin configuration for system safety. And it'll require less change compared to changing entire pin configuration in gpio.c.
unless you populate a mainboard table the one you called as exception table, I'm unable to understand how this is not any more duplication between using LOCK macro in gpio.c vs adding one more table in mainboard for locking the PAD configuration.
Eventually both should do the same. Also, please don't take the ability for changing the PAD configuration if not required to lock, we are using feature like FW shell or UEFI shell to alter the GPIO configuration to debug some critical issue w/o need to flash the entire AP FW> Therefore, I don't see a need to lock every GPIOs, rather we should only lock the required GPIOs like wake capable and IRQ ones (rests are harmless).
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84949?usp=email )
Change subject: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE
......................................................................
mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP
headers for FSP as banshee is using a converged firmware image.
This effort also helps to save banshee boot time by 80-100ms as
RPL FSP is better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which
saves 10ms of the boot time.
BUG=b:358254132
TEST=Able to build and boot google/banshee.
cold boot time w/o this CL
```
Total Time: 1,399,888
```
cold boot time w/ this CL
```
Total Time: 1,295,334
```
Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84949
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---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
Dtrain Hsu: Looks good to me, approved
Subrata Banik: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 2981ea7..20207f4 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -169,6 +169,7 @@
select DRIVERS_GENERIC_GPIO_KEYS
select INTEL_GMA_HAVE_VBT
select MEMORY_SODIMM
+ select SOC_INTEL_RAPTORLAKE
config BOARD_GOOGLE_BRASK
select BOARD_GOOGLE_BASEBOARD_BRASK
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Change subject: mb/google/brox: Hint romstage init about upcoming reset
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
......................................................................
Patch Set 10: Code-Review+1
(1 comment)
Patchset:
PS8:
> I have edited the commit message right on gerrit (so there's no new code being pushed). […]
Awesome. Thank you.
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Change subject: soc/intel/jasperlake: add support for RP LTR mechanism
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84866/comment/f6b4e8d5_4681e85a?us… :
PS3, Line 13: Tested on Awasuki with RTL8852BE
> You can check root port configuration space dump, LTR Mechanism Enable bit is offset 68h[10].
Please add these details, and the command how to dump the root port configuration space.
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Change subject: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
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Patch Set 1: Code-Review+1
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