coreboot-gerrit November 2024

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2521 discussions

[S] Change in coreboot[main]: drivers/spi/spi_flash: introduce 'spi_flash_cmd_multi'
by Matt DeVillier (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Ana Carolina Cabral, Felix Held. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84789?usp=email ) Change subject: drivers/spi/spi_flash: introduce 'spi_flash_cmd_multi' ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e Gerrit-Change-Number: 84789 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Nov 2024 17:07:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/common/psp/rpmc: bring debug output in line with fmap section
by Matt DeVillier (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/85007?usp=email ) Change subject: soc/amd/common/psp/rpmc: bring debug output in line with fmap section ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie89dfcfe4b8780f422c222477bb627e03bd3662d Gerrit-Change-Number: 85007 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Nov 2024 17:06:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/84724?usp=email ) Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Gerrit-Change-Number: 84724 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 17:03:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: vc/intel/fsp/raptorlake: Add FspProducerDataHeader.h header
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84723?usp=email ) Change subject: vc/intel/fsp/raptorlake: Add FspProducerDataHeader.h header ...................................................................... vc/intel/fsp/raptorlake: Add FspProducerDataHeader.h header This patch is to add FspProducerDataHeader.h header file to support MRC version Info in RPL. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: Iaf7983fbe8f103d9f51065cd160177e2bde7fd3d Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84723 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- A src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspProducerDataHeader.h 1 file changed, 80 insertions(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspProducerDataHeader.h new file mode 100644 index 0000000..b7cd634 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspProducerDataHeader.h @@ -0,0 +1,80 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include <Guid/FspHeaderFile.h> + +#define BUILD_TIME_STAMP_SIZE 12 + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H -- To view, visit https://review.coreboot.org/c/coreboot/+/84723?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7983fbe8f103d9f51065cd160177e2bde7fd3d Gerrit-Change-Number: 84723 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: select UDK_202305_BINDING for RPL
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84722?usp=email ) Change subject: soc/intel/alderlake: select UDK_202305_BINDING for RPL ...................................................................... soc/intel/alderlake: select UDK_202305_BINDING for RPL RPL FSP v5311 uses 202305 Edk2. Select UDK_202305_BINDING Kconfig for RPL SoC. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: I8dcc7d85cddadcce148ded5a81658253e8598413 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84722 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 6ed43bf..14137a3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -92,8 +92,9 @@ select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC + select UDK_202305_BINDING if SOC_INTEL_RAPTORLAKE select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N - select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N + select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N && !SOC_INTEL_RAPTORLAKE select VBOOT_LIB select X86_CLFLUSH_CAR help -- To view, visit https://review.coreboot.org/c/coreboot/+/84722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8dcc7d85cddadcce148ded5a81658253e8598413 Gerrit-Change-Number: 84722 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: vendorcode/intel: Add edk2-stable202305 support
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84817?usp=email ) Change subject: vendorcode/intel: Add edk2-stable202305 support ...................................................................... vendorcode/intel: Add edk2-stable202305 support Add edk2-stable202305 support for MTL and RPL FSPs. This patch includes (edk2/edk2-stable202302) all required headers for edk2-stable202302 EDK2 tag from EDK2 github project using below command: git clone -b edk2-stable202305 https://github.com/tianocore/edk2.git commit hash: ba91d0292e593df8528b66f99c1b0b14fadc8e16 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Add following fixes from older Edk2 060492ecd2 Safe guard enum macro in SmBios.h 2bf9599cf1 Use fixed size struct elements cf4c6fd225 Remove FSPM_ARCH_UPD config guard dc781d3a83 Define FSP_SIG macro for FSP 2.x compatibility d045074b91 Remove wchar_t asserts Change-Id: I96f0d0e393d31b325f9e42e3494556a2f6e1228e Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84817 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.mk A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/FspEas.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/FspEas/FspApi.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/FspGlobalData.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/FspMeasurePointId.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/FspStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/CacheLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/FspCommonLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/FspPlatformLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h A src/vendorcode/intel/edk2/edk2-stable202305/IntelFsp2Pkg/Include/Ppi/Variable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/AArch64/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Arm/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Base.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/ConfidentialComputingGuestAttr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ebc/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/Acpi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/Apriori.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/AprioriFileName.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/Btt.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/CapsuleReport.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/Cper.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/DebugImageInfoTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/DxeServices.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/EventGroup.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/EventLegacyBios.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/FileInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/FileSystemInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/FirmwareContentsSigned.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/FirmwareFileSystem2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/FirmwareFileSystem3.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/FmpCapsule.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/GlobalVariable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/Gpt.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/GraphicsInfoHob.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/HardwareErrorVariable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/HiiFormMapMethodGuid.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/HiiKeyBoardLayout.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/HiiPlatformSetupFormset.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/HobList.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/ImageAuthentication.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/JsonCapsule.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/LinuxEfiInitrdMedia.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/MdePkgTokenSpace.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/MemoryAllocationHob.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/MemoryAttributesTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/MemoryOverwriteControl.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/Mps.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/PcAnsi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/RtPropertiesTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/SmBios.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/SmramMemoryReserve.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/StatusCodeDataTypeId.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/SystemResourceTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/VectorHandoffTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Guid/WinCertificate.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ia32/Nasm.inc A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ia32/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi10.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi20.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi30.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi40.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi50.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi51.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi60.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi61.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi62.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi63.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi64.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Acpi65.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/AcpiAml.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/ArmPerformanceMonitoringUnitTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Atapi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Bluetooth.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Bmp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Cxl.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Cxl11.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/DebugPort2Table.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/DebugPortTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Dhcp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/ElTorito.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Emmc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Hsti.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Http11.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IoRemappingTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Ipmi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiKcs.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/IpmiSsif.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Mbr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Mctp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Nvme.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Pci.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Pci22.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Pci23.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Pci30.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PciCodeId.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PciExpress21.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PciExpress30.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PciExpress31.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PciExpress40.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PciExpress50.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PeImage.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Pldm.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/PldmSmbiosTransfer.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Scsi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Sd.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/SdramSpd.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/SmBios.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/SmBus.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Spdm.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/TcgStorageCore.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/TcgStorageOpal.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/TcpaAcpi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Tdx.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Tls1.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Tpm12.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Tpm20.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Tpm2Acpi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/TpmPtp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/TpmTis.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Udf.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/Usb.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/WatchdogActionTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/ArmTrngLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/BaseLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/BaseMemoryLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/BaseRiscVSbiLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/CacheMaintenanceLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/CcProbeLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/CpuLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/DebugLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/DebugPrintErrorLevelLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/DevicePathLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/DxeCoreEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/DxeServicesLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/DxeServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/ExtractGuidedSectionLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/FdtLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/FileHandleLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/HobLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/HstiLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/IoLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/JedecJep106Lib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/MemoryAllocationLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/MipiSysTLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/MmServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/MmUnblockMemoryLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/OrderedCollectionLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PcdLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PciCf8Lib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PciExpressLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PciLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PciSegmentInfoLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PciSegmentLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PeCoffExtraActionLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PeCoffGetEntryPointLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PeCoffLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PeiCoreEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PeiServicesLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PeiServicesTablePointerLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PeimEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PerformanceLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PostCodeLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/PrintLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/RegisterFilterLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/ReportStatusCodeLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/ResourcePublicationLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/RngLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/S3BootScriptLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/S3IoLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/S3PciLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/S3PciSegmentLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/S3SmbusLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/S3StallLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SafeIntLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SerialPortLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmbusLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmiHandlerProfileLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmmCpuRendezvousLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmmIoLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmmLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmmMemLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmmPeriodicSmiLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SmmServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/SynchronizationLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/TdxLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/TimerLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/TraceHubDebugSysTLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiApplicationEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiBootServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiDecompressLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiDriverEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiRuntimeLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiScsiLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UefiUsbLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Library/UnitTestLib.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/LoongArch64/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiBootMode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiDependency.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiDxeCis.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiFirmwareFile.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiFirmwareVolume.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiHob.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiI2c.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiMmCis.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiMultiPhase.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiPeiCis.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiS3BootScript.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiSmmCis.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Pi/PiStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/PiDxe.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/PiMm.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/PiPei.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/PiSmm.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/BlockIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/BlockIo2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/BootInRecoveryMode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Capsule.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/CpuIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Decompress.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/DelayedDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/DeviceRecoveryModule.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/DxeIpl.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/EndOfPeiPhase.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/FirmwareVolume.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/FirmwareVolumeInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Graphics.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/GuidedSectionExtraction.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/I2cMaster.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/IsaHc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/LoadFile.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/LoadImage.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/MasterBootMode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/MemoryDiscovered.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/MmAccess.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/MmCommunication.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/MmConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/MmControl.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/MpServices.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Pcd.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/PcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/PciCfg2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/PeiCoreFvLocation.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/PiPcd.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/PiPcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/ReadOnlyVariable2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/RecoveryModule.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/ReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Reset.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Reset2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/S3Resume2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/SecHobData.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/SecPlatformInformation.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/SecPlatformInformation2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Security2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Smbus2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/Stall.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/StatusCode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/SuperIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/TemporaryRamDone.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/TemporaryRamSupport.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Ppi/VectorHandoffInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/AbsolutePointer.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/AcpiTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/AdapterInformation.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Arp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/AtaPassThru.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/AuthenticationInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Bds.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Bis.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BlockIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BlockIo2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BlockIoCrypto.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BluetoothAttribute.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BluetoothConfig.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BluetoothHc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BluetoothIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BluetoothLeConfig.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BootManagerPolicy.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/BusSpecificDriverOverride.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Capsule.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/CcMeasurement.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ComponentName.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ComponentName2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Cpu.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/CpuIo2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DebugPort.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DebugSupport.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Decompress.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DeferredImageLoad.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DeviceIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DevicePath.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DevicePathFromText.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DevicePathToText.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DevicePathUtilities.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Dhcp4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Dhcp6.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DiskInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DiskIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DiskIo2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Dns4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Dns6.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverBinding.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverConfiguration2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverDiagnostics.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverDiagnostics2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverFamilyOverride.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverHealth.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DxeMmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/DxeSmmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Eap.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/EapConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/EapManagement.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/EapManagement2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Ebc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/EdidActive.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/EdidDiscovered.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/EdidOverride.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/EraseBlock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/FirmwareManagement.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/FirmwareVolume2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/FirmwareVolumeBlock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/FormBrowser2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Ftp4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/GraphicsOutput.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/GuidedSectionExtraction.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Hash.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Hash2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiConfigAccess.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiConfigKeyword.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiConfigRouting.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiDatabase.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiFont.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiImage.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiImageDecoder.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiImageEx.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiPackageList.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiPopup.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HiiString.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Http.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HttpBootCallback.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/HttpUtilities.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/I2cEnumerate.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/I2cHost.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/I2cIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/I2cMaster.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/IScsiInitiatorName.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/IdeControllerInit.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Ip4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Ip4Config.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Ip4Config2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Ip6.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Ip6Config.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/IpSec.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/IpSecConfig.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/IsaHc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Kms.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LegacyRegion2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LegacySpiController.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LegacySpiFlash.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LegacySpiSmmController.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LegacySpiSmmFlash.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LoadFile.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LoadFile2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/LoadedImage.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ManagedNetwork.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MemoryAccept.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MemoryAttribute.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Metronome.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmAccess.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmBase.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmCommunication.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmCommunication2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmControl.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmCpu.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmCpuIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmEndOfDxe.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmGpiDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmIoTrapDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmMp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmPciRootBridgeIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmPowerButtonDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmSwDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmSxDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MmUsbDispatch.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MonotonicCounter.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/MpService.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Mtftp4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Mtftp6.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/NvdimmLabel.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/NvmExpressPassthru.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PartitionInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Pcd.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciEnumerationComplete.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciHotPlugInit.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciHotPlugRequest.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciOverride.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciPlatform.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PciRootBridgeIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PiPcd.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PiPcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Pkcs7Verify.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PlatformDriverOverride.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PxeBaseCode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/RamDisk.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/RealTimeClock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/RedfishDiscover.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/RegularExpressionProtocol.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Reset.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ResetNotification.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Rest.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/RestEx.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/RestJsonStructure.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Rng.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Runtime.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/S3SaveState.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/S3SmmSaveState.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ScsiIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ScsiPassThru.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ScsiPassThruExt.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SdMmcPassThru.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Security.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Security2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SecurityPolicy.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SerialIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ServiceBinding.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Shell.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ShellDynamicCommand.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/ShellParameters.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SimpleFileSystem.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SimpleNetwork.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SimplePointer.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SimpleTextIn.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SimpleTextInEx.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SimpleTextOut.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmartCardEdge.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmartCardReader.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Smbios.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmbusHc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmAccess2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmBase2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmCommunication.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmControl2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmCpu.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmCpuIo2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmEndOfDxe.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmGpiDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmSwDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmSxDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SmmUsbDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SpiConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SpiHc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SpiIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SpiNorFlash.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SpiSmmConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SpiSmmHc.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SpiSmmNorFlash.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/StatusCode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/StorageSecurityCommand.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SuperIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/SuperIoControl.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Supplicant.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/TapeIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Tcg2Protocol.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/TcgService.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Tcp4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Tcp6.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Timer.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Timestamp.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Tls.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/TlsConfig.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/TrEEProtocol.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Udp4.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Udp6.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UfsDeviceConfig.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UgaDraw.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UgaIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UnicodeCollation.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Usb2HostController.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UsbFunctionIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UsbHostController.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UsbIo.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UserCredential.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UserCredential2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/UserManager.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/Variable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/VariableWrite.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/VlanConfig.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/WatchdogTimer.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/WiFi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Protocol/WiFi2.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Amd/Cpuid.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Amd/Fam17Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Amd/Ghcb.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Amd/Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/ArchitecturalMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Cpuid.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/LocalApic.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Microcode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/AtomMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/Core2Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/CoreMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/P6Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/SmramSaveStateMap.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/StmApi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/StmResourceDescriptor.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/Intel/StmStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/RiscV64/RiscVEncoding.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Register/RiscV64/RiscVImpl.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/RiscV64/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi/UefiAcpiDataTable.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi/UefiBaseType.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi/UefiGpt.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi/UefiMultiPhase.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi/UefiPxe.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/Uefi/UefiSpec.h A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/X64/Nasm.inc A src/vendorcode/intel/edk2/edk2-stable202305/MdePkg/Include/X64/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/AcpiCpuData.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/CpuHotPlugData.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Guid/MsegSmram.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Guid/SmmBaseHob.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/CcExitLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/CpuPageTableLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/LocalApicLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/MicrocodeLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/MpInitLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/MtrrLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/PlatformSecLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Ppi/MpServices2.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Protocol/SmMonitorInit.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Protocol/SmmCpuService.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Register/ArchitecturalMsr.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Register/Cpuid.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Register/LocalApic.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Register/Microcode.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Register/Msr.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Register/SmramSaveStateMap.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/Register/StmApi.h A src/vendorcode/intel/edk2/edk2-stable202305/UefiCpuPkg/Include/StuffRsbNasm.inc M src/vendorcode/intel/fsp/fsp2_0/IntelFspPkg/Include/FspInfoHeader.h 642 files changed, 247,172 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved -- To view, visit https://review.coreboot.org/c/coreboot/+/84817?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I96f0d0e393d31b325f9e42e3494556a2f6e1228e Gerrit-Change-Number: 84817 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email ) Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 ...................................................................... mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:366383364 TEST=Tested on Awasuki with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Signed-off-by: Hualin Wei <weihualin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/awasuki/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Weimin Wu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index cc7eba83..e0abe19 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" -- To view, visit https://review.coreboot.org/c/coreboot/+/84951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Gerrit-Change-Number: 84951 Gerrit-PatchSet: 5 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email ) Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ...................................................................... soc/intel/jasperlake: add support for RP LTR mechanism Reserve Root Port LTR mechanism in FSP, in case some devices need to optimize LTR. BUG=366383364 TEST=Tested on Awasuki with RTL8852BE use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable bit is offset 68h[10]. 00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01) 00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20 20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08 50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00 60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00 90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00 a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00 e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00 f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84 Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Signed-off-by: Lawrence Chang <lawrence.chang(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84866 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: David Ruth <druth(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Subrata Banik: Looks good to me, approved David Ruth: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 53bf34f..00fac3c 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -152,6 +152,9 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR: Enable (1) / Disable (0) */ + uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 85664ce..3bad533 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -190,6 +190,10 @@ /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* PCIe Root Ports LTR mechanism */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; + /* Configure FIVR RFI related settings */ params->FivrRfiFrequency = config->FivrRfiFrequency; params->FivrSpreadSpectrum = config->FivrSpreadSpectrum; -- To view, visit https://review.coreboot.org/c/coreboot/+/84866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Gerrit-Change-Number: 84866 Gerrit-PatchSet: 5 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: David Ruth <druth(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Update ext_vr for board version > 0xb
by Karthik Ramasubramanian (Code Review) 06 Nov '24

06 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84953?usp=email ) Change subject: mb/google/dedede/var/drawcia: Update ext_vr for board version > 0xb ...................................................................... mb/google/dedede/var/drawcia: Update ext_vr for board version > 0xb ext_vr_update should be run after board version 0xb, but skipped by return. Drawper LTE board version was set after 0x9, but there are more board added after that. Specific Drawper board version as 0xa, 0xb and 0xf. BUG=b:376828839 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage and test on DUTs. Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84953 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/ramstage.c 1 file changed, 13 insertions(+), 7 deletions(-) Approvals: Derek Huang: Looks good to me, approved build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c index 06ff4b5..f44a170 100644 --- a/src/mainboard/google/dedede/variants/drawcia/ramstage.c +++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c @@ -15,21 +15,27 @@ cfg->disable_external_bypass_vr = 1; } -void variant_devtree_update(void) +static void update_lte_device_drawcia(void) { - uint32_t board_version = board_id(); struct device *lte_usb2 = DEV_PTR(lte_usb2); struct drivers_usb_acpi_config *config; struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0); - /* board version 9 is drawper EVT */ - if (board_version > 9) - return; - if (lte_usb2 == NULL) return; config = config_of(lte_usb2); config->reset_gpio = lte_reset_gpio; - ext_vr_update(); +} + +void variant_devtree_update(void) +{ + uint32_t board_version = board_id(); + + /* Remove power IC after board version 0xb for Draw* and Oscino units */ + if (board_version > 0xb) + ext_vr_update(); + /* Board version 0xa, 0xb and 0xf are for Drawper units */ + if (board_version != 0xa && board_version != 0xb && board_version != 0xf) + update_lte_device_drawcia(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Gerrit-Change-Number: 84953 Gerrit-PatchSet: 18 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: drivers/wifi: Support Drive Strength BRI Rsp Table
by Jérémy Compostella (Code Review) 06 Nov '24

06 Nov '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85017?usp=email ) Change subject: drivers/wifi: Support Drive Strength BRI Rsp Table ...................................................................... drivers/wifi: Support Drive Strength BRI Rsp Table Drive Strength BRI Rsp Object provides information from the OEM platforms if they have replaced the Bluetooth Radio Interface resistor to overcome the potential STEP errors on their designs. Based on configuration, CNV firmware shall adjust the BRI Rsp line drive strength. The bri_resistor_value is encoded as follow: | Bit | Val | Description | Default | |------+-----+---------------------------------------------+---------| | 0 | 0 | Device FW default values | 1 | | | 1 | Override device FW default values | | | 3:1 | 0 | Reserved (shall be set to 0) | 0 | | 7:4 | 0 | DSBR override values (only if bit 0 is set) | 0xf | | 31:7 | 0 | Reserved (shall be set to 0) | 0 | Possible values: - 0xf1 (default): indicates that the resistor on board is 33 Ohm - 0x0 or 0xb1: indicates that the resistor on board is 10 Ohm The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=DSBR methods are added to the wifi device and bluetooth companion device and they return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e300 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 53 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/85017/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index ca80594..00de176 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -962,6 +962,40 @@ acpigen_write_package_end(); } +static void sar_emit_dsbr(const struct dsbr_profile *dsbr, uint32_t domain) +{ + if (dsbr == NULL) + return; + + /* + * Name ("DSBR", Package() { + * { + * Revision, + * Package() + * { + * DomainType, // 0x7:WiFi + * BRI Resistor Value // in Ohm + * } + } }) + */ + if (dsbr->revision != DSBR_REVISION) { + printk(BIOS_ERR, "Unsupported DSBR table revision: %d\n", + dsbr->revision); + return; + } + + acpigen_write_name("DSBR"); + acpigen_write_package(2); + acpigen_write_dword(dsbr->revision); + + acpigen_write_package(2); + acpigen_write_dword(domain); + acpigen_write_dword(dsbr->bri_resistor_value); + + acpigen_write_package_end(); + acpigen_write_package_end(); +} + static void emit_wifi_sar_acpi_structures(const struct device *dev, union wifi_sar_limits *sar_limits) { @@ -979,6 +1013,7 @@ sar_emit_wtas(sar_limits->wtas); sar_emit_wbem(sar_limits->wbem); sar_emit_wpfc(sar_limits->wpfc); + sar_emit_dsbr(sar_limits->dsbr, DOMAIN_TYPE_WIFI); } static void wifi_ssdt_write_device(const struct device *dev, const char *path) @@ -1102,6 +1137,7 @@ sar_emit_bucs(sar_limits.bucs); sar_emit_bdmm(sar_limits.bdmm); sar_emit_ebrd(sar_limits.ebrd); + sar_emit_dsbr(sar_limits.dsbr, DOMAIN_TYPE_BLUETOOTH); acpigen_write_scope_end(); } else { printk(BIOS_ERR, "Failed to get %s Bluetooth companion ACPI path\n", diff --git a/src/include/sar.h b/src/include/sar.h index fc8954f..b2b4647 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -9,7 +9,7 @@ #define MAX_DENYLIST_ENTRY 16 #define MAX_DSAR_SET_COUNT 3 #define MAX_GEO_OFFSET_REVISION 3 -#define MAX_PROFILE_COUNT 15 +#define MAX_PROFILE_COUNT 16 #define MAX_SAR_REVISION 2 #define BSAR_REVISION 1 #define WBEM_REVISION 0 @@ -21,6 +21,7 @@ #define BDMM_REVISION 1 #define EBRD_REVISION 1 #define WPFC_REVISION 0 +#define DSBR_REVISION 0 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 #define SAR_REV0_SUBBANDS_COUNT 5 @@ -155,6 +156,11 @@ uint8_t filter_cfg_chain_d; } __packed; +struct dsbr_profile { + uint8_t revision; + uint32_t bri_resistor_value; +} __packed; + struct sar_header { char marker[SAR_STR_PREFIX_SIZE]; uint8_t version; @@ -179,6 +185,7 @@ struct bdmm_profile *bdmm; struct ebrd_profile *ebrd; struct wpfc_profile *wpfc; + struct dsbr_profile *dsbr; }; void *profile[MAX_PROFILE_COUNT]; }; diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 91c21ca..7437c3c 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -174,6 +174,14 @@ return sizeof(struct wpfc_profile); } +static int dsbr_table_size(const struct dsbr_profile *dsbr) +{ + if (dsbr == NULL) + return 0; + + return sizeof(struct dsbr_profile); +} + static bool valid_legacy_length(size_t bin_len) { if (bin_len == LEGACY_SAR_WGDS_BIN_SIZE) @@ -235,6 +243,7 @@ expected_sar_bin_size += bdmm_table_size(sar_limits->bdmm); expected_sar_bin_size += ebrd_table_size(sar_limits->ebrd); expected_sar_bin_size += wpfc_table_size(sar_limits->wpfc); + expected_sar_bin_size += dsbr_table_size(sar_limits->dsbr); if (sar_bin_size != expected_sar_bin_size) { printk(BIOS_ERR, "Invalid SAR size, expected: %zu, obtained: %zu\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/85017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e300 Gerrit-Change-Number: 85017 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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coreboot-gerrit November 2024