coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: util/ifdtool: Fix invalid pointer dereference
by Yu-Ping Wu (Code Review) 06 Nov '24

06 Nov '24

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85016?usp=email ) Change subject: util/ifdtool: Fix invalid pointer dereference ...................................................................... util/ifdtool: Fix invalid pointer dereference When calculating the GPR0 protection range, currently the offsets of "CSE data partition offset" and FPT are not checked. Invalid pointer dereference may lead to segmentation fault. Ensure the offset is within the image size before accessing the pointer. Change-Id: Ic9557d8fc8ae9e4c12114ee170bfc90d5e149df9 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M util/ifdtool/ifdtool.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85016/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 36477ee..ce3e85e 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1756,9 +1756,22 @@ fprintf(stderr, "Unsupported platform\n"); exit(EXIT_FAILURE); } - uint32_t data_part_offset = *((uint32_t *)(image + cse_region_start + cse_data_offset)); + const uint32_t *data_part_offset_ptr = (uint32_t *)(image + cse_region_start + cse_data_offset); + if (!PTR_IN_RANGE(data_part_offset_ptr, image, size)) { + fprintf(stderr, "Data part offset %d exceeds image size %d\n", + cse_region_start + cse_data_offset, size); + return -1; + } + uint32_t data_part_offset = *data_part_offset_ptr; + /* Start reading the CSE Data Partition Table, also known as FPT */ uint32_t data_part_start = data_part_offset + cse_region_start; + struct cse_fpt *fpt = (struct cse_fpt *)(image + data_part_start); + if (!PTR_IN_RANGE(fpt, image, size)) { + fprintf(stderr, "FPT offset %d exceeds image size %d\n", + data_part_start, size); + return -1; + } uint32_t fitc_region_start = 0; size_t fitc_region_size = 0; @@ -1766,8 +1779,7 @@ * FPT holds entry for own FPT data structure also bunch of sub-partitions. * `FITC` is one of such sub-partition entry. */ - if (parse_fitc_table(((struct cse_fpt *)(image + data_part_start)), - &fitc_region_start, &fitc_region_size) < 0) { + if (parse_fitc_table(fpt, &fitc_region_start, &fitc_region_size) < 0) { fprintf(stderr, "Unable to find FITC entry\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9557d8fc8ae9e4c12114ee170bfc90d5e149df9 Gerrit-Change-Number: 85016 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Add initial LTE related settings
by Eric Lai (Code Review) 06 Nov '24

06 Nov '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84925?usp=email ) Change subject: mb/google/nissa/var/glassway: Add initial LTE related settings ...................................................................... mb/google/nissa/var/glassway: Add initial LTE related settings 1. Add DB_1C_LTE 4 on DB_USB fw_config. 2. Implement WWAN power sequencing. 3. Disable LTE-related GPIOs based on fw_config. 4. Add I2C SX9324 (P-sensor) support. Refer Schematic file: CA31AC_R10_MB_SUB_240903A_P.pdf BUG=b:374666995 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Confirm the device node i2c-STH9324:00 created correctly, and command for # i2cdump -f -y 11 0x28 is workable. Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84925 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/glassway/fw_config.c M src/mainboard/google/brya/variants/glassway/include/variant/gpio.h M src/mainboard/google/brya/variants/glassway/overridetree.cb 4 files changed, 117 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 20207f4..fadb977 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -278,7 +278,10 @@ select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_GOTHRAX diff --git a/src/mainboard/google/brya/variants/glassway/fw_config.c b/src/mainboard/google/brya/variants/glassway/fw_config.c index b4dfc50..3cca3fe 100644 --- a/src/mainboard/google/brya/variants/glassway/fw_config.c +++ b/src/mainboard/google/brya/variants/glassway/fw_config.c @@ -5,6 +5,19 @@ #include <console/console.h> #include <fw_config.h> +static const struct pad_config lte_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + static const struct pad_config stylus_disable_pads[] = { /* F13 : SOC_PEN_DETECT_R_ODL */ PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), @@ -14,6 +27,12 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on Glassway serial projects.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, + ARRAY_SIZE(lte_disable_pads)); + } + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); gpio_padbased_override(padbased_table, stylus_disable_pads, diff --git a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 85c08db..b8751c7 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -8,10 +8,11 @@ option AUDIO_ALC5650_ALC5650 1 end field DB_USB 5 7 - option DB_NONE 0 - option DB_1C 1 - option DB_1A 2 - option DB_1C_1A 3 + option DB_NONE 0 + option DB_1C 1 + option DB_1A 2 + option DB_1C_1A 3 + option DB_1C_LTE 4 end field SD_CARD 8 option SD_ABSENT 0 @@ -426,6 +427,78 @@ end end end #I2C1 + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x46" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x46" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0xc0" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x20" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_msk" = "0x60" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "512" + register "ph23_resolution" = "512" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "3" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""gnd"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on + probe DB_USB DB_1C_LTE + end + end + end #I2C2 device ref i2c3 on chip drivers/i2c/generic register "hid" = ""RTL5682"" @@ -598,6 +671,13 @@ end end chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port6 on end @@ -632,6 +712,13 @@ probe DB_USB DB_1C_1A end end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe DB_USB DB_1C_LTE + end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/84925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Gerrit-Change-Number: 84925 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Add Fn key scancode
by Eric Lai (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Eric Lai has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85014?usp=email ) Change subject: mb/google/nissa/var/rull: Add Fn key scancode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Gerrit-Change-Number: 85014 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 07:49:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Change padbased_override to rtd3 of wifi
by Jayvik Desai (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Jayvik Desai has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85000?usp=email ) Change subject: mb/google/nissa/var/rull: Change padbased_override to rtd3 of wifi ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia95dc9f6b707db63840de9b15b38bdaea48ea192 Gerrit-Change-Number: 85000 Gerrit-PatchSet: 12 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 07:31:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXART
by Jayvik Desai (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Kyle Lin, Nick Vaccaro, Rui Zhou. Jayvik Desai has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/84999?usp=email ) Change subject: mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXART ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacf09cd46d4a97fb79f91043c84452f76689462f Gerrit-Change-Number: 84999 Gerrit-PatchSet: 8 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 07:01:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen
by Rui Zhou (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85015?usp=email to look at the new patch set (#2). Change subject: UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. BUG=b:374629673 BRANCH=None TEST=Local build successfully and touchpanel function is normal Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85015/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen
by Rui Zhou (Code Review) 06 Nov '24

06 Nov '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85015?usp=email ) Change subject: UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen ...................................................................... UPSTREAM: mb/google/nissa/var/rull: Add Elan touchscreen Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. BUG=b:374629673 BRANCH=None TEST=Local build successfully and touchpanel function is normal Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85015/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index b59a0de..963ebbc 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -219,7 +219,25 @@ device generic 0 on end end end - device ref i2c1 off end # Touchscreen + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end device ref i2c3 on chip drivers/i2c/rt5645 register "hid" = ""10EC5650"" -- To view, visit https://review.coreboot.org/c/coreboot/+/85015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Gerrit-Change-Number: 85015 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Robert Chen (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Eric Lai, Karthik Ramasubramanian. Robert Chen has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email ) Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 06:45:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Add initial LTE related settings
by Daniel Peng (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Anson Tseng, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Ricky Chang. Daniel Peng has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/84925?usp=email ) Change subject: mb/google/nissa/var/glassway: Add initial LTE related settings ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Thanks for the CR+2. If ready, could the reviewer help to submit the CL? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/84925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Gerrit-Change-Number: 84925 Gerrit-PatchSet: 5 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 06:06:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update power limits config
by Subrata Banik (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Jamie Ryu, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/85006?usp=email ) Change subject: soc/intel/pantherlake: Update power limits config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Gerrit-Change-Number: 85006 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 05:43:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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