coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2177 discussions

[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Jarried Lin (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Runyang Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84896?usp=email to look at the new patch set (#5). Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... soc/mediatek/mt8196: Disable irq2axi feature Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled by checking /proc/interrupts. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 --- M src/mainboard/google/rauru/romstage.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/irq2axi.h A src/soc/mediatek/mt8196/irq2axi.c 4 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84896/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Jarried Lin (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Runyang Chen, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Runyang Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84896?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Yidi Lin, Code-Review+1 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... soc/mediatek/mt8196: Disable irq2axi feature Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 --- M src/mainboard/google/rauru/romstage.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/irq2axi.h A src/soc/mediatek/mt8196/irq2axi.c 4 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84896/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Enable lastbus debug hardware
by Yu-Ping Wu (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84928?usp=email ) Change subject: soc/mediatek/mt8196: Enable lastbus debug hardware ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c Gerrit-Change-Number: 84928 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 02:30:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE
by Ian Feng (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Ian Feng has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/84949?usp=email ) Change subject: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84949/comment/db498c4d_beb74a78?us… : PS1, Line 11: > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/84949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287 Gerrit-Change-Number: 84949 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Nov 2024 01:50:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE
by Ian Feng (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84949?usp=email to look at the new patch set (#2). Change subject: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE ...................................................................... mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as banshee is using a converged firmware image. This effort also helps to save banshee boot time by 80-100ms as RPL FSP is better optimized. Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which saves 10ms of the boot time. BUG=b:358254132 TEST=Able to build and boot google/banshee. cold boot time w/o this CL ``` Total Time: 1,399,888 ``` cold boot time w/ this CL ``` Total Time: 1,295,334 ``` Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84949/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287 Gerrit-Change-Number: 84949 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE
by Ian Feng (Code Review) 01 Nov '24

01 Nov '24

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84949?usp=email ) Change subject: mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE ...................................................................... mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKE Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as banshee is using a converged firmware image. This effort also helps to save banshee boot time by 80-100ms as RPL FSP is better optimized. Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which saves 10ms of the boot time. BUG=b:358254132 TEST=Able to build and boot google/banshee. cold boot time w/o this CL ``` Total Time: 1,399,888 ``` cold boot time w/ this CL ``` Total Time: 1,295,334 ``` Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84949/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2981ea7..20207f4 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -169,6 +169,7 @@ select DRIVERS_GENERIC_GPIO_KEYS select INTEL_GMA_HAVE_VBT select MEMORY_SODIMM + select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_BRASK select BOARD_GOOGLE_BASEBOARD_BRASK -- To view, visit https://review.coreboot.org/c/coreboot/+/84949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287 Gerrit-Change-Number: 84949 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
by Keith Hui (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Fabian Groffen, Keith Hui, Paul Menzel. Keith Hui has uploaded a new patch set (#10) to the change originally created by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM ...................................................................... mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM Revert super I/O IRQ polarity settings replicated from OEM firmware back to its power-on defaults. With OEM settings COM 1/UART A/serial port 1 gets blocked right after the kernel boots. It no longer works or responds, which actually means the Linux boot process gets stuck forever when configured to write to ttyS0. Also revised the comment on another SIO setting to say it's being set for PECI. TEST=Not using these settings, I have not found any downside. Serial keeps working, sensors still work, S3 suspend/resume works correctly. Reported by Fabian and confirmed Keith. Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Signed-off-by: Keith Hui <buurin(a)gmail.com> Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75137/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 10 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2024