coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Enable EARLY_MMU_INIT
by Yu-Ping Wu (Code Review) 06 Nov '24

06 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84897?usp=email ) Change subject: soc/mediatek/mt8196: Enable EARLY_MMU_INIT ...................................................................... soc/mediatek/mt8196: Enable EARLY_MMU_INIT The boot time is improved by 58ms in bootblock. (78ms -> 20m) BUG=b:361729697 TEST=check cbmem Change-Id: I27ce378ba8e3744cfb3921835e34b32bbba991cb Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84897 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index d97b092..d373b95 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -12,6 +12,7 @@ select FLASH_DUAL_IO_READ select ARM64_USE_ARCH_TIMER select PCI + select EARLY_MMU_INIT if SOC_MEDIATEK_MT8196 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 809f3dc..b73f213 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -10,6 +10,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c +bootblock-y += ../common/bootblock.c bootblock.c bootblock-y += ../common/early_init.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c -- To view, visit https://review.coreboot.org/c/coreboot/+/84897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27ce378ba8e3744cfb3921835e34b32bbba991cb Gerrit-Change-Number: 84897 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Complete PCIe reset in romstage
by Yu-Ping Wu (Code Review) 06 Nov '24

06 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84895?usp=email ) Change subject: mb/google/rauru: Complete PCIe reset in romstage ...................................................................... mb/google/rauru: Complete PCIe reset in romstage De-assert PERST# at romstage to reduce the waiting time in ramstage. BUG=b:361728592 TEST=The boot time improves 62ms Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/romstage.c M src/soc/mediatek/mt8196/Makefile.mk 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 0db6fd2..7ee8759 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/pcie.h> void platform_romstage_main(void) { /* TODO: add romstage main function */ + + if (CONFIG(PCI)) + mtk_pcie_deassert_perst(); } diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index df72ba6..809f3dc 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -16,6 +16,7 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c +romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c romstage-y += emi.c romstage-y += l2c_ops.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c -- To view, visit https://review.coreboot.org/c/coreboot/+/84895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787 Gerrit-Change-Number: 84895 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Enable EARLY_MMU_INIT
by Yidi Lin (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84897?usp=email ) Change subject: soc/mediatek/mt8196: Enable EARLY_MMU_INIT ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27ce378ba8e3744cfb3921835e34b32bbba991cb Gerrit-Change-Number: 84897 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 03:58:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Complete PCIe reset in romstage
by Yidi Lin (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84895?usp=email ) Change subject: mb/google/rauru: Complete PCIe reset in romstage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787 Gerrit-Change-Number: 84895 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 03:58:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/**/spi.h: Enclose complex macros in parentheses
by Yidi Lin (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/85001?usp=email ) Change subject: soc/mediatek/**/spi.h: Enclose complex macros in parentheses ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74 Gerrit-Change-Number: 85001 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 03:57:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Add Fn key scancode
by Rui Zhou (Code Review) 06 Nov '24

06 Nov '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85014?usp=email ) Change subject: mb/google/nissa/var/rull: Add Fn key scancode ...................................................................... mb/google/nissa/var/rull: Add Fn key scancode The Fn key on rull emits a scancode of 94 (0x5e). BUG=b:372211281 TEST=Flash rull, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85014/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 20207f4..743d435 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only config ACPI_FNKEY_GEN_SCANCODE - default 94 if (BOARD_GOOGLE_XOL || BOARD_GOOGLE_RIVEN) + default 94 if (BOARD_GOOGLE_XOL || BOARD_GOOGLE_RIVEN || BOARD_GOOGLE_RULL) config BOARD_GOOGLE_BRYA_COMMON def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/85014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Gerrit-Change-Number: 85014 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: southbridge/intel/common/acpi_pirq_gen: Pass PCI scope as parameter w...
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Shuo Liu. Hello Shuo Liu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85013?usp=email to look at the new patch set (#2). Change subject: southbridge/intel/common/acpi_pirq_gen: Pass PCI scope as parameter when writing _PRT table ...................................................................... southbridge/intel/common/acpi_pirq_gen: Pass PCI scope as parameter when writing _PRT table Add a scope parameter for `intel_write_pci0_PRT()` so that it could be reused for multiple domains. Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/irq/irq.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c 4 files changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85013/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Gerrit-Change-Number: 85013 Gerrit-PatchSet: 2 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIRs
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Shuo Liu. Hello Shuo Liu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85012?usp=email to look at the new patch set (#2). Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIRs ...................................................................... soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIRs ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one of PIRQA-H. This patch adds a funtion `itss_get_dev_pirq()` returning PIRQ for a given device and INT pin. Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/itss/itss.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85012/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 2 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: southbridge/intel/common/acpi_pirq_gen: make PCI scope as parameter w...
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85013?usp=email ) Change subject: southbridge/intel/common/acpi_pirq_gen: make PCI scope as parameter when writing _PRT table ...................................................................... southbridge/intel/common/acpi_pirq_gen: make PCI scope as parameter when writing _PRT table Add a scope parameter for `intel_write_pci0_PRT()` so that it could be reused for multiple domains. Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/irq/irq.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c 4 files changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85013/1 diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index 386538e..16d0fa3 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -397,7 +397,7 @@ entry = entry->next; } - intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map); + intel_write_pci_PRT("\\_SB.PCI0", pin_irq_map, map_count, &pirq_map); free(pin_irq_map); return true; diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 1dadc8e..3b5c3e5 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -43,12 +43,10 @@ } } -void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map, - unsigned int map_count, - const struct pic_pirq_map *pirq_map) +void intel_write_pci_PRT(const char *scope, const struct slot_pin_irq_map *pin_irq_map, + unsigned int map_count, const struct pic_pirq_map *pirq_map) { - /* \_SB.PCI0._PRT */ - acpigen_write_scope("\\_SB.PCI0"); + acpigen_write_scope(scope); acpigen_write_method("_PRT", 0); acpigen_write_if(); acpigen_emit_namestring("PICM"); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h index 36e432e..f22e1d4 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.h +++ b/src/southbridge/intel/common/acpi_pirq_gen.h @@ -84,9 +84,8 @@ * slot/pin combination, and optionally providing paths to LNKx devices that can * provide IRQs in PIC mode. */ -void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map, - unsigned int map_count, - const struct pic_pirq_map *pirq_map); +void intel_write_pci_PRT(const char *scope, const struct slot_pin_irq_map *pin_irq_map, + unsigned int map_count, const struct pic_pirq_map *pirq_map); bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map, unsigned int map_count, unsigned int slot, diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 956fe63..ae22143 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -90,7 +90,7 @@ map_count++; } - intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map); + intel_write_pci_PRT("\\_SB.PCI0", pin_irq_map, map_count, &pirq_map); free(pin_irq_map); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Gerrit-Change-Number: 85013 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT[A-D] to PIRQ using PIR reg...
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

yuchi.chen(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email ) Change subject: soc/intel/common/block/itss: Route PCI INT[A-D] to PIRQ using PIR registers ...................................................................... soc/intel/common/block/itss: Route PCI INT[A-D] to PIRQ using PIR registers ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one of PIRQA-H. This patch adds a funtion `itss_get_pir()` returning PIRQx for a given device and INT pin. Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/itss/itss.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85012/1 diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h index 84ba7b4..e9850a6 100644 --- a/src/soc/intel/common/block/include/intelblocks/itss.h +++ b/src/soc/intel/common/block/include/intelblocks/itss.h @@ -23,6 +23,9 @@ #define PCR_ITSS_PIRQG_ROUT 0x3106 /* PIRQH Routing Control Register */ #define PCR_ITSS_PIRQH_ROUT 0x3107 +/* ITSS Interrupt Route */ +#define PCR_ITSS_PIR 0x3140 +#define PCI_ITSS_PIR(i) (PCR_ITSS_PIR + (i) * 2) /* ITSS Interrupt polarity control */ #define PCR_ITSS_IPC0_CONF 0x3200 /* ITSS Power reduction control */ @@ -30,6 +33,7 @@ #if !defined(__ACPI__) +#include <device/device.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <stdint.h> @@ -43,6 +47,12 @@ void itss_irq_init(const uint8_t pch_interrupt_routing[PIRQ_COUNT]); void itss_clock_gate_8254(void); +/* SoC implemention to return corresponding PIR register offset. */ +uint32_t itss_soc_get_pir(struct device *dev); + +/* Return which PIRQx the device's INTx is connected to. */ +enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin); + #endif /* !defined(__ACPI__) */ #endif /* SOC_INTEL_COMMON_BLOCK_ITSS_H */ diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index 50e4c38..83094e2 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -134,3 +134,12 @@ show_irq_polarities("After"); } + +enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin) +{ + uint16_t pir = pcr_read16(PID_ITSS, itss_soc_get_pir(dev)); + /* The lower 3 bits of every 4 bits indicates which PIRQ is connect to INT. */ + unsigned int pir_shift = (pin - PCI_INT_A) * 4; + unsigned int pir_mask = 0x07; + return ((pir >> pir_shift) & pir_mask) + PIRQ_A; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com

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coreboot-gerrit November 2024