coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2521 discussions

[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83322?usp=email to look at the new patch set (#50). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- A src/mainboard/intel/frost_creek/Kconfig A src/mainboard/intel/frost_creek/Kconfig.name A src/mainboard/intel/frost_creek/Makefile.mk A src/mainboard/intel/frost_creek/acpi/platform.asl A src/mainboard/intel/frost_creek/acpi_tables.c A src/mainboard/intel/frost_creek/board.fmd A src/mainboard/intel/frost_creek/board_id.c A src/mainboard/intel/frost_creek/board_id.h A src/mainboard/intel/frost_creek/board_info.txt A src/mainboard/intel/frost_creek/devicetree.cb A src/mainboard/intel/frost_creek/dsdt.asl A src/mainboard/intel/frost_creek/gpio.c A src/mainboard/intel/frost_creek/ramstage.c A src/mainboard/intel/frost_creek/ramstage.h A src/mainboard/intel/frost_creek/romstage.c A src/mainboard/intel/frost_creek/romstage.h 16 files changed, 640 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/50 -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 50 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#46). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/pch_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/dlb.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/itss.c A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 64 files changed, 4,948 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/46 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 46 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: soc/intel/common/systemagent_server: Add server platform system agent
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel, yuchi.chen(a)intel.com. Hello Angel Pons, Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83318?usp=email to look at the new patch set (#28). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/systemagent_server: Add server platform system agent ...................................................................... soc/intel/common/systemagent_server: Add server platform system agent Intel server process has a different system agent design, it has some differences with client platform such as (1) no BDSM and BGSM registers; (2) different alignment size and bit fields in TOLUD, TOUUD and TSEG registers. Thus this patch adds a new common block for server platform system agent. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/systemagent_server.h A src/soc/intel/common/block/systemagent-server/Kconfig A src/soc/intel/common/block/systemagent-server/Makefile.mk A src/soc/intel/common/block/systemagent-server/common.c A src/soc/intel/common/block/systemagent-server/memmap.c A src/soc/intel/common/block/systemagent-server/systemagent.c A src/soc/intel/common/block/systemagent-server/systemagent_early.c 7 files changed, 416 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 28 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Felix Held (Code Review) 06 Nov '24

06 Nov '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84786?usp=email to look at the new patch set (#10). Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... drivers/spi/spi_flash_sfdp: add basic SFDP support Add basic support for the Serial Flash Discoverable Parameters (SFDP) standard which can be used to discover the parameters to interact with a specific SPI flash chip that supports this mechanism. This commit adds functionality to find specific SFDP parameter headers and print all SFDP parameter headers, but not to parse any SFDP parameter table. This is a preparation for a follow-up patch that adds support to parse the RPMC SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in the next patch, it's marked as static inline in this commit so that the code still build; the 'inline' keyword will be removed again in that follow-up patch. JESD216F.02 was used as a reference. TEST=On a board with a W74M12JW SPI flash chip, calling 'spi_flash_print_sfdp_headers' prints this on the console output: Manufacturer: ef SF: Detected ef 6018 with sector size 0x1000, total 0x1000000 SF: Exiting 4-byte addressing mode SFDP header found in SPI flash. major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3 SFPD header with index 0: table ID 0xff00, major rev 0x1, minor rev 0x6 table pointer 0x80, table length DWORDS 0x10 SFPD header with index 1: table ID 0xff84, major rev 0x1, minor rev 0x0 table pointer 0xd0, table length DWORDS 0x2 SFPD header with index 2: table ID 0xff03, major rev 0x1, minor rev 0x0 table pointer 0xf0, table length DWORDS 0x2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.mk A src/drivers/spi/spi_flash_sfdp.c M src/include/spi_flash.h 4 files changed, 210 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/84786/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Robert Chen (Code Review) 06 Nov '24

06 Nov '24

Robert Chen has posted comments on this change by Robert Chen. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email ) Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 02:30:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Felix Held (Code Review) 06 Nov '24

06 Nov '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84786?usp=email to look at the new patch set (#9). Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... drivers/spi/spi_flash_sfdp: add basic SFDP support Add basic support for the Serial Flash Discoverable Parameters (SFDP) standard which can be used to discover the parameters to interact with a specific SPI flash chip that supports this mechanism. This commit adds functionality to find specific SFDP parameter headers and print all SFDP parameter headers, but not to parse any SFDP parameter table. This is a preparation for a follow-up patch that adds support to parse the RPMC SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in the next patch, it's marked as static inline in this commit so that the code still build; the 'inline' keyword will be removed again in that follow-up patch. JESD216F.02 was used as a reference. TEST=On a board with a W74M12JW SPI flash chip, calling 'spi_flash_print_sfdp_headers' prints this on the console output: Manufacturer: ef SF: Detected ef 6018 with sector size 0x1000, total 0x1000000 SF: Exiting 4-byte addressing mode SFDP header found in SPI flash. major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3 SFPD header with index 0: table ID 0xff00, major rev 0x1, minor rev 0x6 table pointer 0x80, table length DWORDS 0x10 SFPD header with index 1: table ID 0xff84, major rev 0x1, minor rev 0x0 table pointer 0xd0, table length DWORDS 0x2 SFPD header with index 2: table ID 0xff03, major rev 0x1, minor rev 0x0 table pointer 0xf0, table length DWORDS 0x2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.mk A src/drivers/spi/spi_flash_sfdp.c M src/include/spi_flash.h 4 files changed, 210 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/84786/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
by Eric Lai (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Subrata Banik, hualin wei. Eric Lai has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email ) Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Gerrit-Change-Number: 84951 Gerrit-PatchSet: 4 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 02:09:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Robert Chen (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Robert Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85011?usp=email to look at the new patch set (#2). Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:377400590 TEST=Tested on Drawman with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 BRANCH=firmware-dedede-13606.B Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85011/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Li1 Feng (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Bora Guvendik, Pranava Y N, Subrata Banik, YH Lin. Li1 Feng has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84998/comment/1dad7a3c_2ea163af?us… : PS1, Line 236: chip drivers/intel/ish : register "firmware_name" = ""ish_fw.bin"" : register "add_acpi_dma_property" = "true" > > Li Feng was telling me that firmware_name property is not needed anymore since kernel has hard cod […] Correct. From PTL, there is new ISH loader code implemented. Kernel will handle ISH image name. We don't have to add in CB. -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 02:01:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Robert Chen (Code Review) 06 Nov '24

06 Nov '24

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85011?usp=email ) Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:377400590 TEST=Tested on Drawman with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 BRANCH=firmware-dedede-13606.B SSigned-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85011/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 67c9262..6c745d9 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -7,6 +7,9 @@ end chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera -- To view, visit https://review.coreboot.org/c/coreboot/+/85011?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Gerrit-Change-Number: 85011 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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coreboot-gerrit November 2024