coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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2521 discussions

[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Subrata Banik (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Bora Guvendik, Li1 Feng, Pranava Y N, YH Lin. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84998/comment/dfa3ec9c_7dee370d?us… : PS1, Line 236: chip drivers/intel/ish : register "firmware_name" = ""ish_fw.bin"" : register "add_acpi_dma_property" = "true" > Correct. From PTL, there is new ISH loader code implemented. Kernel will handle ISH image name. We don't have to add in CB. let me remove this entry in that case. -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 04:32:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Li1 Feng <li1.feng(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Add Fn key scancode
by Subrata Banik (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85014?usp=email ) Change subject: mb/google/nissa/var/rull: Add Fn key scancode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Gerrit-Change-Number: 85014 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 04:29:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox: Hint romstage init about upcoming reset
by Subrata Banik (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Bob Moragues, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Shyam Sundar Radjacoumar. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84937?usp=email ) Change subject: mb/google/brox: Hint romstage init about upcoming reset ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Gerrit-Change-Number: 84937 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 04:28:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info
by Subrata Banik (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Forest Mittelberg, Karthik Ramasubramanian, Nick Vaccaro, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85005?usp=email ) Change subject: ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Gerrit-Change-Number: 85005 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 04:27:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: southbridge/intel/common: Imrpove ACPI _PRT method generation
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Shuo Liu, yuchi.chen(a)intel.com. Hello Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85013?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: southbridge/intel/common: Imrpove ACPI _PRT method generation ...................................................................... southbridge/intel/common: Imrpove ACPI _PRT method generation Add a scope parameter for `intel_write_pci0_PRT()` so that it could be reused for multiple domains. Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/irq/irq.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c 4 files changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85013/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Gerrit-Change-Number: 85013 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
by Name of user not set (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Shuo Liu, yuchi.chen(a)intel.com. Hello Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85012?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ...................................................................... soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one of PIRQA-H. This patch adds a function itss_get_dev_pirq() returning PIRQ for a given device and INT pin. Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/itss/itss.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85012/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Ronak Kanabar has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/84724?usp=email ) Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 4: (2 comments) Patchset: PS3: > Please remove WIP tag and mark this patch as active. Done Commit Message: https://review.coreboot.org/c/coreboot/+/84724/comment/44b562ba_6c71b13e?us… : PS3, Line 10: It select > Nit: This patch selects Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Gerrit-Change-Number: 84724 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 04:10:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Subrata Banik. Hello Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84724?usp=email to look at the new patch set (#4). Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION This patch introduces support for storing the MRC cache based on the MRC version for RPL platforms. This patch selects the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_RAPTORLAKE is chosen. BUG=b:281846937 TEST=Able to build and boot google/brox and verify MRC version in CBMEM. Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/84724/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Gerrit-Change-Number: 84724 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Ronak Kanabar, Subrata Banik. Ronak Kanabar has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/84724?usp=email ) Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Gerrit-Change-Number: 84724 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Nov 2024 04:08:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Yu-Ping Wu (Code Review) 06 Nov '24

06 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84896?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... soc/mediatek/mt8196: Disable irq2axi feature Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled by checking /proc/interrupts. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/romstage.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/irq2axi.h A src/soc/mediatek/mt8196/irq2axi.c 4 files changed, 39 insertions(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 7ee8759..98e8cd9 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/irq2axi.h> #include <soc/pcie.h> void platform_romstage_main(void) { - /* TODO: add romstage main function */ + irq2axi_disable(); if (CONFIG(PCI)) mtk_pcie_deassert_perst(); diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index b73f213..6b29e73 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -19,6 +19,7 @@ romstage-y += ../common/cbmem.c romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c romstage-y += emi.c +romstage-y += irq2axi.c romstage-y += l2c_ops.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c diff --git a/src/soc/mediatek/mt8196/include/soc/irq2axi.h b/src/soc/mediatek/mt8196/include/soc/irq2axi.h new file mode 100644 index 0000000..22071e5 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/irq2axi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8196_IRQ2AXI_H +#define SOC_MEDIATEK_MT8196_IRQ2AXI_H + +#define IRQ2AXI_BASE 0x14413000 +#define IRQ2AXI_CFG1 (IRQ2AXI_BASE + 0x0004) + +#define APIFR_AO_IO_INTX_SEC_REG 0x101C9000 +#define CIRQ_AXI_MODE (APIFR_AO_IO_INTX_SEC_REG + 0x900) +#define CIRQ_AXI_MODE_LEGACY 0x3 + +#define MCUSYS_ACK_REG 0x0C00FFEC +#define MCUSYS_ACK_CLR 0x1 + +void irq2axi_disable(void); + +#endif /* SOC_MEDIATEK_MT8196_IRQ2AXI_H */ diff --git a/src/soc/mediatek/mt8196/irq2axi.c b/src/soc/mediatek/mt8196/irq2axi.c new file mode 100644 index 0000000..e0250a9 --- /dev/null +++ b/src/soc/mediatek/mt8196/irq2axi.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/irq2axi.h> + +void irq2axi_disable(void) +{ + printk(BIOS_DEBUG, "%s\n", __func__); + /* disable IRQ2AXI */ + write32p(IRQ2AXI_CFG1, 0x0); + + /* disable mcusys ack */ + clrbits32p(MCUSYS_ACK_REG, MCUSYS_ACK_CLR); + + /* switch to legacy channel */ + clrbits32p(CIRQ_AXI_MODE, CIRQ_AXI_MODE_LEGACY); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit November 2024