coreboot-gerrit November 2024

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[S] Change in coreboot[main]: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
by Robert Chen (Code Review) 06 Nov '24

06 Nov '24

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85010?usp=email ) Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ...................................................................... mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:377400590 TEST=Tested on Drawman with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 BRANCH=firmware-dedede-13606.B Change-Id: Ib9a393dbc23e80633bf01ccdab75286e3c636c8f Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 5 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/85010/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 26c5729..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 26c572974bcf7255930b0e9a51da3144ed0104b5 +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index 45f1b75..fe7040a 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 45f1b757402f9a0ae8a4e021a8f5745318515308 +Subproject commit fe7040a278642dc3d28e20eb7e7866cb6e2ac2ac diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 129f82f..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 129f82f7429c29976b15d6837d2f573cc6a02c26 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index a252198..9d52d27 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit a252198ec6544e13904cfe831cec3e784aaa715d +Subproject commit 9d52d272e1b883d5560d84303526972a220cc678 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 67c9262..6c745d9 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -7,6 +7,9 @@ end chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera -- To view, visit https://review.coreboot.org/c/coreboot/+/85010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9a393dbc23e80633bf01ccdab75286e3c636c8f Gerrit-Change-Number: 85010 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration
by Felix Held (Code Review) 06 Nov '24

06 Nov '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83911?usp=email ) Change subject: mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration ...................................................................... mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration Looking at Intel document 759603 revision 001, Alder Lake N only has 5 PCIe clock outputs and clock request pins. I only have the version 2 of this board which has a significantly different USB port configuration to version 1, but there the Ethernet controller on RP 11 and the E key m.2 slot on RP 12 share the last PCIe clock output. The on-board TUBF0304 clock buffer chip takes the clock output form the last PCH PCIe clock generator output and drives the clock inputs of both the last Ethernet chip and the E key m.2 slot. Since the last clock output is always active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the non-existent clock output and request for RP 12 didn't break things. ASPM L0s might still work though, since that one doesn't involve switching off the PCIe reference clock, but haven't tested that yet. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83911 Reviewed-by: coreboot org <coreboot.org(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/cwwk/adl/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve coreboot org: Looks good to me, approved diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index 86a31e7..72a1a98 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -42,9 +42,9 @@ }" register "pch_pcie_rp[PCH_RP(12)]" = "{ - .clk_src = 5, - .clk_req = 5, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .pcie_rp_aspm = ASPM_DISABLE, }" # Enable EDP in PortA -- To view, visit https://review.coreboot.org/c/coreboot/+/83911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378 Gerrit-Change-Number: 83911 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Felix Held (Code Review) 06 Nov '24

06 Nov '24

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84786?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 01:50:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/spi: add RPMC info to spi_flash struct
by Felix Held (Code Review) 06 Nov '24

06 Nov '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85009?usp=email ) Change subject: drivers/spi: add RPMC info to spi_flash struct ...................................................................... drivers/spi: add RPMC info to spi_flash struct Fill 'rpmc_caps' struct inside the 'spi_flash' struct with the RPMC info from the SFDP table. TEST=On a board with a W74M12JW SPI flash chip, the 'rpmc_caps' struct has the expected entries (RPMC available, OP2 extended status as polling method, 4 RPMC counters, OP1 is 0x9b, and OP2 is 0x96). Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9 --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.mk M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h A src/drivers/spi/spi_flash_rpmc.c M src/include/spi_flash.h 6 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/85009/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 72fcec5..5d9698e 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -194,6 +194,12 @@ help Include serial flash discoverable parameters (SFDP) support. +config SPI_FLASH_RPMC + bool + select SPI_FLASH_SFDP + help + Include replay-protected monotonic counter (RPMC) support. + endif # SPI_FLASH config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT diff --git a/src/drivers/spi/Makefile.mk b/src/drivers/spi/Makefile.mk index d873c90..3310b96 100644 --- a/src/drivers/spi/Makefile.mk +++ b/src/drivers/spi/Makefile.mk @@ -32,6 +32,7 @@ $(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c $(1)-$(CONFIG_SPI_FLASH_ISSI) += issi.c $(1)-$(CONFIG_SPI_FLASH_SFDP) += spi_flash_sfdp.c +$(1)-$(CONFIG_SPI_FLASH_RPMC) += spi_flash_rpmc.c endef $(eval $(call add_spi_stage,bootblock,_EARLY)) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 6ecd29f..b7a024c 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -569,6 +569,11 @@ spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0); } + /* TODO: only do this in stages that will need to call those functions? */ + if (CONFIG(SPI_FLASH_RPMC)) { + spi_flash_fill_rpmc_caps(flash); + } + return 0; } diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 830a178..a30f58f 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -159,4 +159,7 @@ enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, struct sfdp_rpmc_info *rpmc_info); +/* Fill rpmc_caps field in spi_flash struct with RPMC config from SFDP */ +void spi_flash_fill_rpmc_caps(struct spi_flash *flash); + #endif /* SPI_FLASH_INTERNAL_H */ diff --git a/src/drivers/spi/spi_flash_rpmc.c b/src/drivers/spi/spi_flash_rpmc.c new file mode 100644 index 0000000..148e3bb --- /dev/null +++ b/src/drivers/spi/spi_flash_rpmc.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include <string.h> +#include <timer.h> +#include <types.h> + +#include "spi_flash_internal.h" + +void spi_flash_fill_rpmc_caps(struct spi_flash *flash) +{ + struct sfdp_rpmc_info rpmc_info; + + flash->rpmc_caps.rpmc_available = false; + + if (spi_flash_get_sfdp_rpmc(flash, &rpmc_info) != CB_SUCCESS) + return; + + if (rpmc_info.monotonic_counter_size != SFDP_RPMC_COUNTER_BITS_32) { + printk(BIOS_WARNING, "RPMC: unexpected counter size\n"); + return; + } + + flash->rpmc_caps.poll_op2_ext_stat = rpmc_info.busy_polling_method == + SFDP_RPMC_POLL_OP2_EXTENDED_STATUS; + flash->rpmc_caps.number_of_counters = rpmc_info.number_of_counters; + flash->rpmc_caps.op1_write_cmd = rpmc_info.op1_write_command; + flash->rpmc_caps.op2_read_cmd = rpmc_info.op2_read_command; + flash->rpmc_caps.rpmc_available = true; +} diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 7736a94..76c33be 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -95,6 +95,14 @@ struct spi_flash_part_id; +struct spi_flash_rpmc_cap { + bool rpmc_available; + bool poll_op2_ext_stat; + unsigned int number_of_counters; + uint8_t op1_write_cmd; + uint8_t op2_read_cmd; +}; + struct spi_flash { struct spi_slave spi; u8 vendor; @@ -118,6 +126,7 @@ /* If !NULL all protection callbacks exist. */ const struct spi_flash_protection_ops *prot_ops; const struct spi_flash_part_id *part; + struct spi_flash_rpmc_cap rpmc_caps; }; void lb_spi_flash(struct lb_header *header); -- To view, visit https://review.coreboot.org/c/coreboot/+/85009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9 Gerrit-Change-Number: 85009 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters
by Felix Held (Code Review) 06 Nov '24

06 Nov '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85008?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters ...................................................................... drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters JESD216F.02 and JESD260 were used as a reference. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 --- M src/drivers/spi/spi_flash_internal.h M src/drivers/spi/spi_flash_sfdp.c 2 files changed, 176 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/85008/1 diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index d0f32c5..830a178 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -136,4 +136,27 @@ /* Page Programming Command Set with 0xd8 Sector Erase command. */ extern const struct spi_flash_ops_descriptor spi_flash_pp_0xd8_sector_desc; +struct sfdp_rpmc_info { + bool flash_hardening; + enum { + SFDP_RPMC_COUNTER_BITS_32 = 0, + SFDP_RPMC_COUNTER_BITS_RESERVED = 1, + } monotonic_counter_size; + enum { + SFDP_RPMC_POLL_OP2_EXTENDED_STATUS = 0, + SFDP_RPMC_POLL_READ_STATUS = 1, + } busy_polling_method; + uint8_t number_of_counters; + uint8_t op1_write_command; + uint8_t op2_read_command; + uint64_t update_rate_s; + uint64_t read_counter_polling_delay_us; + uint64_t write_counter_polling_short_delay_us; + uint64_t write_counter_polling_long_delay_us; +}; + +/* Get RPMC information from the SPI flash's SFDP table */ +enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, + struct sfdp_rpmc_info *rpmc_info); + #endif /* SPI_FLASH_INTERNAL_H */ diff --git a/src/drivers/spi/spi_flash_sfdp.c b/src/drivers/spi/spi_flash_sfdp.c index e6b32fa..885df17 100644 --- a/src/drivers/spi/spi_flash_sfdp.c +++ b/src/drivers/spi/spi_flash_sfdp.c @@ -154,10 +154,9 @@ } } -static inline enum cb_err find_sfdp_parameter_header(const struct spi_flash *flash, - uint16_t table_id, uint16_t *revision, - uint8_t *length_dwords, - uint32_t *table_pointer) +static enum cb_err find_sfdp_parameter_header(const struct spi_flash *flash, uint16_t table_id, + uint16_t *revision, uint8_t *length_dwords, + uint32_t *table_pointer) { enum cb_err stat; uint16_t sfdp_rev; @@ -190,3 +189,153 @@ return CB_ERR; } + +#define SFDP_PARAMETER_ID_RPMC 0xff03 + +#define SFDP_RPMC_TABLE_LENGTH_DWORDS 2 +#define SFDP_RPMC_TABLE_SUPPORTED_MAJOR_REV 1 + +/* RPMC parameter table byte offsets and fields */ +#define SFDP_RPMC_TABLE_CONFIG 0 +#define SFDP_RPMC_TABLE_CONFIG_FLASH_HARDENING_BIT BIT(0) +#define SFDP_RPMC_TABLE_CONFIG_MONOTONIC_COUNTER_SIZE_BIT BIT(1) +#define SFDP_RPMC_TABLE_CONFIG_BUSY_POLLING_METHOD BIT(2) +#define SFDP_RPMC_TABLE_CONFIG_RESERVED BIT(3) +#define SFDP_RPMC_TABLE_CONFIG_RESERVED_VALUE 0x08 +#define SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_MASK 0xf0 +#define SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_SHIFT 4 +#define SFDP_RPMC_TABLE_RPMC_OP1 1 +#define SFDP_RPMC_TABLE_RPMC_OP2 2 +#define SFDP_RPMC_TABLE_UPDATE_RATE 3 +#define SFDP_RPMC_TABLE_UPDATE_RATE_MASK 0x0f +#define SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_MASK 0xf0 +#define SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_VALUE 0xf0 +#define SFDP_RPMC_TABLE_READ_COUNTER_POLLING_DELAY 4 +#define SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_SHORT_DELAY 5 +#define SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_LONG_DELAY 6 +#define SFDP_RPMC_TABLE_RESERVED_BYTE 7 +#define SFDP_RPMC_TABLE_RESERVED_BYTE_VALUE 0xff + +static uint64_t calc_rpmc_update_rate_s(uint8_t val) +{ + /* val is at most 15, so this won't overflow */ + return 5 * 1 << (val & SFDP_RPMC_TABLE_UPDATE_RATE_MASK); +} + +#define SPDF_RPMC_DELAY_VALUE_MASK 0x1f +#define SPDF_RPMC_DELAY_UNIT_MASK 0x60 +#define SPDF_RPMC_DELAY_UNIT_SHIFT 5 +#define SPDF_RPMC_DELAY_SHORT_UNIT_0_US 1 /* 1us */ +#define SPDF_RPMC_DELAY_SHORT_UNIT_1_US 16 /* 16us */ +#define SPDF_RPMC_DELAY_SHORT_UNIT_2_US 128 /* 128us */ +#define SPDF_RPMC_DELAY_SHORT_UNIT_3_US 1000 /* 1ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_0_US 1000 /* 1ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_1_US 16000 /* 16ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_2_US 128000 /* 128ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_3_US 1000000 /* 1s */ + +static uint64_t calc_rpmc_short_delay_us(uint8_t val) +{ + const uint8_t value = val & SPDF_RPMC_DELAY_VALUE_MASK; + const uint8_t shift = (val & SPDF_RPMC_DELAY_UNIT_MASK) >> SPDF_RPMC_DELAY_UNIT_SHIFT; + uint64_t multiplicator; + + switch (shift) { + case 0: + multiplicator = SPDF_RPMC_DELAY_SHORT_UNIT_0_US; + break; + case 1: + multiplicator = SPDF_RPMC_DELAY_SHORT_UNIT_1_US; + break; + case 2: + multiplicator = SPDF_RPMC_DELAY_SHORT_UNIT_2_US; + break; + default: + multiplicator = SPDF_RPMC_DELAY_SHORT_UNIT_3_US; + break; + } + + return value * multiplicator; +} + +static uint64_t calc_rpmc_long_delay_us(uint8_t val) +{ + const uint8_t value = val & SPDF_RPMC_DELAY_VALUE_MASK; + const uint8_t shift = (val & SPDF_RPMC_DELAY_UNIT_MASK) >> SPDF_RPMC_DELAY_UNIT_SHIFT; + uint64_t multiplicator; + + switch (shift) { + case 0: + multiplicator = SPDF_RPMC_DELAY_LONG_UNIT_0_US; + break; + case 1: + multiplicator = SPDF_RPMC_DELAY_LONG_UNIT_1_US; + break; + case 2: + multiplicator = SPDF_RPMC_DELAY_LONG_UNIT_2_US; + break; + default: + multiplicator = SPDF_RPMC_DELAY_LONG_UNIT_3_US; + break; + } + + return value * multiplicator; +} + +enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, + struct sfdp_rpmc_info *rpmc_info) +{ + uint16_t rev; + uint8_t length_dwords; + uint32_t table_pointer; + uint8_t buf[SFDP_RPMC_TABLE_LENGTH_DWORDS * sizeof(uint32_t)]; + + if (find_sfdp_parameter_header(flash, SFDP_PARAMETER_ID_RPMC, &rev, &length_dwords, + &table_pointer) != CB_SUCCESS) + return CB_ERR; + + if (length_dwords != SFDP_RPMC_TABLE_LENGTH_DWORDS) + return CB_ERR; + + if (rev >> 8 != SFDP_RPMC_TABLE_SUPPORTED_MAJOR_REV) { + printk(BIOS_ERR, "Unsupprted major RPMC table revision %#x\n", rev >> 8); + return CB_ERR; + } + + if (read_sfdp_data(flash, table_pointer, sizeof(buf), buf) != CB_SUCCESS) + return CB_ERR; + + if ((buf[SFDP_RPMC_TABLE_CONFIG] & SFDP_RPMC_TABLE_CONFIG_RESERVED) != + SFDP_RPMC_TABLE_CONFIG_RESERVED_VALUE || + (buf[SFDP_RPMC_TABLE_UPDATE_RATE] & SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_MASK) != + SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_VALUE || + buf[SFDP_RPMC_TABLE_RESERVED_BYTE] != SFDP_RPMC_TABLE_RESERVED_BYTE_VALUE) { + printk(BIOS_ERR, "Unexpected reserved values in RPMC table\n"); + return CB_ERR; + } + + rpmc_info->flash_hardening = !!(buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_FLASH_HARDENING_BIT); + rpmc_info->monotonic_counter_size = (buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_FLASH_HARDENING_BIT) ? + SFDP_RPMC_COUNTER_BITS_RESERVED : + SFDP_RPMC_COUNTER_BITS_32; + rpmc_info->busy_polling_method = (buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_BUSY_POLLING_METHOD) ? + SFDP_RPMC_POLL_READ_STATUS : + SFDP_RPMC_POLL_OP2_EXTENDED_STATUS; + rpmc_info->number_of_counters = ((buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_MASK) >> + SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_SHIFT) + 1; + rpmc_info->op1_write_command = buf[SFDP_RPMC_TABLE_RPMC_OP1]; + rpmc_info->op2_read_command = buf[SFDP_RPMC_TABLE_RPMC_OP2]; + rpmc_info->update_rate_s = calc_rpmc_update_rate_s(buf[SFDP_RPMC_TABLE_UPDATE_RATE] & + SFDP_RPMC_TABLE_UPDATE_RATE_MASK); + rpmc_info->read_counter_polling_delay_us = calc_rpmc_short_delay_us( + buf[SFDP_RPMC_TABLE_READ_COUNTER_POLLING_DELAY]); + rpmc_info->write_counter_polling_short_delay_us = calc_rpmc_short_delay_us( + buf[SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_SHORT_DELAY]); + rpmc_info->write_counter_polling_long_delay_us = calc_rpmc_long_delay_us( + buf[SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_LONG_DELAY]); + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Gerrit-Change-Number: 85008 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Angel Pons (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Máté Kukri, Paul Menzel. Angel Pons has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... Patch Set 17: Code-Review+2 (1 comment) File src/mainboard/dell/optiplex_3050/ramstage.c: https://review.coreboot.org/c/coreboot/+/82053/comment/1b18a717_9b9540c6?us… : PS17, Line 18: // NOTE: one of these is MT, but 2 and 3 both get the same table anyways Probably DT and MT -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 17 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 06 Nov 2024 01:31:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
by Keith Hui (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Fabian Groffen, Keith Hui, Keith Hui. Keith Hui has uploaded a new patch set (#11) to the change originally created by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM ...................................................................... mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM Revert super I/O IRQ polarity settings replicated from OEM firmware back to its power-on defaults. With OEM settings COM 1/UART A/serial port 1 gets blocked right after the kernel boots. It no longer works or responds, which actually means the Linux boot process gets stuck forever when configured to write to ttyS0. Also revised the comment on another SIO setting to say it's being set for PECI. TEST=Not using these settings, I have not found any downside. Serial keeps working, sensors still work, S3 suspend/resume works correctly. Reported by Fabian and confirmed by Keith. Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Signed-off-by: Keith Hui <buurin(a)gmail.com> Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75137/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 11 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of ...
by Rui Zhou (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Rui Zhou has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/84997?usp=email ) Change subject: mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3 ...................................................................... Patch Set 21: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84997/comment/7ad7e584_191f376b?us… : PS20, Line 7: timeing > timing thanks https://review.coreboot.org/c/coreboot/+/84997/comment/d1af7212_117da982?us… : PS20, Line 10: We adjust the position of the enable and reset pins. > According to what source? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Gerrit-Change-Number: 84997 Gerrit-PatchSet: 21 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Nov 2024 01:14:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of ...
by Rui Zhou (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84997?usp=email to look at the new patch set (#21). Change subject: mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3 ...................................................................... mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3 The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/gpio.c M src/mainboard/google/brya/variants/rull/overridetree.cb 2 files changed, 17 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84997/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/84997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Gerrit-Change-Number: 84997 Gerrit-PatchSet: 21 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: drivers/spi/spi_flash: introduce 'spi_flash_cmd_multi'
by Felix Held (Code Review) 06 Nov '24

06 Nov '24

Attention is currently required from: Ana Carolina Cabral, Matt DeVillier. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84789?usp=email ) Change subject: drivers/spi/spi_flash: introduce 'spi_flash_cmd_multi' ...................................................................... Patch Set 5: (1 comment) Patchset: PS1: > discussed this one with Matt and we both think that introducing 'spi_flash_cmd_multi' would be the b […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e Gerrit-Change-Number: 84789 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Tue, 05 Nov 2024 23:13:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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