coreboot-gerrit November 2024

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Yidi Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84497?usp=email ) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... Patch Set 27: (1 comment) File src/soc/mediatek/mt8196/mtcmos.c: https://review.coreboot.org/c/coreboot/+/84497/comment/d84f3303_e43792ad?us… : PS26, Line 886: mtcmos_cb_register > no, the api would be called in mminfra @jarried.lin@mediatek.com @guangjie.song@mediatek.corp-partner.google.com can you also submit the mminfra patch ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 03:49:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77046?usp=email ) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H This board is based off ga-b75m-d3h, which uses the same SuperIO chip. It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with 2 SATA3 ports next to the 4 SATA2 ports. Flashing notes: These boards come with dual-BIOS feature. This is set of two unremovable what appears to be identical chips marked M_BIOS and B_BIOS. Flash the B_BIOS chip, and boot the system. Ensure you have a payload and setup ready to boot a Linux system with iomem=relaxed or similar. Immediately use flashrom -p internal to flash the same firmware again. If you skip this step your next boot will show weird exception traces in either coreboot or your payload. Flashing from there via the chip is very difficult (you have to try many times in order to get a booting run), which can all be remedied by doing a flash from internal. I suppose the dual-BIOS feature is somewhat in the way here. Tested with: - CPU Core i7-3770S - RAM single bank 4GB CL11, two banks 4+4GB CL11 - OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload - Intel ME stripped - Integrated graphics with libgfxinit - (boot from) SATA2, SATA3 ports - Rear and mainboard connector USB ports, supporting boot - Atheros GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS events) - S3 suspend/resume - PWM FAN control, FAN speed readings - Temperature sensor readings Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Reviewed-on: https://review.coreboot.org/c/coreboot/+/77046 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-h77m-d3h/Makefile.mk A src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl A src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt A src/mainboard/gigabyte/ga-h77m-d3h/cmos.default A src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout A src/mainboard/gigabyte/ga-h77m-d3h/data.vbt A src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb A src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl A src/mainboard/gigabyte/ga-h77m-d3h/early_init.c A src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads A src/mainboard/gigabyte/ga-h77m-d3h/gpio.c A src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c A src/mainboard/gigabyte/ga-h77m-d3h/thermal.h 17 files changed, 565 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig new file mode 100644 index 0000000..6d7532a --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_GIGABYTE_GA_H77M_D3H + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select SERIRQ_CONTINUOUS_MODE + select MAINBOARD_HAS_LIBGFXINIT + select MEMORY_MAPPED_TPM + +config DRAM_RESET_GATE_GPIO + int + # Use GPIO25 because it does not exist on desktop PCHs and because + # this board does not use DRAM reset gate GPIO + default 25 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + default "gigabyte/ga-h77m-d3h" + +config MAINBOARD_PART_NUMBER + default "GA-H77M-D3H" + +endif # BOARD_GIGABYTE_GA_H77_D3H diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name new file mode 100644 index 0000000..792a954 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_GIGABYTE_GA_H77M_D3H + bool "GA-H77M-D3H" diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/Makefile.mk b/src/mainboard/gigabyte/ga-h77m-d3h/Makefile.mk new file mode 100644 index 0000000..ebc5434 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl new file mode 100644 index 0000000..b9be1a3 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return (Package () {0, 0}) +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt new file mode 100644 index 0000000..049ac3b --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-H77M-D3H-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/cmos.default b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.default new file mode 100644 index 0000000..6f3cec7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout new file mode 100644 index 0000000..8c6a055 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/data.vbt b/src/mainboard/gigabyte/ga-h77m-d3h/data.vbt new file mode 100644 index 0000000..ccbf6ee --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/data.vbt Binary files differ diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb new file mode 100644 index 0000000..ce64324 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb @@ -0,0 +1,116 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x003c0a01" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "usb_port_config" = "{ + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 } + }" + + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + + device ref xhci on # USB 3.0 Controller + subsystemid 0x1458 0x5007 + end + device ref mei1 off end # Management Engine Interface 1 + device ref ehci2 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device ref hda on # High Definition Audio + subsystemid 0x1458 0xa002 + end + device ref pcie_rp1 on end # PCIe Port #1: PCIEX4 slot + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on # PCIe Port #5: AR8161 GbE + device pci 00.0 on end + end + device ref pcie_rp6 on end # PCIe Port #6: PCIEX1 slot + device ref pcie_rp7 on end # PCIe Port #7: IT8892E PCIe-to-PCI + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device ref pci_bridge off end # PCI bridge + device ref lpc on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN1.min" = "-10" + register "TMPIN1.max" = "100" + register "TMPIN2.mode" = "THERMAL_MODE_DISABLED" + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "100" + register "TMPIN3.min" = "0" + register "TMPIN3.max" = "100" + + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # EC + io 0x60 = 0xa30 + irq 0x70 = 9 + io 0x62 = 0xa20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR + end + + chip drivers/pc80/tpm + device pnp 0c31.0 off end + end + end + device ref sata1 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device ref smbus on # SMBus + subsystemid 0x1458 0x5001 + end + device ref sata2 off end # SATA Controller 2 + end + end +end diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl new file mode 100644 index 0000000..b0ddd6d --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/early_init.c b/src/mainboard/gigabyte/ga-h77m-d3h/early_init.c new file mode 100644 index 0000000..b9f7891 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/early_init.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SUPERIO_BASE 0x2e +#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot + + /* FIXME: These values could be configured in ramstage */ + ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable + ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ? + ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ? + ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads new file mode 100644 index 0000000..cdf051d --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-only + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/gpio.c b/src/mainboard/gigabyte/ga-h77m-d3h/gpio.c new file mode 100644 index 0000000..e4358fa --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/gpio.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio12 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio30 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c new file mode 100644 index 0000000..396d458 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x11060441, /* Codec Vendor / Device ID: VIA VT2020 */ + 0x1458a014, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a014), + AZALIA_PIN_CFG(2, 0x24, 0x01014010), + AZALIA_PIN_CFG(2, 0x25, 0x410110f0), + AZALIA_PIN_CFG(2, 0x26, 0x410160f0), + AZALIA_PIN_CFG(2, 0x27, 0x410120f0), + AZALIA_PIN_CFG(2, 0x28, 0x0221401f), + AZALIA_PIN_CFG(2, 0x29, 0x02a19037), + AZALIA_PIN_CFG(2, 0x2a, 0x0181303e), + AZALIA_PIN_CFG(2, 0x2b, 0x01a19036), + AZALIA_PIN_CFG(2, 0x2c, 0x503701f0), + AZALIA_PIN_CFG(2, 0x2d, 0x474511f0), + AZALIA_PIN_CFG(2, 0x2e, 0x074521f0), + AZALIA_PIN_CFG(2, 0x2f, 0x47c521f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/thermal.h b/src/mainboard/gigabyte/ga-h77m-d3h/thermal.h new file mode 100644 index 0000000..f68eeb7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/thermal.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef GAB75MD3H_THERMAL_H +#define GAB75MD3H_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/77046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 77046 Gerrit-PatchSet: 11 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[L] Change in coreboot[main]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Angel Pons, Fabian Groffen, Patrick Rudolph. Felix Singer has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/77046?usp=email ) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: Looks reasonable to me. Some more cleanups would be nice, but these can be addressed in follow-ups. Thank you! -- To view, visit https://review.coreboot.org/c/coreboot/+/77046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 77046 Gerrit-PatchSet: 10 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 03:44:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and clock init support
by Yidi Lin (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email ) Change subject: soc/mediatek/mt8196: Add PLL and clock init support ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Gerrit-Change-Number: 84495 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 03:43:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Angel Pons, Fabian Groffen, Patrick Rudolph. Felix Singer has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/77046?usp=email ) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 77046 Gerrit-PatchSet: 10 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 03:43:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Máté Kukri, Paul Menzel. Felix Singer has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 19 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 03:24:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Máté Kukri, Paul Menzel. Felix Singer has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: Replaced the gitiles URL with the repo URL, since gitiles is disabled at the moment. -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 19 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 03:24:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Máté Kukri, Paul Menzel. Felix Singer has uploaded a new patch set (#19) to the change originally created by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) ...................................................................... mb/dell: OptiPlex 3050 Micro port (Intel KabyLake) - Boots Linux 6.11 (Debian) - GRUB and SeaBIOS payloads work - SMSC SCH5553 SIO/EC + Serial port works + PWM fan control works - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/admin/repos/deguard,general - Audio works - All USB ports work - Currently limited to the Micro form factor, but others are very similar - HDA verbs and VBT by Leah Rowe Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- A src/mainboard/dell/optiplex_3050/Kconfig A src/mainboard/dell/optiplex_3050/Kconfig.name A src/mainboard/dell/optiplex_3050/Makefile.mk A src/mainboard/dell/optiplex_3050/acpi/ec.asl A src/mainboard/dell/optiplex_3050/acpi/superio.asl A src/mainboard/dell/optiplex_3050/board_info.txt A src/mainboard/dell/optiplex_3050/bootblock.c A src/mainboard/dell/optiplex_3050/cmos.default A src/mainboard/dell/optiplex_3050/cmos.layout A src/mainboard/dell/optiplex_3050/data.vbt A src/mainboard/dell/optiplex_3050/devicetree.cb A src/mainboard/dell/optiplex_3050/dsdt.asl A src/mainboard/dell/optiplex_3050/gma-mainboard.ads A src/mainboard/dell/optiplex_3050/hda_verb.c A src/mainboard/dell/optiplex_3050/include/early_gpio.h A src/mainboard/dell/optiplex_3050/include/gpio.h A src/mainboard/dell/optiplex_3050/ramstage.c A src/mainboard/dell/optiplex_3050/romstage.c A src/mainboard/dell/optiplex_3050/sch5555_ec.c A src/mainboard/dell/optiplex_3050/sch5555_ec.h 20 files changed, 1,317 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 19 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[main]: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
by Felix Singer (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Elyes Haouas, Maxim. Felix Singer has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83107?usp=email ) Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard ...................................................................... Patch Set 32: Code-Review+2 (1 comment) Patchset: PS32: Looks reasonable. Thank you! -- To view, visit https://review.coreboot.org/c/coreboot/+/83107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Gerrit-Change-Number: 83107 Gerrit-PatchSet: 32 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 07 Nov 2024 03:17:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Yu-Ping Wu (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84497?usp=email ) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... Patch Set 27: Code-Review+1 (1 comment) File src/soc/mediatek/mt8196/mtcmos.c: https://review.coreboot.org/c/coreboot/+/84497/comment/a9a43a7d_7b331185?us… : PS26, Line 843: { > Done Not changed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 02:41:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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