coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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2521 discussions

[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Configure Acoustic noise mitigation
by David Wu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Paul Menzel. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/84908?usp=email ) Change subject: mb/google/nissa/var/riven: Configure Acoustic noise mitigation ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Could we merge this CL? Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/84908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia71985ef21d634763fc5ae22e4f611f7f5e9652a Gerrit-Change-Number: 84908 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Nov 2024 23:54:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update SAF base address
by Anil Kumar K (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Anil Kumar K, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84863?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Update SAF base address ...................................................................... soc/intel/pantherlake: Update SAF base address BUG=b:357011633 TEST=build and boot coreboot image on Google/Fatcat board. Change-Id: I14fa8cf06144f46369cc8cab6087c790280e9859 Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> --- M src/soc/intel/pantherlake/include/soc/iomap.h 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/84863/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14fa8cf06144f46369cc8cab6087c790280e9859 Gerrit-Change-Number: 84863 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/topton/adl: Add initial support for X2F N100 FW appliance
by Angel Pons (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Alicja Michalska. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/84175?usp=email ) Change subject: mb/topton/adl: Add initial support for X2F N100 FW appliance ...................................................................... Patch Set 9: Code-Review+1 (2 comments) File src/mainboard/topton/adl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84175/comment/cf7c5095_59bdea96?us… : PS2, Line 43: # TODO: SATA doesn't work. EDK2 returns "Unsupported", not sure how to fix (yet). > Yes, I know. I tried setting it, but it didn't work. […] I meant these: ``` register "sata_ports_enable" = "{ [0] = 1, [1] = 1, }" ``` I forget how many SATA ports ADL-N has, though. Also, it could be like the ODROID and use a PCIe-to-SATA controller, did you check that? File src/mainboard/topton/adl/mainboard.c: https://review.coreboot.org/c/coreboot/+/84175/comment/d123e358_d33257b3?us… : PS9, Line 17: params->PchLegacyIoLowLatency = 1; I think I commented on what this was, could you please add a comment so that I don't ask over and over? :D -- To view, visit https://review.coreboot.org/c/coreboot/+/84175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65 Gerrit-Change-Number: 84175 Gerrit-PatchSet: 9 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 21:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Li1 Feng (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Bora Guvendik, Pranava Y N, Subrata Banik. Li1 Feng has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/84998/comment/372d924a_ec87461b?us… : PS2, Line 469: static const struct pad_config ish_enable_pads[] = { > > In the enable, D5&6 are for UART0 […] Sure, I will update them. -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 21:25:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Li1 Feng <li1.feng(a)intel.com>

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[M] Change in coreboot[main]: superio/ite: Add support for IT8625E
by Angel Pons (Code Review) 07 Nov '24

07 Nov '24

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85028?usp=email ) Change subject: soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config ...................................................................... soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs (ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type for the RAMTOP range. Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was crucial to ensure data consistency, as WB caches both reads and writes. However, since the RAMTOP range now relies on WC MTRR, the role of CLFLUSH becomes less critical. Removing CLFLUSH in this scenario can improve performance, as it avoids unnecessary cache invalidations. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/pantherlake/Kconfig 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/85028/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dddf71f..f6e9182 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -96,7 +96,6 @@ select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N && !SOC_INTEL_RAPTORLAKE select VBOOT_LIB - select X86_CLFLUSH_CAR help Intel Alderlake support. Mainboards should specify the PCH type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 4dc6082..73d68df 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -102,7 +102,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202302_BINDING - select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI select INTEL_KEYLOCKER help diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 76a84cd..96324b7 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -105,7 +105,6 @@ select UDELAY_TSC select UDK_202302_BINDING select USE_X86_64_SUPPORT - select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI help Intel Pantherlake support. Mainboards should specify the SoC -- To view, visit https://review.coreboot.org/c/coreboot/+/85028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Gerrit-Change-Number: 85028 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common: Apply Intel recommendation for early ramtop caching
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85027?usp=email ) Change subject: soc/intel/common: Apply Intel recommendation for early ramtop caching ...................................................................... soc/intel/common: Apply Intel recommendation for early ramtop caching Configuring the Early Caching Ramtop range as Write-Back (WB) before memory initialization is NOT RECOMMENDED. Speculative execution within this WB range can lead to issues. WB configuration should be applied to this range ONLY AFTER memory initialization is complete. To enable Ramtop caching before memory initialization, use Write-Combining (WC) instead of Write-Back (WB). This change applies the recommendation by always configuring the early ramtop caching range as WC. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/basecode/ramtop/ramtop.c 1 file changed, 14 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/85027/1 diff --git a/src/soc/intel/common/basecode/ramtop/ramtop.c b/src/soc/intel/common/basecode/ramtop/ramtop.c index 0ef531a..203d343 100644 --- a/src/soc/intel/common/basecode/ramtop/ramtop.c +++ b/src/soc/intel/common/basecode/ramtop/ramtop.c @@ -181,25 +181,19 @@ } size_t ramtop_size = get_ramtop_size(); - /* - * Background: Some SoCs have a critical bug inside the NEM logic which is responsible - * for mapping cached memory to physical memory during tear down and - * eventually malfunctions if the number of cache sets is not a power of two. - * This can lead to runtime hangs. - * - * Workaround: To mitigate this issue on affected SoCs, we force the MTRR type to - * WC (Write Combining) unless the cache set count is a power of two. - * This change alters caching behavior but prevents the runtime failures. - */ - unsigned int mtrr_type = MTRR_TYPE_WRCOMB; - /* - * Late romstage (including FSP-M post-memory initialization) needs to be - * executed from cache for performance reasons. This requires caching - * `ramtop_size`, which encompasses both FSP reserved memory and the CBMEM - * range, to guarantee sufficient cache coverage for late romstage. - */ - if (is_cache_sets_power_of_two()) - mtrr_type = MTRR_TYPE_WRBACK; + if (!ramtop_size) + return; - set_var_mtrr(mtrr, ramtop - ramtop_size, ramtop_size, mtrr_type); + /* + * INTEL RECOMMENDATION: Early Ramtop Caching Configuration + * + * Configuring the Early Caching Ramtop range as Write-Back (WB) before + * memory initialization is NOT RECOMMENDED. Speculative execution within + * this WB range can lead to issues. WB configuration should be applied + * to this range ONLY AFTER memory initialization is complete. + * + * To enable Ramtop caching before memory initialization, use Write-Combining + * (WC) instead of Write-Back (WB). + */ + set_var_mtrr(mtrr, ramtop - ramtop_size, ramtop_size, MTRR_TYPE_WRCOMB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071 Gerrit-Change-Number: 85027 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common: Add RAMTOP size in ramtop_table
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: V Sowmya. Hello V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85003?usp=email to look at the new patch set (#4). Change subject: soc/intel/common: Add RAMTOP size in ramtop_table ...................................................................... soc/intel/common: Add RAMTOP size in ramtop_table This patch adds a new field, `size`, to the `ramtop_table` structure to store the size of the RAMTOP region. The RAMTOP size is calculated as the difference between the cbmem top and the FSP reserved memory base address, aligned up to the nearest 4MB boundary. This change allows for more accurate tracking of the RAMTOP region and improves compatibility with different memory configurations. Previously, the RAMTOP size was always assumed to be 16MB. This could lead to boot hangs on systems with different memory configurations, where the actual RAMTOP size exceeded 16MB. By dynamically calculating and storing the RAMTOP size, this patch ensures that the correct memory range is used for intermediate caching, preventing boot hangs and improving boot speed. The `update_ramtop()` function is updated to write the calculated RAMTOP size to CMOS along with the RAMTOP address. The `early_ramtop_enable_cache_range()` function is also updated to use the RAMTOP size from CMOS to set the correct MTRR range. BUG=b:373290479 TEST=Built and booted successfully on various platforms. Verified that the RAMTOP size is correctly calculated and stored in CMOS Change-Id: I16d610c5791895b59da57d543c54da6621617912 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/basecode/ramtop/ramtop.c 1 file changed, 63 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85003/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16d610c5791895b59da57d543c54da6621617912 Gerrit-Change-Number: 85003 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/[tiger|cannon|meteor]lake: Fix uninitialized usb_cfg pointer
by Jon Murphy (Code Review) 07 Nov '24

07 Nov '24

Jon Murphy has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85026?usp=email ) Change subject: soc/intel/[tiger|cannon|meteor]lake: Fix uninitialized usb_cfg pointer ...................................................................... soc/intel/[tiger|cannon|meteor]lake: Fix uninitialized usb_cfg pointer This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/meteorlake/fsp_params.c: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild for GOOGLE_HATCH, GOOGLE_VOLTEER, GOOGLE_KARIS Change-Id: I169b6d3a979c4db78e7c0932a126d8b0a9306da7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85026 Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 3 files changed, 6 insertions(+), 6 deletions(-) Approvals: Jon Murphy: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index bd3d149..df5fcee 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -531,7 +531,7 @@ /* Enable CNVi Wifi if enabled in device tree */ #if CONFIG(SOC_INTEL_COMETLAKE) struct device *port = NULL; - struct drivers_usb_acpi_config *usb_cfg; + struct drivers_usb_acpi_config *usb_cfg = NULL; bool usb_audio_offload = false; /* Search through the devicetree for matching USB devices */ @@ -564,7 +564,7 @@ if (s_cfg->CnviBtAudioOffload && !usb_audio_offload) { printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver.\n"); } - if (!s_cfg->CnviBtAudioOffload && usb_audio_offload) { + if (!s_cfg->CnviBtAudioOffload && usb_cfg && usb_audio_offload) { printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n"); usb_cfg->cnvi_bt_audio_offload = 0; } diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index c2770e6..0ae36e6 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -578,7 +578,7 @@ const struct soc_intel_meteorlake_config *config) { struct device *port = NULL; - struct drivers_usb_acpi_config *usb_cfg; + struct drivers_usb_acpi_config *usb_cfg = NULL; bool usb_audio_offload = false; /* Search through the devicetree for matching USB devices */ @@ -615,7 +615,7 @@ if (s_cfg->CnviBtAudioOffload && !usb_audio_offload) { printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver\n"); } - if (!s_cfg->CnviBtAudioOffload && usb_audio_offload) { + if (!s_cfg->CnviBtAudioOffload && usb_cfg && usb_audio_offload) { printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n"); usb_cfg->cnvi_bt_audio_offload = 0; } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 9706ac6..fa95e47 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -495,7 +495,7 @@ /* CNVi */ struct device *port = NULL; - struct drivers_usb_acpi_config *usb_cfg; + struct drivers_usb_acpi_config *usb_cfg = NULL; bool usb_audio_offload = false; /* Search through the devicetree for matching USB devices */ @@ -528,7 +528,7 @@ if (params->CnviBtAudioOffload && !usb_audio_offload) { printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver.\n"); } - if (!params->CnviBtAudioOffload && usb_audio_offload) { + if (!params->CnviBtAudioOffload && usb_cfg && usb_audio_offload) { printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n"); usb_cfg->cnvi_bt_audio_offload = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I169b6d3a979c4db78e7c0932a126d8b0a9306da7 Gerrit-Change-Number: 85026 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/fatcat: Add ISH support with FW_CONFIG toggle
by Subrata Banik (Code Review) 07 Nov '24

07 Nov '24

Attention is currently required from: Bora Guvendik, Li1 Feng, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84998?usp=email ) Change subject: mb/google/fatcat: Add ISH support with FW_CONFIG toggle ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/84998/comment/e37385b7_96c4fd04?us… : PS2, Line 469: static const struct pad_config ish_enable_pads[] = { > In the enable, D5&6 are for UART0 > /* GPP_D05: ISH_UART0_RXD */ > PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), > /* GPP_D06: ISH_UART0_TXD */ > PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), > > currently we don't use I3C, H14&15 can be moved out and set to NC. > > D07&08 also can be NC all the time. > /* GPP_D07: Not used */ > PAD_NC(GPP_D07, NONE), > /* GPP_D08: Not used */ > PAD_NC(GPP_D08, NONE), thank u, can you please advise Intel HW team to update the mapping doc to reflect the actual usage of these GPIO for fatcat. https://docs.google.com/spreadsheets/d/1EUSGpxgA4trxrCNIarwbo0HZMzXSZKqw/ed… -- To view, visit https://review.coreboot.org/c/coreboot/+/84998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Gerrit-Change-Number: 84998 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 07 Nov 2024 19:51:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Li1 Feng <li1.feng(a)intel.com>

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coreboot-gerrit November 2024